--- sys/conf/files.orig 2008-01-21 13:27:31.000000000 +0900 +++ sys/conf/files 2008-01-23 10:55:24.000000000 +0900 @@ -780,6 +780,7 @@ dev/mfi/mfi_cam.c optional mfip scbus dev/mii/acphy.c optional miibus | acphy dev/mii/amphy.c optional miibus | amphy +dev/mii/atphy.c optional miibus | atphy dev/mii/bmtphy.c optional miibus | bmtphy dev/mii/brgphy.c optional miibus | brgphy dev/mii/ciphy.c optional miibus | ciphy --- /dev/null 2008-01-23 11:00:02.000000000 +0900 +++ sys/dev/mii/atphy.c 2008-01-23 10:56:51.000000000 +0900 @@ -0,0 +1,393 @@ +/*- + * Copyright (c) 2008, Pyun YongHyeon + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Driver for the Attansic/Atheros F1 10/100/1000 PHY. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "miidevs.h" + +#include + +#include "miibus_if.h" + +static int atphy_probe(device_t); +static int atphy_attach(device_t); + +struct atphy_softc { + struct mii_softc mii_sc; + int mii_oui; + int mii_model; + int mii_rev; +}; + +static device_method_t atphy_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, atphy_probe), + DEVMETHOD(device_attach, atphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { NULL, NULL } +}; + +static devclass_t atphy_devclass; +static driver_t atphy_driver = { + "atphy", + atphy_methods, + sizeof(struct atphy_softc) +}; + +DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0); + +static int atphy_service(struct mii_softc *, struct mii_data *, int); +static void atphy_status(struct mii_softc *); +static void atphy_reset(struct mii_softc *); +static uint16_t atphy_anar(struct ifmedia_entry *); +static int atphy_auto(struct mii_softc *); + +static const struct mii_phydesc atphys[] = { + MII_PHY_DESC(ATHEROS, F1), + MII_PHY_END +}; + +static int +atphy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT)); +} + +static int +atphy_attach(device_t dev) +{ + struct atphy_softc *asc; + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + asc = device_get_softc(dev); + sc = &asc->mii_sc; + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = device_get_softc(sc->mii_dev); + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_inst = mii->mii_instance; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = atphy_service; + sc->mii_pdata = mii; + sc->mii_anegticks = MII_ANEGTICKS_GIGE; + + mii->mii_instance++; + + asc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); + asc->mii_model = MII_MODEL(ma->mii_id2); + asc->mii_rev = MII_REV(ma->mii_id2); + if (bootverbose) + device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", + asc->mii_oui, asc->mii_model, asc->mii_rev); + + + atphy_reset(sc); + + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return(0); +} + +static int +atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + uint16_t anar, bmcr, bmsr; + + switch (cmd) { + case MII_POLLSTAT: + /* + * If we're not polling our PHY instance, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + break; + + case MII_MEDIACHG: + /* + * If the media indicates a different PHY instance, + * isolate ourselves. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) { + bmcr = PHY_READ(sc, MII_BMCR); + PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); + return (0); + } + + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || + IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { + atphy_auto(sc); + break; + } + + bmcr = 0; + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_100_TX: + bmcr = BMCR_S100; + break; + case IFM_10_T: + bmcr = BMCR_S10; + break; + case IFM_NONE: + bmcr = PHY_READ(sc, MII_BMCR); + PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO | BMCR_PDOWN); + goto done; + default: + return (EINVAL); + } + + anar = 0; + if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { + bmcr |= BMCR_FDX; + /* Enable pause. */ + anar |= (3 << 10); + } + + PHY_WRITE(sc, MII_100T2CR, 0); + anar |= atphy_anar(ife); + PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA); + + /* + * Reset the PHY so all changes take effect. + */ + PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET); +done: + break; + + case MII_TICK: + /* + * If we're not currently selected, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + /* + * Only used for autonegotiation. + */ + if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { + sc->mii_ticks = 0; + break; + } + + /* + * check for link. + * Read the status register twice; BMSR_LINK is latch-low. + */ + bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); + if (bmsr & BMSR_LINK) { + sc->mii_ticks = 0; + break; + } + + /* Announce link loss right after it happens. */ + if (sc->mii_ticks++ == 0) + break; + if (sc->mii_ticks <= sc->mii_anegticks) + return (0); + + sc->mii_ticks = 0; + atphy_auto(sc); + break; + } + + /* Update the media status. */ + atphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +atphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + uint32_t bmsr, bmcr, ssr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); + if ((bmsr & BMSR_LINK) != 0) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(sc, MII_BMCR); + if ((bmcr & BMCR_ISO) != 0) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if ((bmcr & BMCR_LOOP) != 0) + mii->mii_media_active |= IFM_LOOP; + + ssr = PHY_READ(sc, ATPHY_SSR); + if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + if ((ssr & ATPHY_SSR_1000MBS) != 0) + mii->mii_media_active |= IFM_1000_T; + else if ((ssr & ATPHY_SSR_100MBS) != 0) + mii->mii_media_active |= IFM_100_TX; + else + mii->mii_media_active |= IFM_10_T; + + if ((ssr & ATPHY_SSR_DUPLEX) != 0) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + + /* XXX Master/Slave, Flow-control */ +} + +static void +atphy_reset(struct mii_softc *sc) +{ + struct atphy_softc *asc; + uint32_t reg; + int i; + + asc = (struct atphy_softc *)sc; + + /* Take PHY out of power down mode. */ + PHY_WRITE(sc, 29, 0x29); + PHY_WRITE(sc, 30, 0); + + reg = PHY_READ(sc, ATPHY_SCR); + /* Enable automatic crossover. */ + reg |= ATPHY_SCR_AUTO_X_MODE; + /* Disable power down. */ + reg &= ~ATPHY_SCR_MAC_PDOWN; + /* Enable CRS on Tx. */ + reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; + /* Auto correction for reversed cable polarity. */ + reg |= ATPHY_SCR_POLARITY_REVERSAL; + PHY_WRITE(sc, ATPHY_SCR, reg); + + atphy_auto(sc); + + for (i = 0; i < 1000; i++) { + DELAY(1); + if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) + break; + } +} + +static uint16_t +atphy_anar(struct ifmedia_entry *ife) +{ + uint16_t anar; + + anar = 0; + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; + return (anar); + case IFM_1000_T: + return (anar); + case IFM_100_TX: + anar = ANAR_TX_FD | ANAR_TX; + break; + case IFM_10_T: + anar = ANAR_10_FD | ANAR_10; + break; + default: + return (0); + } + + if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { + if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) + anar &= ~ANAR_TX; + else + anar &= ~ANAR_10; + } else { + if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) + anar &= ~ANAR_TX_FD; + else + anar &= ~ANAR_10_FD; + } + + return (anar); +} + +static int +atphy_auto(struct mii_softc *sc) +{ + uint16_t anar; + + anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities); + PHY_WRITE(sc, MII_ANAR, anar | (3 << 10) | ANAR_CSMA); + if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) + PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | + GTCR_ADV_1000THDX); + PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN); + + return (EJUSTRETURN); +} --- /dev/null 2008-01-23 11:00:02.000000000 +0900 +++ sys/dev/mii/atphyreg.h 2008-01-23 10:55:24.000000000 +0900 @@ -0,0 +1,63 @@ +/*- + * Copyright (c) 2008, Pyun YongHyeon + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _DEV_MII_ATPHYREG_H_ +#define _DEV_MII_ATPHYREG_H_ + +/* + * Registers for the Atheros/Attansic Gigabit PHY. + */ + +/* Special Control Register */ +#define ATPHY_SCR 0x10 +#define ATPHY_SCR_JABBER_DISABLE 0x0001 +#define ATPHY_SCR_POLARITY_REVERSAL 0x0002 +#define ATPHY_SCR_SQE_TEST 0x0004 +#define ATPHY_SCR_MAC_PDOWN 0x0008 +#define ATPHY_SCR_CLK125_DISABLE 0x0010 +#define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 +#define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 +#define ATPHY_SCR_AUTO_X_1000T 0x0040 +#define ATPHY_SCR_AUTO_X_MODE 0x0060 +#define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 +#define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 +#define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 +#define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 +#define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 + +/* Special Status Register. */ +#define ATPHY_SSR 0x11 +#define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 +#define ATPHY_SSR_DUPLEX 0x2000 +#define ATPHY_SSR_SPEED 0xC000 +#define ATPHY_SSR_10MBS 0x0000 +#define ATPHY_SSR_100MBS 0x4000 +#define ATPHY_SSR_1000MBS 0x8000 + +#endif /* _DEV_MII_IP1000PHYREG_H_ */ --- sys/dev/mii/miidevs.orig 2007-10-29 11:17:44.000000000 +0900 +++ sys/dev/mii/miidevs 2008-01-23 10:55:24.000000000 +0900 @@ -51,6 +51,7 @@ oui ALTIMA 0x0010a9 Altima Communications oui AMD 0x00001a Advanced Micro Devices +oui ATHEROS 0x001374 Atheros Communications oui BROADCOM 0x001018 Broadcom Corporation oui CICADA 0x0003F1 Cicada Semiconductor oui DAVICOM 0x00606e Davicom Semiconductor @@ -112,6 +113,9 @@ model AMD 79c978 0x0039 Am79c978 HomePNA PHY model xxAMD 79C873 0x0000 Am79C873/DM9101 10/100 media interface +/* Atheros Communications/Attansic PHYs. */ +model ATHEROS F1 0x0001 Atheros F1 Gigabit PHY + /* Broadcom Corp. PHYs. */ model BROADCOM 3C905B 0x0012 3c905B 10/100 internal PHY model BROADCOM 3C905C 0x0017 3c905C 10/100 internal PHY