/*-
 * Copyright (c) 2008 Wojciech A. Koszek <wkoszek@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD$
 */

/*
 * Reset vectors differ between two processor versions.
 */
#define AVR32A_RESET	0x8000000
#define AVR32B_RESET	0xA000000

#define	AVR32_OFFSET_UNREC	0x00	/* Unrecoverable exception */
#define AVR32_OFFSET_TLBMH	0x04	/* TLB Multiple hit exception */
#define AVR32_OFFSET_BEDF	0x08	/* Bus error data fetch */
#define AVR32_OFFSET_BEIF	0x0C	/* Bus error instruction fetch */
#define AVR32_OFFSET_NMI	0x10	/* NMI */
#define AVR32_OFFSET_IADDR	0x14	/* Instruction address. */
#define AVR32_OFFSET_ITLBM	0x50	/* ITLB Miss */
#define AVR32_OFFSET_ITLBP	0x18	/* ITLB Procestion */
#define AVR32_OFFSET_BP		0x1C	/* Breakpoint */
#define AVR32_OFFSET_ILOP	0x20	/* Illegal Opcode */
#define AVR32_OFFSET_UIMPL	0x24	/* Unimplemented instruction */
#define AVR32_OFFSET_PVIOL	0x28	/* Privilege violation */
#define AVR32_OFFSET_FP		0x2C	/* Floating-point */
#define AVR32_OFFSET_CPA	0x30	/* Coprocessor absent */
#define AVR32_OFFSET_SVCALL	0x100	/* Supervisor call */
#define AVR32_OFFSET_DAR	0x34	/* Data Address (Read) */
#define AVR32_OFFSET_DAW	0x38	/* Data Address (Write) */
#define AVR32_OFFSET_DTLBMR	0x60	/* DTLB Miss (Read) */
#define AVR32_OFFSET_DTLBMW	0x70	/* DTLB Miss (Write) */
#define AVR32_OFFSET_DTLBPR	0x3C	/* DTLB Protection (Read) */
#define AVR32_OFFSET_DTLBPW	0x40	/* DTLB Protection (Write) */
#define AVR32_OFFSET_DTLBM	0x44	/* DTLB Modified */

struct avr32a_trapframe {
	register_t pc;
	register_t lr;
	register_t sp_app;
	register_t r12;
	register_t r11;
	register_t r10;
	register_t r9;
	register_t r8;
	register_t r7;
	register_t r6;
	register_t r5;
	register_t r4;
	register_t r3;
	register_t r2;
	register_t r1;
	register_t r0;
	register_t sr;
};