/*- * Copyright (c) 2008 Wojciech A. Koszek * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * The AVR32 Virtual memory layout * ------------------------------- * * Priviledged mode Unprivileged Mode * +---------------------------+ 0xFFFFFFFF +---------------------------+ * | P4: 512MB system space | | | * | non-cachable | | | * +---------------------------+ 0xE0000000 + Unaccessible space | * | P3: 512MB translated | | Access error | * | cacheable | | | * +---------------------------+ 0xC0000000 + | * | P2: 512MB non-translated | | | * | non-cacheable | | | * +---------------------------+ 0xA0000000 + | * | P1: 512MB non-translated | | | * | cacheable | | | * +---------------------------+ 0x80000000 +---------------------------+ * | P0: 2GB translated | | U0: 2GB translated | * | cacheable | | cacheable | * +---------------------------+ 0x00000000 +---------------------------+ */ #define AVR32_P0SEG_START 0x00000000 #define AVR32_P0SEG_END 0x7FFFFFFF #define AVR32_P1SEG_START 0x80000000 #define AVR32_P1SEG_END 0x9FFFFFFF #define AVR32_P2SEG_START 0xA0000000 #define AVR32_P1SEG_END 0xBFFFFFFF #define AVR32_P3SEG_START 0xC0000000 #define AVR32_P3SEG_END 0xDFFFFFFF #define AVR32_P4SEG_START 0xE0000000 #define AVR32_P4SEG_END 0xFFFFFFFF #define AVR32_U0SEG_START AVR32_U0SEG_START #define AVR32_U0SEG_END AVR32_U0SEG_END /*-----------------------------------------------------------------------*/ /* * TLBEHI Register: * * 31 10 9 8 7 0 * +---------------------------------------+---+---+------+ * | VPN | V | I | ASID | * +---------------------------------------+---+---+------+ */ #define AVR32_TLBEHI_VPN(x) ((x) >> 10 & 0x3fffff) /* V. Page Number*/ #define AVR32_TLBEHI_V(x) ((x) & (1 << 9)) /* Valid */ #define AVR32_TLBEHI_I(x) ((x) & (1 << 8)) /* Instr. TLB */ #define AVR32_TKBEHI_ASID(x) ((x) & 0xff) /* ASID */ /* * TLBELO Register: * * 31 10 9 8 7 6 4 3 2 1 0 * +------------------------+---+---+---+-----+----+---+---+ * | PFN | C | G | B | AP | SZ | D | W | * +------------------------+---+---+---+-----+----+---+---+ */ #define AVR32_TLBELO_W(x) ((x) & (1 << 0)) /* write through*/ #define AVR32_TLBELO_D(x) ((x) & (1 << 1)) /* dirty */ #define AVR32_TLBELO_SZ(x) ((x) &((1 << 2) \ (1 << 3))) /* page size */ #define AVR32_TLBELO_AP(x) ((x) &((1 << 4)| \ (1 << 5)| \ (1 << 6))) /* access perm. */ #define AVR32_TLBELO_B(x) ((x) & (1 << 7)) /* bufferable */ #define AVR32_TLBELO_G(x) ((x) & (1 << 8)) /* global bit */ #define AVR32_TLBELO_C(x) ((x) & (1 << 9)) /* cacheable */ #define AVR32_TLBLO_PFN(x) (((x) >> 10) & 0x3fffff) /* * AVR32 Protected mode AP interpretation. Reading is always * allowed in protected mode, thus AVR32_AP_PMISR() result doesn't * really matter. */ #define AVR32_AP_PMISX(x) ((x & 1) == 1) #define AVR32_AP_PMISW(x) ((x & 2) == 2) #define AVR32_AP_PMISR(x) ((x & 4) == 4) /* * Check the highest bit for validity, since AP can't be equal to 000b, * 001b, 010b, 011b within unpriviledged mode. Reading is always * allowed here as well. */ #define _AVR32_AP_UM_VALID(x) (x & (1 << 2)) #define AVR32_AP_UMISX(x) ((x & 1) && _AVR32_AP_UM_VALID((x))) #define AVR32_AP_UMISW(x) ((x & 2) && _AVR32_AP_UM_VALID((x))) #define AVR32_AP_UMISR(x) ((x & 4) && _AVR32_AP_UM_VALID((x))) /* * AVR32_TLBELO_SZ interpretation. */ static uint32_t __inline avr32_pgsize_get(void) { uint32_t tlblo; uint32_t sz; tlblo = avr32_reg_get(AVR32_REG_TLBLO); sz = AVR32_TLBELO_SZ(tlblo); KASSERT(sz >= 0 && sz <= 3); if (sz == 0) return (1024); else if (sz == 1) return (4096); else if (sz == 2) return (65536); else if (sz == 3) return (1048576); return (0); } /* * MMUCR Register: * * 31 26 25 20 19 14 13 8 7 5 4 3 2 1 0 * +-------+--------+-----+------+-----+---+---+---+---+---+ * | IRP | ILA | DRP | DLA | --- | S | N | I | M | E | * +-------+--------+-----+------+-----+---+---+---+---+---+ */ #define AVR32_MMUCR_E(x) (x & (1 << 0)) /* Enabled */ #define AVR32_MMUCR_M(x) (x & (1 << 1)) /* Mode. */ #define AVR32_MMUCR_I(x) (x & (1 << 2)) /* Invalidate. */ #define AVR32_MMUCR_N(x) (x & (1 << 3)) /* Not Found. */ #define AVR32_MMUCR_S(x) (x & (1 << 4)) /* Segmentation enabled. */ #define AVR32_MMUCR_RSV(x) (((x) >> 5) & 0x07) /* Data TLB Lockdown Amount. */ #define AVR32_MMUCR_DLA(x) (((x) >> 8) & 0x3f) /* Data TLB Replacement Pointer. */ #define AVR32_MMUCR_DRP(x) (((x) >> 14) & 0x3f) /* Instruction TLB Lockdown Amount. */ #define AVR32_MMUCR_ILA(x) (((x) >> 20) & 0x3f) /* Instruction TLB Replacement Pointer. */ #define AVR32_MMUCR_IRP(x) (((x) >> 26) & 0x3f) /* * AVR32_MMUCR_M interpretation. */ #define AVR32_MMU_PVM 0 /* Private virtual memory */ #define AVR32_MMU_SVM 1 /* Shared virtual memory */ /* * Performance counter control register: * * 31 24 23 18 17 12 10 8 7 6 4 3 2 1 0 * +-------+--------+-------+---+-----+---+-----+---+---+---+---+ * | ----- | CONF1 | CONF0 | - | F | - | IE | S | C | R | E | * +-------+--------+-------+---+-----+---+-----+---+---+---+---+ */ #define AVR32_PCCR_E 1 << 0 /* Clock counter enable */ #define AVR32_PCCR_R 1 << 1 /* Performance counter reset */ #define AVR32_PCCR_C 1 << 2 /* Clock counter reset */ #define AVR32_PCCR_S 1 << 3 /* Clock counter scaler */ #define AVR32_PCCR_IE0 1 << 4 /* Interrupt enable */ #define AVR32_PCCR_IE1 1 << 5 #define AVR32_PCCR_IE2 1 << 6 #define AVR32_PCCR_RSV0 1 << 7 /* Reserved */ #define AVR32_PCCR_F0 1 << 8 /* Interrupt flag */ #define AVR32_PCCR_F1 1 << 9 #define AVR32_PCCR_F2 1 << 10 #define AVR32_PCCR_RSV1 1 << 11 /* Reserved */ #define AVR32_PCCR_CONF0 0x3f << 12 /* What goes to PCNT0 */ #define AVR32_PCCR_CONF1 0x3f << 18 /* What goes to PCNT1 */ #define AVR32_PCCR_RSV2 0xff << 24 /* Reserved */ #define AVR32_PEV_ICACHEMISS 0x0 #define AVR32_PEV_IFETCHSTALL 0x1 #define AVR32_PEV_DHSTALL 0x2 #define AVR32_PEV_ITLBMISS 0x3 #define AVR32_PEV_DTLBMISS 0x4 #define AVR32_PEV_BIEX 0x5 #define AVR32_PEV_BMISP 0x6 #define AVR32_PEV_IEX 0x7 #if 0 #define AVR32_PEV_ 0x8 #define AVR32_PEV_ 0x #define AVR32_PEV_ 0x 0x8 Stall due to data cache write buffers full. Incremented once for each occurrence. 0x9 Stall due to data cache write buffers full. Incremented every cycle the condition is true. Stall due to data cache read miss. Incremented once for each data access to a cacheable memory area 0xA that did not hit in the cache. Stall due to data cache read miss. Incremented every cycle the pipeline is stalled due to a data access to a 0xB cacheable memory area that did not hit in the cache. 0xC Write access counter. Incremented once for each write access. 0xD Write access counter. Incremented every cycle a write access is ongoing. 0xE Read access counter. Incremented once for each read access. 0xF Read access counter. Incremented every cycle a read access is ongoing. 0x10 Cache stall counter. Incremented once for each read or write access that stalls. Cache stall counter. Incremented every cycle a read or write access stalls. Write accesses are counted 0x11 only until the write is put in the write buffer. 0x12 Cache access counter. Incremented once for each read or write access. Cache access counter. Incremented every cycle a read or write access is ongoing. Write accesses are 0x13 counted only until the write is put in the write buffer. 0x14 Data cache line writeback. Incremented once when a line containing dirty data is replaced in the cache. 0x15 Accumulator cache hit 0x16 Accumulator cache miss 0x17 BTB hit. Incremented once per hit occurrence. 0x18 Micro-ITLB miss. Incremented once per miss occurrence. 0x19 Micro-DTLB miss. Incremented once per miss occurrence. Other Reserved. #endif