/*- * Copyright (c) 2008 Wojciech A. Koszek * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _AVR32_H_ #define _AVR32_H_ /*------------------------------------------------------------------------- * AVR32 Status register: high halfword */ #define AVR32_STR_GM (1 << 0) /* Global Interrupt Mask */ #define AVR32_STR_I0M (1 << 1) /* Interrupt Level 0 Mask */ #define AVR32_STR_I1M (1 << 2) /* Interrupt Level 1 Mask */ #define AVR32_STR_I2M (1 << 3) /* Interrupt Level 2 Mask */ #define AVR32_STR_I3M (1 << 4) /* Interrupt Level 3 Mask */ #define AVR32_STR_EM (1 << 5) /* Exception Mask */ #define AVR32_STR_M0 (1 << 6) /* Mode Bit 0 */ #define AVR32_STR_M1 (1 << 7) /* Mode Bit 1 */ #define AVR32_STR_M2 (1 << 8) /* Mode Bit 2 */ #define AVR32_STR_RSV0 (1 << 9) /* Reserved */ #define AVR32_STR_D (1 << 10) /* Debug State */ #define AVR32_STR_DM (1 << 11) /* Debug State Mask */ #define AVR32_STR_J (1 << 12) /* Java State */ #define AVR32_STR_H (1 << 13) /* Java Handle */ #define AVR32_STR_RSV1 (1 << 14) /* Reserved */ #define AVR32_STR_RSV2 (1 << 15) /* Reserved */ /*------------------------------------------------------------------------- * AVR32 Status register: low halfword */ #define AVR32_STR_C (1 << 0) /* Carry */ #define AVR32_STR_Z (1 << 1) /* Zero */ #define AVR32_STR_N (1 << 2) /* Sign */ #define AVR32_STR_V (1 << 3) /* Overflow */ #define AVR32_STR_Q (1 << 4) /* Saturation */ #define AVR32_STR_L (1 << 5) /* Lock */ #define AVR32_STR_RSV0 (1 << 6) /* Reserved */ #define AVR32_STR_RSV1 (1 << 7) /* Reserved */ #define AVR32_STR_RSV2 (1 << 8) /* Reserved */ #define AVR32_STR_RSV3 (1 << 9) /* Reserved */ #define AVR32_STR_RSV4 (1 << 10) /* Reserved */ #define AVR32_STR_RSV5 (1 << 11) /* Reserved */ #define AVR32_STR_RSV6 (1 << 12) /* Reserved */ #define AVR32_STR_RSV7 (1 << 13) /* Reserved */ #define AVR32_STR_T (1 << 14) /* Scratch */ #define AVR32_STR_R (1 << 15) /* Register Remap Enable */ /*------------------------------------------------------------------------- * M0/M1/M2 register mask. */ #define AVR32_MODE_MASK (AVR32_STR_M0|AVR32_STR_M1|AVR32_STR_M2) #define AVR32_MODE_NMI (AVR32_STR_M2 | AVR32_STR_M1 | AVR32_STR_M0 ) #define AVR32_MODE_EX (AVR32_STR_M2 | AVR32_STR_M1 | 0 ) #define AVR32_MODE_IL3 (AVR32_STR_M2 | 0 | AVR32_STR_M0 ) #define AVR32_MODE_IL2 (AVR32_STR_M2 | 0 | 0 ) #define AVR32_MODE_IL1 ( 0 | AVR32_STR_M1 | AVR32_STR_M0 ) #define AVR32_MODE_IL0 ( 0 | AVR32_STR_M1 | 0 ) #define AVR32_MODE_SV ( 0 | 0 | AVR32_STR_M0 ) #define AVR32_MODE_AP ( 0 | 0 | 0 ) /*------------------------------------------------------------------------- * AVR32 Config 0 register */ #define AVR32_CR0_R (1 << 0) /* R/M/Wr instr. implemented */ #define AVR32_CR0_D (1 << 1) /* DSP instr. implemented */ #define AVR32_CR0_S (1 << 2) /* SIMD instr. implemented */ #define AVR32_CR0_O (1 << 3) /* On-Chip Debug implemented */ #define AVR32_CR0_P (1 << 4) /* Perf. counters implemented */ #define AVR32_CR0_J (1 << 5) /* Java extension implemented */ #define AVR32_CR0_F (1 << 6) /* FP unit implemented */ #define AVR32_CR0_MMUT0 (1 << 7) /* MMU type */ #define AVR32_CR0_MMUT1 (1 << 8) #define AVR32_CR0_MMUT2 (1 << 9) #define AVR32_CR0_AR0 (1 << 10) /* Archirecture revision */ #define AVR32_CR0_AR1 (1 << 11) #define AVR32_CR0_AR2 (1 << 12) #define AVR32_CR0_AT0 (1 << 13) /* Architecture type */ #define AVR32_CR0_AT1 (1 << 14) #define AVR32_CR0_AT2 (1 << 15) #define AVR32_CR0_PREV0 (1 << 16) /* Processor revision */ #define AVR32_CR0_PREV1 (1 << 17) #define AVR32_CR0_PREV2 (1 << 18) #define AVR32_CR0_PREV3 (1 << 19) #define AVR32_CR0_RSV0 (1 << 20) /* Reserved */ #define AVR32_CR0_RSV1 (1 << 21) #define AVR32_CR0_RSV2 (1 << 22) #define AVR32_CR0_RSV3 (1 << 23) #define AVR32_CR0_PRID0 (1 << 24) /* Processor ID */ #define AVR32_CR0_PRID1 (1 << 25) #define AVR32_CR0_PRID2 (1 << 26) #define AVR32_CR0_PRID3 (1 << 27) #define AVR32_CR0_PRID4 (1 << 28) #define AVR32_CR0_PRID5 (1 << 29) #define AVR32_CR0_PRID6 (1 << 30) #define AVR32_CR0_PRID7 (1 << 31) #define AVR32_MASK_MMUT \ (AVR32_CR0_MMUT0|AVR32_CR0_MMUT1|AVR32_CR0_MMUT2) #define AVR32_MASK_AR \ (AVR32_CR0_AR0|AVR32_CR0_AR1|AVR32_CR0_AR2) #define AVR32_MASK_AT \ (AVR32_CR0_AT0|AVR32_CR0_AT1|AVR32_CR0_AT2) #define AVR32_MASK_PREV \ (AVR32_CR0_PREV0|AVR32_CR0_PREV1|AVR32_CR0_PREV2| \ AVR32_CR0_PREV2) #define AVR32_MASK_RSV \ (AVR32_CR0_RSV0|AVR32_CR0_RSV1|AVR32_CR0_RSV2| \ AVR32_CR0_RSV2) #define AVR32_MASK_PRID \ (AVR32_CR0_PRID0|AVR32_CR0_PRID1|AVR32_CR0_PRID2| \ AVR32_CR0_PRID3|AVR32_CR0_PRID4|AVR32_CR0_PRID5| \ AVR32_CR0_PRID6|AVR32_CR0_PRID7) /* * AVR32_MASK_AR interpretation */ #define AVR32_AR_AR0 0 #define AVR32_AR_AR1 1 #define AVR32_AR_AR2 2 /* * AVR32_MASK_AT interpretation */ #define AVR32_AT_AVR32A 0 #define AVR32_AT_AVR32B 1 /*-------------------------------------------------------------------------- * AVR32 Config 1 register */ #define AVR32_CR1_DASS0 (1 << 0) /* Associativity of DCACHE */ #define AVR32_CR1_DASS1 (1 << 1) #define AVR32_CR1_DASS2 (1 << 2) #define AVR32_CR1_DLSZ0 (1 << 3) /* Line size in DCACHE */ #define AVR32_CR1_DLSZ1 (1 << 4) #define AVR32_CR1_DLSZ2 (1 << 5) #define AVR32_CR1_DSET0 (1 << 6) /* Number of sets in DCACHE */ #define AVR32_CR1_DSET1 (1 << 7) #define AVR32_CR1_DSET2 (1 << 8) #define AVR32_CR1_DSET3 (1 << 9) #define AVR32_CR1_IASS0 (1 << 10) /* Associativity of ICACHE */ #define AVR32_CR1_IASS1 (1 << 11) #define AVR32_CR1_IASS2 (1 << 12) #define AVR32_CR1_ILSZ0 (1 << 13) /* Line size in ICACHE */ #define AVR32_CR1_ILSZ1 (1 << 14) #define AVR32_CR1_ILSZ2 (1 << 15) #define AVR32_CR1_ISET0 (1 << 16) /* Number of sets in ICACHE */ #define AVR32_CR1_ISET1 (1 << 17) #define AVR32_CR1_ISET2 (1 << 18) #define AVR32_CR1_ISET3 (1 << 19) #define AVR32_CR1_DMMUSZ0 (1 << 20) /* Nr. of entries in the DMMU */ #define AVR32_CR1_DMMUSZ1 (1 << 21) #define AVR32_CR1_DMMUSZ2 (1 << 22) #define AVR32_CR1_DMMUSZ3 (1 << 23) #define AVR32_CR1_DMMUSZ4 (1 << 24) #define AVR32_CR1_DMMUSZ5 (1 << 25) #define AVR32_CR1_IMMUSZ0 (1 << 26) /* Nr. of entries in the IMMU */ #define AVR32_CR1_IMMUSZ1 (1 << 27) #define AVR32_CR1_IMMUSZ2 (1 << 28) #define AVR32_CR1_IMMUSZ3 (1 << 29) #define AVR32_CR1_IMMUSZ4 (1 << 30) #define AVR32_CR1_IMMUSZ5 (1 << 31) #define AVR32_CR1_MASK_DASS \ (AVR32_CR1_DASS0|AVR32_CR1_DASS1|AVR32_CR1_DASS2) #define AVR32_CR1_MASK_DLSZ \ (AVR32_CR1_DLSZ0| AVR32_CR1_DLSZ1| AVR32_CR1_DLSZ2) #define AVR32_CR1_MASK_DSET \ (AVR32_CR1_DSET0|AVR32_CR1_DSET1|AVR32_CR1_DSET2|AVR32_CR1_DSET3) #define AVR32_CR1_MASK_IASS \ (AVR32_CR1_IASS0|AVR32_CR1_IASS1|AVR32_CR1_IASS2) #define AVR32_CR1_MASK_ILSZ \ (AVR32_CR1_ILSZ0|AVR32_CR1_ILSZ1|AVR32_CR1_ILSZ2) #define AVR32_CR1_MASK_ISET \ (AVR32_CR1_ISET0|AVR32_CR1_ISET1|AVR32_CR1_ISET2|AVR32_CR1_ISET3) #define AVR32_CR1_MASK_DMMUSZ \ (AVR32_CR1_DMMUSZ0|AVR32_CR1_DMMUSZ1|AVR32_CR1_DMMUSZ2| \ AVR32_CR1_DMMUSZ3|AVR32_CR1_DMMUSZ4|AVR32_CR1_DMMUSZ5) #define AVR32_CR1_MASK_IMMUSZ \ (AVR32_CR1_IMMUSZ0|AVR32_CR1_IMMUSZ1|AVR32_CR1_IMMUSZ2| \ AVR32_CR1_IMMUSZ3|AVR32_CR1_IMMUSZ4|AVR32_CR1_IMMUSZ5) /* * Interpretation of cache information from: * AVR32_CR1_MASK_ISET, AVR32_CR1_MASK_IASS, AVR32_CR1_MASK_ILSZ, * AVR32_CR1_MASK_DSET, AVR32_CR1_MASK_DLSZ, AVR32_CR1_MASK_DASS * * AVR32_[DI]CACHE_SETNR: number of sets * AVR32_[DI]CACHE_ASS: associativity * AVR32_[DI]CACHE_LSZ: line size */ #define AVR32_ICACHE_SETNR(x) (1 << (x)) /* number of sets */ #define AVR32_ICACHE_ASS(x) (1 << (x)) /* associativity */ #define AVR32_ICACHE_LSZ(x) (2 << (x)) /* line size */ #define AVR32_DCACHE_SETNR(x) (1 << (x)) #define AVR32_DCACHE_ASS(x) (1 << (x)) #define AVR32_DCACHE_LSZ(x) (2 << (x)) /*-------------------------------------------------------------------------- * AVR32 Register numbers. */ #define AVR32_REG_SR 0 /* Status Reg. */ #define AVR32_REG_EVBA 1 /* Exception Vector Base Address */ #define AVR32_REG_ACBA 2 /* Application Call Base Address */ #define AVR32_REG_CPUCR 3 /* CPU Control Reg. */ #define AVR32_REG_ECR 4 /* Exception Cause Reg. */ #define AVR32_REG_RSR_SUP 5 /* Ret. Status Reg. for Supervis. */ #define AVR32_REG_RSR_INT0 6 /* Ret. Status Reg. for INT */ #define AVR32_REG_RSR_INT1 7 /* Ret. Status Reg. for INT */ #define AVR32_REG_RSR_INT2 8 /* Ret. Status Reg. for INT */ #define AVR32_REG_RSR_INT3 9 /* Ret. Status Reg. for INT */ #define AVR32_REG_RSR_EX 10 /* Ret. Status Reg. for Exception */ #define AVR32_REG_RSR_NMI 11 /* Ret. Status Reg. for NMI */ #define AVR32_REG_RSR_DBG 12 /* Ret. Status Reg. for Debug */ #define AVR32_REG_RAR_SUP 13 /* Ret. Addr. Reg. for Supervis. */ #define AVR32_REG_RAR_INT0 14 /* Ret. Addr. Reg. for INT */ #define AVR32_REG_RAR_INT1 15 /* Ret. Addr. Reg. for INT */ #define AVR32_REG_RAR_INT2 16 /* Ret. Addr. Reg. for INT */ #define AVR32_REG_RAR_INT3 17 /* Ret. Addr. Reg. for INT */ #define AVR32_REG_RAR_EX 18 /* Ret. Addr. Reg. for Exception */ #define AVR32_REG_RAR_NMI 19 /* Ret. Addr. Reg. for NMI */ #define AVR32_REG_RAR_DBG 20 /* Ret. Addr. Reg. for Debug */ #define AVR32_REG_JECR 21 /* Java Exception Cause Reg. */ #define AVR32_REG_JOSP 22 /* Java Operand Stack Pointer */ #define AVR32_REG_JAVA_LV0 23 /* Java Local Variable 0 */ #define AVR32_REG_JAVA_LV1 24 /* Java Local Variable 1 */ #define AVR32_REG_JAVA_LV2 25 /* Java Local Variable 2 */ #define AVR32_REG_JAVA_LV3 26 /* Java Local Variable 3 */ #define AVR32_REG_JAVA_LV4 27 /* Java Local Variable 4 */ #define AVR32_REG_JAVA_LV5 28 /* Java Local Variable 5 */ #define AVR32_REG_JAVA_LV6 29 /* Java Local Variable 6 */ #define AVR32_REG_JAVA_LV7 30 /* Java Local Variable 7 */ #define AVR32_REG_JTBA 31 /* Java Trap Base Address */ #define AVR32_REG_JBCR 32 /* Java Write Barrier Cont. Reg. */ #if 0 /* Reserved range */ #define AVR32_REG_Reserved 33-63 /* Reserved for future use */ #endif #define AVR32_REG_CONFIG0 64 /* Configuration register 0 */ #define AVR32_REG_CONFIG1 65 /* Configuration register 1 */ #define AVR32_REG_COUNT 66 /* Cycle Counter register */ #define AVR32_REG_COMPARE 67 /* Compare register */ #define AVR32_REG_TLBEHI 68 /* MMU TLB Entry High */ #define AVR32_REG_TLBELO 69 /* MMU TLB Entry Low */ #define AVR32_REG_PTBR 70 /* MMU Page Table Base Reg. */ #define AVR32_REG_TLBEAR 71 /* MMU TLB Exception Addr. Reg. */ #define AVR32_REG_MMUCR 72 /* MMU Control Reg. */ #define AVR32_REG_TLBARLO 73 /* MMU TLB Accessed Reg. Low */ #define AVR32_REG_TLBARHI 74 /* MMU TLB Accessed Reg. High */ #define AVR32_REG_PCCNT 75 /* Perf. Clock Counter */ #define AVR32_REG_PCNT0 76 /* Perf. Counter 0 */ #define AVR32_REG_PCNT1 77 /* Perf. Counter 1 */ #define AVR32_REG_PCCR 78 /* Perf. Counter Control Reg. */ #define AVR32_REG_BEAR 79 /* Bus Error Address Reg. */ #define AVR32_REG_MPUAR0 80 /* MPU Address Reg. region 0 */ #define AVR32_REG_MPUAR1 81 /* MPU Address Reg. region 1 */ #define AVR32_REG_MPUAR2 82 /* MPU Address Reg. region 2 */ #define AVR32_REG_MPUAR3 83 /* MPU Address Reg. region 3 */ #define AVR32_REG_MPUAR4 84 /* MPU Address Reg. region 4 */ #define AVR32_REG_MPUAR5 85 /* MPU Address Reg. region 5 */ #define AVR32_REG_MPUAR6 86 /* MPU Address Reg. region 6 */ #define AVR32_REG_MPUAR7 87 /* MPU Address Reg. region 7 */ #define AVR32_REG_MPUPSR0 88 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUPSR1 89 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUPSR2 90 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUPSR3 91 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUPSR4 92 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUPSR5 93 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUPSR6 94 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUPSR7 95 /* MPU Priv. Select Reg. region */ #define AVR32_REG_MPUCRA 96 /* MPU Cacheable Reg. A */ #define AVR32_REG_MPUCRB 97 /* MPU Cacheable Reg. B */ #define AVR32_REG_MPUBRA 98 /* MPU Bufferable Reg. A */ #define AVR32_REG_MPUBRB 99 /* MPU Bufferable Reg. B */ #define AVR32_REG_MPUAPRA 100 /* MPU Access Permission Reg. A */ #define AVR32_REG_MPUAPRB 101 /* MPU Access Permission Reg. B */ #define AVR32_REG_MPUCR 102 /* MPU Control Reg. */ /* * The rest isn't used. */ #if 0 #define AVR32_REG_Reserved 103-191 /* Reserved for future use */ #define AVR32_REG_IMPL 192-255 /* IMPLEMENTATION DEFINED */ #endif static uint32_t __inline avr32_reg_get(u_char reg_num) { uint32_t r; return (r); } #endif