Index: arch/powerpc/conf/files.ibm4xx
===================================================================
RCS file: /opt/r/NetBSD.cvs/src/sys/arch/powerpc/conf/files.ibm4xx,v
retrieving revision 1.3
diff -u -r1.3 files.ibm4xx
--- arch/powerpc/conf/files.ibm4xx	23 Nov 2002 19:42:41 -0000	1.3
+++ arch/powerpc/conf/files.ibm4xx	1 Jul 2003 19:29:54 -0000
@@ -31,6 +31,11 @@
 attach	emac at opb
 file	arch/powerpc/ibm4xx/dev/if_emac.c	emac
 
+# On-chip IIC device(s)
+device	iic {[addr = -1], [irq = -1]}
+attach	iic at opb
+file	arch/powerpc/ibm4xx/dev/iic.c		iic
+
 # Watchdog timer
 device	wdog: sysmon_wdog
 attach	wdog at opb
Index: arch/powerpc/ibm4xx/dev/iicreg.h
===================================================================
RCS file: /opt/r/NetBSD.cvs/src/sys/arch/powerpc/ibm4xx/dev/iicreg.h,v
retrieving revision 1.2
diff -u -r1.2 iicreg.h
--- arch/powerpc/ibm4xx/dev/iicreg.h	1 May 2003 09:05:56 -0000	1.2
+++ arch/powerpc/ibm4xx/dev/iicreg.h	1 Jul 2003 19:29:54 -0000
@@ -38,7 +38,18 @@
 #ifndef _IBM4XX_IICREG_H_
 #define	_IBM4XX_IICREG_H_
 
-/* IIC Registers */
+/* IIC FIFO buffer size */
+#define IIC_FIFO_BUFSIZE	(4)
+
+/*
+ * definitions for IIC Addressing Mode
+ */
+#define	IIC_LADR_SHFT		1	/* LowAddr (7-bit addressing) shift */
+#define	IIC_HADR_SHFT		1	/* HighAddr (10-bit addressing) shift */
+
+/*
+ * definitions for IIC Registers
+ */
 #define	IIC_MDBUF		0x00	/* Master Data Buffer */
 #define	IIC_SDBUF		0x02	/* Slave Data Buffer */
 #define	IIC_LMADR		0x04	/* Low Master Address */
@@ -57,6 +68,72 @@
 #define	IIC_NREG		0x20
 
 /*
+ * Bit definitions for IIC_CNTL
+ */
+#define	IIC_CNTL_PT		(1u << 0)	/* Pending Transfer */
+#define	IIC_CNTL_RW		(1u << 1)	/* Read/Write */
+#define	IIC_CNTL_CHT		(1u << 2)	/* Chain Transfer */
+#define	IIC_CNTL_RPST		(1u << 3)	/* Repeated Start */
+#define	IIC_CNTL_TCT		(3u << 4)	/* Transfer Count */
+#define	IIC_CNTL_AMD		(1u << 6)	/* Addressing Mode */
+#define	IIC_CNTL_HMT		(1u << 7)	/* Halt Master Transfer */
+#define	IIC_CNTL_TCT_SHFT	4
+
+/*
+ * Bit definitions for IIC_MDCNTL
+ */
+#define	IIC_MDCNTL_HSCL		(1u << 0)	/* Hold IIC Serial Clock Low */
+#define	IIC_MDCNTL_EUBS		(1u << 1)	/* Exit Unknown IIC Bus State */
+#define	IIC_MDCNTL_EINT		(1u << 2)	/* Enable Interrupt */
+#define	IIC_MDCNTL_ESM		(1u << 3)	/* Enable Slave Mode */
+#define	IIC_MDCNTL_FSM		(1u << 4)	/* Fast/Standard Mode */
+#define	IIC_MDCNTL_FMDB		(1u << 6)	/* Flush Master Data Buffer */
+#define	IIC_MDCNTL_FSDB		(1u << 7)	/* Flush Slave Data Buffer */
+
+/*
+ * Bit definitions for IIC_STS
+ */
+#define	IIC_STS_PT		(1u << 0)	/* RO:Pending Transfer */
+#define	IIC_STS_IRQA		(1u << 1)	/* IRQ Active */
+#define	IIC_STS_ERR		(1u << 2)	/* RO:Error */
+#define	IIC_STS_SCMP		(1u << 3)	/* Stop Complete */
+#define	IIC_STS_MDBF		(1u << 4)	/* RO:MasterDataBuffer Full */
+#define	IIC_STS_MDBS		(1u << 5)	/* RO:MasterDataBuffer Status */
+#define	IIC_STS_SLPR		(1u << 6)	/* Sleep Request */
+#define	IIC_STS_SSS		(1u << 7)	/* Slave Status Set */
+
+/*
+ * Bit definitions for IIC_EXTSTS
+ */
+#define	IIC_EXTSTS_XFRA		(1u << 0)	/* Transfer Aborted */
+#define	IIC_EXTSTS_ICT		(1u << 1)	/* Incomplete Transfer */
+#define	IIC_EXTSTS_LA		(1u << 2)	/* Lost Arbitration */
+#define	IIC_EXTSTS_IRQD		(1u << 3)	/* IRQ On-Deck */
+#define	IIC_EXTSTS_BCS		(7u << 4)	/* RO:Bus Control State */
+#define	IIC_EXTSTS_IRQP		(1u << 7)	/* IRQ Pending */
+
+#define	IIC_EXTSTS_BCS_FREE	(4u << 4)	/* BCS: Free Bus */
+
+/*
+ * Bit definitions for IIC_XFRCNT
+ */
+#define	IIC_INTRMSK_EIMTC	(1u << 0)	/* Enable IRQ on Reqested MT */
+#define	IIC_INTRMSK_EITA	(1u << 1)	/* Enable IRQ on Trans Abort */
+#define	IIC_INTRMSK_EIIC	(1u << 2)	/* Enable IRQ on Incomp*/
+#define	IIC_INTRMSK_EIHE	(1u << 3)	/* */
+#define	IIC_INTRMSK_EIWS	(1u << 4)	/* */
+#define	IIC_INTRMSK_EIWC	(1u << 5)	/* */
+#define	IIC_INTRMSK_EIRS	(1u << 6)	/* */
+#define	IIC_INTRMSK_EIRC	(1u << 7)	/* */
+
+/*
+ * Bit definitions for IIC_XFRCNT
+ */
+#define	IIC_XFRCNT_STC		(7u << 4)	/* Slave Transfer Count */
+#define	IIC_XFRCNT_MTC		(7u << 0)	/* Master Transfer Count */
+#define	IIC_XFRCNT_STC_SHFT	4
+
+/*
  * Bit definitions for IIC_XTCNTLSS
  */
 #define	IIC_XTCNTLSS_SRST	(1u << 0)	/* Soft reset */
@@ -75,5 +152,15 @@
 #define	IIC_DIRECTCNTL_MSDA	(1u << 1)	/* Monitor IIC Data Line (ro) */
 #define	IIC_DIRECTCNTL_SCC	(1u << 2)	/* IIC Clock Control */
 #define	IIC_DIRECTCNTL_SDAC	(1u << 3)	/* IIC Data Control */
+
+/*
+ * Value definitions for IIC_CLKDIV
+ */
+#define	IIC_CLKDIV_20MHZ	(0x01)		/* OPB f = 20 MHz */
+#define	IIC_CLKDIV_30MHZ	(0x02)		/* OPB 20 < f <= 30 MHz */
+#define	IIC_CLKDIV_40MHZ	(0x03)		/* OPB 30 < f <= 40 MHz */
+#define	IIC_CLKDIV_50MHZ	(0x04)		/* OPB 40 < f <= 50 MHz */
+#define	IIC_CLKDIV_60MHZ	(0x05)		/* OPB 50 < f <= 60 MHz */
+#define	IIC_CLKDIV_70MHZ	(0x06)		/* OPB 60 < f <= 70 MHz */
 
 #endif	/* _IBM4XX_IICREG_H_ */