/*-
 * Copyright (C) 2009-2010 Semihalf. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _E6000SWREG_H_
#define _E6000SWREG_H_

struct atu_opt {
	uint16_t mac_01;
	uint16_t mac_23;
	uint16_t mac_45;
	uint16_t fid;
};

/*
 * Definitions for the Marvell 88E6165 Ethernet Switch.
 */

#define	CPU_PORT			0x5

/*
 * Switch Registers
 */
#define REG_GLOBAL			0x1b
#define REG_GLOBAL2			0x1c
#define REG_PORT(p)			(0x10 + (p))

/*
 * Per-Port Switch Registers
 */
#define PORT_STATUS			0x0
#define PSC_CONTROL			0x1
#define JAM_CONTROL			0x2
#define SWITCH_ID			0x3
#define CONTROL				0x4
#define PORT_CONTROL1			0x5
#define PORT_VLAN_MAP			0x6
#define PORT_VID			0x7
#define PORT_CONTROL2			0x8
#define PORT_ASSOCIATION_VECTOR		0xb
#define PORT_ATU_CTRL			0xc
#define RX_COUNTER			0x12
#define TX_COUNTER			0x13

/* MV6165_PORT_CONTROL fields */
#define PORT_CTRL_PORT_STATE		0x0003 /* forwarding */
#define PORT_CTRL_PORT_STATE_DIS	0x0000 /* disable */
#define PORT_CTRL_PORT_STATE_FORW	0x0003 /* forwarding */

#define PORT_CTRL_EGRESS_MODE		0x0100 /* enable on rx */
#define PORT_CTRL_INGRESS_TRAILER	0x4000 /* enable on tx */

#define PORT_CTRL_FRAME_MODE_NORMAL	0x0000 /* normal network */
#define PORT_CTRL_FRAME_MODE_DSA	0x0100 /* distr. arch */
#define PORT_CTRL_FRAME_MODE_PROV	0x0200 /* provider */
#define PORT_CTRL_FRAME_MODE_ETH_DSA	0x0300 /* ether type DSA */

#define EGRESS_TRAILER_VALID		0x80
#define INGRESS_TRAILER_OVERRIDE	0x80

/* PORT_CONTROL2 fields */
#define PORT_CTRL2_FORCE_FCS		(1 << 15)	/* force good FCS in the frame */
#define PORT_CTRL2_JUMBO_1522		(0x0 << 12)	/* max 1522 bytes */
#define PORT_CTRL2_JUMBO_2048		(0x1 << 12)
#define PORT_CTRL2_JUMBO_10240		(0x2 << 12)
#define PORT_CTRL2_JUMBO_RSVD		(0x3 << 12)
#define PORT_CTRL2_8021Q_DISABLE	(0x0 << 10)	/* disable */
#define PORT_CTRL2_8021Q_FALLBCK	(0x1 << 10)	/* fallback mode */
#define PORT_CTRL2_8021Q_CHECK		(0x2 << 10)	/* check mode */
#define PORT_CTRL2_8021Q_SECURE		(0x3 << 10)	/* secure mode */
#define PORT_CTRL2_DISCARD_TAGGED	(1 << 9)	/* discard tagged frames */
#define PORT_CTRL2_DISCARD_UNTAGGED	(1 << 8)	/* discard untagged frames */
#define PORT_CTRL2_MAPDA		(1 << 7)	/* map using DA hits */
#define PORT_CTRL2_ARP_MIRROR		(1 << 6)	/* ARP mirror enable */
#define PORT_CTRL2_EGRESS_MON		(1 << 5)	/* egress monitor source port */
#define PORT_CTRL2_INGRESS_MON		(1 << 4)	/* ingress monitor source port */

/*
 * Switch Global Register 1 accessed via REG_GLOBAL_ADDR
 */

#define SWITCH_GLOBAL_STATUS		0
#define SWITCH_GLOBAL_CONTROL		4
#define SWITCH_GLOBAL_CONTROL2		28

#define MONITOR_CONTROL			26

/* VTU operation */
#define VTU_FID				2
#define VTU_SID				3
#define VTU_OPERATION			5
#define VTU_VID				6
#define VTU_DATA_03			7
#define STU_DATA_03			7
#define VTU_DATA_45			8
#define STU_DATA_45			8
#define VTU_OPERATION_DATA		9

/* ATU opertation */
#define ATU_FID				1
#define ATU_CONTROL			10
#define ATU_OPERATION			11
#define ATU_DATA			12
#define ATU_MAC_ADDR01			13
#define ATU_MAC_ADDR23			14
#define ATU_MAC_ADDR45			15

#define ATU_UNIT_BUSY			(1 << 15)
#define ENTRY_STATE			0xf

/* ATU opcode */
#define NO_OPERATION			(0 << 0)
#define FLUSH_ALL			(1 << 0)
#define FLUSH_NON_STATIC		(1 << 1)
#define LOAD_FROM_FIB			(3 << 0)
#define PURGE_FROM_FIB			(3 << 0)
#define GET_NEXT_IN_FIB			(1 << 2)
#define FLUSH_ALL_IN_FIB		(5 << 0)
#define FLUSH_NON_STATIC_IN_FIB		(3 << 1)
#define GET_VIOLATION_DATA		(7 << 0)
#define CLEAR_VIOLATION_DATA		(7 << 0)

/* ATU Stats */
#define COUNT_ALL			(0 << 0)
#define COUNT_STATIC			(1 << 0)
#define COUNT_VALID			(1 << 1)
#define COUNT_VALID_STATIC		(3 << 0)


/*
 * Switch Global Register 2 accessed via REG_GLOBAL2_ADDR
 */

#define	MGMT_EN_2x			2
#define MGMT_EN_0x			3
#define SWITCH_MANG			5
#define ATU_STATS			14
#define QOS_WEIHGT			28

#endif /* _E6000SWREG_H_ */