Index: i386/include/pci_cfgreg.h =================================================================== RCS file: /home/ncvs/src/sys/i386/include/pci_cfgreg.h,v retrieving revision 1.8 diff -u -u -r1.8 pci_cfgreg.h --- i386/include/pci_cfgreg.h 6 Sep 2002 22:15:44 -0000 1.8 +++ i386/include/pci_cfgreg.h 15 Feb 2003 18:20:31 -0000 @@ -51,6 +51,4 @@ u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes); void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes); int pci_cfgintr(int bus, int device, int pin, int oldirq); -int pci_kill_pcibios(void); -int pci_pcibios_active(void); int pci_probe_route_table(int bus); Index: i386/pci/pci_bus.c =================================================================== RCS file: /home/ncvs/src/sys/i386/pci/pci_bus.c,v retrieving revision 1.97 diff -u -u -r1.97 pci_bus.c --- i386/pci/pci_bus.c 23 Dec 2002 22:12:17 -0000 1.97 +++ i386/pci/pci_bus.c 15 Feb 2003 18:19:49 -0000 @@ -310,7 +310,6 @@ int pcifunchigh; int found824xx = 0; int found_orion = 0; - int found_pcibios_flaming_death = 0; device_t child; devclass_t pci_devclass; @@ -398,23 +397,6 @@ } if (found824xx && bus == 0) { bus++; - goto retry; - } - - /* - * This is just freaking brilliant! Some BIOS writers have - * decided that we must be forcibly prevented from using - * PCIBIOS to query the host->pci bridges. If you try and - * access configuration registers, it pretends there is - * no pci device at that bus:device:function address. - */ - if (!found && pci_pcibios_active() && !found_pcibios_flaming_death) { - /* retry with the old mechanism, or fail */ - if (pci_kill_pcibios() == 0) - return; - printf("nexus_pcib_identify: found broken PCIBIOS - disabling it and retrying.\n"); - printf("nexus_pcib_identify: it is bogusly censoring host->pci bridges.\n"); - found_pcibios_flaming_death = 1; goto retry; } Index: i386/pci/pci_cfgreg.c =================================================================== RCS file: /home/ncvs/src/sys/i386/pci/pci_cfgreg.c,v retrieving revision 1.100 diff -u -u -r1.100 pci_cfgreg.c --- i386/pci/pci_cfgreg.c 14 Nov 2002 05:22:37 -0000 1.100 +++ i386/pci/pci_cfgreg.c 16 Feb 2003 16:41:41 -0000 @@ -35,6 +35,8 @@ #include #include #include +#include +#include #include #include #include @@ -58,10 +60,6 @@ static int cfgmech; static int devmax; -static int usebios; -static int enable_pcibios = 0; - -TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios); static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq); static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); @@ -71,11 +69,7 @@ static void pci_print_irqmask(u_int16_t irqs); static void pci_print_route_table(struct PIR_table *prt, int size); -#ifdef USE_PCI_BIOS_FOR_READ_WRITE -static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes); -static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); -#endif -static int pcibios_cfgopen(void); +static void pcibios_cfgopen(void); static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); static int pcireg_cfgopen(void); @@ -83,6 +77,8 @@ static struct PIR_table *pci_route_table; static int pci_route_count; +static struct mtx pcicfg_mtx; + /* * Some BIOS writers seem to want to ignore the spec and put * 0 in the intline rather than 255 to indicate none. Some use @@ -98,19 +94,6 @@ return (line); } -int -pci_pcibios_active(void) -{ - return (usebios); -} - -int -pci_kill_pcibios(void) -{ - usebios = 0; - return (pcireg_cfgopen() != 0); -} - static u_int16_t pcibios_get_version(void) { @@ -147,12 +130,9 @@ if (opened) return(1); - if (pcibios_cfgopen() != 0) - usebios = 1; - else if (pcireg_cfgopen() != 0) - usebios = 0; - else + if (pcireg_cfgopen() == 0) return(0); + pcibios_cfgopen(); /* * Look for the interrupt routing table. @@ -187,6 +167,7 @@ } } } + mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); opened = 1; return(1); } @@ -194,18 +175,6 @@ /* * Read configuration space register */ -static u_int32_t -pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes) -{ -#ifdef USE_PCI_BIOS_FOR_READ_WRITE - return(usebios ? - pcibios_cfgread(bus, slot, func, reg, bytes) : - pcireg_cfgread(bus, slot, func, reg, bytes)); -#else - return (pcireg_cfgread(bus, slot, func, reg, bytes)); -#endif -} - u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes) { @@ -222,8 +191,8 @@ */ if ((reg == PCIR_INTLINE) && (bytes == 1)) { - pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1); - line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1); + pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1); + line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1); if (pin != 0) { int airq; @@ -259,11 +228,11 @@ * the code uses 255 as an invalid IRQ. */ if (reg == PCIR_INTLINE && bytes == 1) { - line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1); + line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1); return pci_i386_map_intline(line); } #endif /* APIC_IO */ - return(pci_do_cfgregread(bus, slot, func, reg, bytes)); + return(pcireg_cfgread(bus, slot, func, reg, bytes)); } /* @@ -272,14 +241,8 @@ void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { -#ifdef USE_PCI_BIOS_FOR_READ_WRITE - if (usebios) - pcibios_cfgwrite(bus, slot, func, reg, data, bytes); - else - pcireg_cfgwrite(bus, slot, func, reg, data, bytes); -#else + pcireg_cfgwrite(bus, slot, func, reg, data, bytes); -#endif } /* @@ -626,79 +589,20 @@ return (0); } -#ifdef USE_PCI_BIOS_FOR_READ_WRITE -/* - * Config space access using BIOS functions - */ -static int -pcibios_cfgread(int bus, int slot, int func, int reg, int bytes) -{ - struct bios_regs args; - u_int mask; - - switch(bytes) { - case 1: - args.eax = PCIBIOS_READ_CONFIG_BYTE; - mask = 0xff; - break; - case 2: - args.eax = PCIBIOS_READ_CONFIG_WORD; - mask = 0xffff; - break; - case 4: - args.eax = PCIBIOS_READ_CONFIG_DWORD; - mask = 0xffffffff; - break; - default: - return(-1); - } - args.ebx = (bus << 8) | (slot << 3) | func; - args.edi = reg; - bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); - /* check call results? */ - return(args.ecx & mask); -} - -static void -pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) -{ - struct bios_regs args; - - switch(bytes) { - case 1: - args.eax = PCIBIOS_WRITE_CONFIG_BYTE; - break; - case 2: - args.eax = PCIBIOS_WRITE_CONFIG_WORD; - break; - case 4: - args.eax = PCIBIOS_WRITE_CONFIG_DWORD; - break; - default: - return; - } - args.ebx = (bus << 8) | (slot << 3) | func; - args.ecx = data; - args.edi = reg; - bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); -} -#endif - /* * Determine whether there is a PCI BIOS present */ -static int +static void pcibios_cfgopen(void) { u_int16_t v = 0; - if (PCIbios.ventry != 0 && enable_pcibios) { + if (PCIbios.ventry != 0) { v = pcibios_get_version(); if (v > 0) printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8, v & 0xff); } - return (v > 0); } /* @@ -756,8 +660,8 @@ int data = -1; int port; + mtx_lock_spin(&pcicfg_mtx); port = pci_cfgenable(bus, slot, func, reg, bytes); - if (port != 0) { switch (bytes) { case 1: @@ -772,6 +676,7 @@ } pci_cfgdisable(); } + mtx_unlock_spin(&pcicfg_mtx); return (data); } @@ -780,6 +685,7 @@ { int port; + mtx_lock_spin(&pcicfg_mtx); port = pci_cfgenable(bus, slot, func, reg, bytes); if (port != 0) { switch (bytes) { @@ -795,6 +701,7 @@ } pci_cfgdisable(); } + mtx_unlock_spin(&pcicfg_mtx); } /* check whether the configuration mechanism has been correctly identified */ @@ -804,6 +711,7 @@ uint32_t id, class; uint8_t header; uint8_t device; + int port; if (bootverbose) printf("pci_cfgcheck:\tdevice "); @@ -812,17 +720,20 @@ if (bootverbose) printf("%d ", device); - id = inl(pci_cfgenable(0, device, 0, 0, 4)); + port = pci_cfgenable(0, device, 0, 0, 4); + id = inl(port); if (id == 0 || id == 0xffffffff) continue; - class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8; + port = pci_cfgenable(0, device, 0, 8, 4); + class = inl(port) >> 8; if (bootverbose) printf("[class=%06x] ", class); if (class == 0 || (class & 0xf870ff) != 0) continue; - header = inb(pci_cfgenable(0, device, 0, 14, 1)); + port = pci_cfgenable(0, device, 0, 14, 1); + header = inb(port); if (bootverbose) printf("[hdr=%02x] ", header); if ((header & 0x7e) != 0) Index: kern/subr_witness.c =================================================================== RCS file: /home/ncvs/src/sys/kern/subr_witness.c,v retrieving revision 1.136 diff -u -u -r1.136 subr_witness.c --- kern/subr_witness.c 13 Feb 2003 01:35:56 -0000 1.136 +++ kern/subr_witness.c 16 Feb 2003 17:16:16 -0000 @@ -259,6 +259,9 @@ #ifdef __ia64__ { "MCA spin lock", &lock_class_mtx_spin }, #endif +#ifdef __i386__ + { "pcicfg", &lock_class_mtx_spin }, +#endif { NULL, NULL }, { NULL, NULL } };