namespace std __attribute__ ((__visibility__ ("default"))) {
}
namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {

  template<typename _Iterator, typename _Container>
    class __normal_iterator;

}

namespace std __attribute__ ((__visibility__ ("default"))) {

namespace __detail
{


  typedef char __one;
  typedef char __two[2];

  template<typename _Tp>
  __one __test_type(int _Tp::*);
  template<typename _Tp>
  __two& __test_type(...);
}


  struct __true_type { };
  struct __false_type { };

  template<bool>
    struct __truth_type
    { typedef __false_type __type; };

  template<>
    struct __truth_type<true>
    { typedef __true_type __type; };



  template<class _Sp, class _Tp>
    struct __traitor
    {
      enum { __value = bool(_Sp::__value) || bool(_Tp::__value) };
      typedef typename __truth_type<__value>::__type __type;
    };


  template<typename, typename>
    struct __are_same
    {
      enum { __value = 0 };
      typedef __false_type __type;
    };

  template<typename _Tp>
    struct __are_same<_Tp, _Tp>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };


  template<typename _Tp>
    struct __is_void
    {
      enum { __value = 0 };
      typedef __false_type __type;
    };

  template<>
    struct __is_void<void>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };




  template<typename _Tp>
    struct __is_integer
    {
      enum { __value = 0 };
      typedef __false_type __type;
    };




  template<>
    struct __is_integer<bool>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<char>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<signed char>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<unsigned char>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };


  template<>
    struct __is_integer<wchar_t>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };


  template<>
    struct __is_integer<short>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<unsigned short>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<int>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<unsigned int>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<long>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<unsigned long>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<long long>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_integer<unsigned long long>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };




  template<typename _Tp>
    struct __is_floating
    {
      enum { __value = 0 };
      typedef __false_type __type;
    };


  template<>
    struct __is_floating<float>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_floating<double>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };

  template<>
    struct __is_floating<long double>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };




  template<typename _Tp>
    struct __is_pointer
    {
      enum { __value = 0 };
      typedef __false_type __type;
    };

  template<typename _Tp>
    struct __is_pointer<_Tp*>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };




  template<typename _Tp>
    struct __is_normal_iterator
    {
      enum { __value = 0 };
      typedef __false_type __type;
    };

  template<typename _Iterator, typename _Container>
    struct __is_normal_iterator< __gnu_cxx::__normal_iterator<_Iterator,
             _Container> >
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };




  template<typename _Tp>
    struct __is_arithmetic
    : public __traitor<__is_integer<_Tp>, __is_floating<_Tp> >
    { };




  template<typename _Tp>
    struct __is_fundamental
    : public __traitor<__is_void<_Tp>, __is_arithmetic<_Tp> >
    { };




  template<typename _Tp>
    struct __is_scalar
    : public __traitor<__is_arithmetic<_Tp>, __is_pointer<_Tp> >
    { };


  template<typename _Tp>
    struct __is_pod
    {
      enum
 {
   __value = (sizeof(__detail::__test_type<_Tp>(0))
       != sizeof(__detail::__one))
 };
    };




  template<typename _Tp>
    struct __is_empty
    {
    private:
      template<typename>
        struct __first { };
      template<typename _Up>
        struct __second
        : public _Up { };

    public:
      enum
 {
   __value = sizeof(__first<_Tp>) == sizeof(__second<_Tp>)
 };
    };




  template<typename _Tp>
    struct __is_char
    {
      enum { __value = 0 };
      typedef __false_type __type;
    };

  template<>
    struct __is_char<char>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };


  template<>
    struct __is_char<wchar_t>
    {
      enum { __value = 1 };
      typedef __true_type __type;
    };


}



typedef signed char __int8_t;
typedef unsigned char __uint8_t;
typedef short __int16_t;
typedef unsigned short __uint16_t;
typedef int __int32_t;
typedef unsigned int __uint32_t;
typedef long __int64_t;
typedef unsigned long __uint64_t;




typedef __int32_t __clock_t;
typedef __int64_t __critical_t;
typedef double __double_t;
typedef float __float_t;
typedef __int64_t __intfptr_t;
typedef __int64_t __intmax_t;
typedef __int64_t __intptr_t;
typedef __int32_t __int_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __int64_t __int_fast64_t;
typedef __int8_t __int_least8_t;
typedef __int16_t __int_least16_t;
typedef __int32_t __int_least32_t;
typedef __int64_t __int_least64_t;
typedef __int64_t __ptrdiff_t;
typedef __int64_t __register_t;
typedef __int64_t __segsz_t;
typedef __uint64_t __size_t;
typedef __int64_t __ssize_t;
typedef __int64_t __time_t;
typedef __uint64_t __uintfptr_t;
typedef __uint64_t __uintmax_t;
typedef __uint64_t __uintptr_t;
typedef __uint32_t __uint_fast8_t;
typedef __uint32_t __uint_fast16_t;
typedef __uint32_t __uint_fast32_t;
typedef __uint64_t __uint_fast64_t;
typedef __uint8_t __uint_least8_t;
typedef __uint16_t __uint_least16_t;
typedef __uint32_t __uint_least32_t;
typedef __uint64_t __uint_least64_t;
typedef __uint64_t __u_register_t;
typedef __uint64_t __vm_offset_t;
typedef __int64_t __vm_ooffset_t;
typedef __uint64_t __vm_paddr_t;
typedef __uint64_t __vm_pindex_t;
typedef __uint64_t __vm_size_t;





typedef __builtin_va_list __va_list;






typedef __va_list __gnuc_va_list;




typedef __uint32_t __blksize_t;
typedef __int64_t __blkcnt_t;
typedef __int32_t __clockid_t;
typedef __uint64_t __cap_rights_t;
typedef __uint32_t __fflags_t;
typedef __uint64_t __fsblkcnt_t;
typedef __uint64_t __fsfilcnt_t;
typedef __uint32_t __gid_t;
typedef __int64_t __id_t;
typedef __uint32_t __ino_t;
typedef long __key_t;
typedef __int32_t __lwpid_t;
typedef __uint16_t __mode_t;
typedef int __accmode_t;
typedef int __nl_item;
typedef __uint16_t __nlink_t;
typedef __int64_t __off_t;
typedef __int32_t __pid_t;
typedef __int64_t __rlim_t;


typedef __uint8_t __sa_family_t;
typedef __uint32_t __socklen_t;
typedef long __suseconds_t;
typedef struct __timer *__timer_t;
typedef struct __mq *__mqd_t;
typedef __uint32_t __uid_t;
typedef unsigned int __useconds_t;
typedef int __cpuwhich_t;
typedef int __cpulevel_t;
typedef int __cpusetid_t;


typedef __uint64_t __new_ino_t;
typedef __uint32_t __new_mode_t;
typedef __uint32_t __new_nlink_t;
typedef int __ct_rune_t;
typedef __ct_rune_t __rune_t;
typedef __ct_rune_t __wchar_t;
typedef __ct_rune_t __wint_t;

typedef __uint32_t __dev_t;

typedef __uint32_t __fixpt_t;





typedef union {
 char __mbstate8[128];
 __int64_t _mbstateL;
} __mbstate_t;

typedef __ptrdiff_t ptrdiff_t;



typedef __rune_t rune_t;





typedef __size_t size_t;

namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::ptrdiff_t;
  using ::size_t;

}


namespace std __attribute__ ((__visibility__ ("default"))) {

  namespace rel_ops
  {
    template <class _Tp>
      inline bool
      operator!=(const _Tp& __x, const _Tp& __y)
      { return !(__x == __y); }
    template <class _Tp>
      inline bool
      operator>(const _Tp& __x, const _Tp& __y)
      { return __y < __x; }
    template <class _Tp>
      inline bool
      operator<=(const _Tp& __x, const _Tp& __y)
      { return !(__y < __x); }
    template <class _Tp>
      inline bool
      operator>=(const _Tp& __x, const _Tp& __y)
      { return !(__x < __y); }

  }

}
namespace std __attribute__ ((__visibility__ ("default"))) {


  template<class _T1, class _T2>
    struct pair
    {
      typedef _T1 first_type;
      typedef _T2 second_type;

      _T1 first;
      _T2 second;





      pair()
      : first(), second() { }


      pair(const _T1& __a, const _T2& __b)
      : first(__a), second(__b) { }


      template<class _U1, class _U2>
        pair(const pair<_U1, _U2>& __p)
 : first(__p.first), second(__p.second) { }
    };


  template<class _T1, class _T2>
    inline bool
    operator==(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
    { return __x.first == __y.first && __x.second == __y.second; }


  template<class _T1, class _T2>
    inline bool
    operator<(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
    { return __x.first < __y.first
      || (!(__y.first < __x.first) && __x.second < __y.second); }


  template<class _T1, class _T2>
    inline bool
    operator!=(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
    { return !(__x == __y); }


  template<class _T1, class _T2>
    inline bool
    operator>(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
    { return __y < __x; }


  template<class _T1, class _T2>
    inline bool
    operator<=(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
    { return !(__y < __x); }


  template<class _T1, class _T2>
    inline bool
    operator>=(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
    { return !(__x < __y); }
  template<class _T1, class _T2>
    inline pair<_T1, _T2>
    make_pair(_T1 __x, _T2 __y)
    { return pair<_T1, _T2>(__x, __y); }

}


namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {


  template<bool, typename>
    struct __enable_if
    { };

  template<typename _Tp>
    struct __enable_if<true, _Tp>
    { typedef _Tp __type; };



  template<bool _Cond, typename _Iftrue, typename _Iffalse>
    struct __conditional_type
    { typedef _Iftrue __type; };

  template<typename _Iftrue, typename _Iffalse>
    struct __conditional_type<false, _Iftrue, _Iffalse>
    { typedef _Iffalse __type; };



  template<typename _Tp>
    struct __add_unsigned
    {
    private:
      typedef __enable_if<std::__is_integer<_Tp>::__value, _Tp> __if_type;

    public:
      typedef typename __if_type::__type __type;
    };

  template<>
    struct __add_unsigned<char>
    { typedef unsigned char __type; };

  template<>
    struct __add_unsigned<signed char>
    { typedef unsigned char __type; };

  template<>
    struct __add_unsigned<short>
    { typedef unsigned short __type; };

  template<>
    struct __add_unsigned<int>
    { typedef unsigned int __type; };

  template<>
    struct __add_unsigned<long>
    { typedef unsigned long __type; };

  template<>
    struct __add_unsigned<long long>
    { typedef unsigned long long __type; };


  template<>
    struct __add_unsigned<bool>;

  template<>
    struct __add_unsigned<wchar_t>;



  template<typename _Tp>
    struct __remove_unsigned
    {
    private:
      typedef __enable_if<std::__is_integer<_Tp>::__value, _Tp> __if_type;

    public:
      typedef typename __if_type::__type __type;
    };

  template<>
    struct __remove_unsigned<char>
    { typedef signed char __type; };

  template<>
    struct __remove_unsigned<unsigned char>
    { typedef signed char __type; };

  template<>
    struct __remove_unsigned<unsigned short>
    { typedef short __type; };

  template<>
    struct __remove_unsigned<unsigned int>
    { typedef int __type; };

  template<>
    struct __remove_unsigned<unsigned long>
    { typedef long __type; };

  template<>
    struct __remove_unsigned<unsigned long long>
    { typedef long long __type; };


  template<>
    struct __remove_unsigned<bool>;

  template<>
    struct __remove_unsigned<wchar_t>;

}





extern const union __infinity_un {
 unsigned char __uc[8];
 double __ud;
} __infinity;

extern const union __nan_un {
 unsigned char __uc[sizeof(float)];
 float __uf;
} __nan;
typedef __double_t double_t;
typedef __float_t float_t;
extern int signgam;
extern "C" {



int __fpclassifyd(double) __attribute__((__const__));
int __fpclassifyf(float) __attribute__((__const__));
int __fpclassifyl(long double) __attribute__((__const__));
int __isfinitef(float) __attribute__((__const__));
int __isfinite(double) __attribute__((__const__));
int __isfinitel(long double) __attribute__((__const__));
int __isinff(float) __attribute__((__const__));
int __isinfl(long double) __attribute__((__const__));
int __isnanf(float) __attribute__((__const__));
int __isnanl(long double) __attribute__((__const__));
int __isnormalf(float) __attribute__((__const__));
int __isnormal(double) __attribute__((__const__));
int __isnormall(long double) __attribute__((__const__));
int __signbit(double) __attribute__((__const__));
int __signbitf(float) __attribute__((__const__));
int __signbitl(long double) __attribute__((__const__));

double acos(double);
double asin(double);
double atan(double);
double atan2(double, double);
double cos(double);
double sin(double);
double tan(double);

double cosh(double);
double sinh(double);
double tanh(double);

double exp(double);
double frexp(double, int *);
double ldexp(double, int);
double log(double);
double log10(double);
double modf(double, double *);

double pow(double, double);
double sqrt(double);

double ceil(double);
double fabs(double) __attribute__((__const__));
double floor(double);
double fmod(double, double);





double acosh(double);
double asinh(double);
double atanh(double);
double cbrt(double);
double erf(double);
double erfc(double);
double exp2(double);
double expm1(double);
double fma(double, double, double);
double hypot(double, double);
int ilogb(double) __attribute__((__const__));
int (isinf)(double) __attribute__((__const__));
int (isnan)(double) __attribute__((__const__));
double lgamma(double);
long long llrint(double);
long long llround(double);
double log1p(double);
double log2(double);
double logb(double);
long lrint(double);
long lround(double);
double nan(const char *) __attribute__((__const__));
double nextafter(double, double);
double remainder(double, double);
double remquo(double, double, int *);
double rint(double);



double j0(double);
double j1(double);
double jn(int, double);
double y0(double);
double y1(double);
double yn(int, double);


double gamma(double);



double scalb(double, double);




double copysign(double, double) __attribute__((__const__));
double fdim(double, double);
double fmax(double, double) __attribute__((__const__));
double fmin(double, double) __attribute__((__const__));
double nearbyint(double);
double round(double);
double scalbln(double, long);
double scalbn(double, int);
double tgamma(double);
double trunc(double);






double drem(double, double);
int finite(double) __attribute__((__const__));
int isnanf(float) __attribute__((__const__));





double gamma_r(double, int *);
double lgamma_r(double, int *);




double significand(double);




float acosf(float);
float asinf(float);
float atanf(float);
float atan2f(float, float);
float cosf(float);
float sinf(float);
float tanf(float);

float coshf(float);
float sinhf(float);
float tanhf(float);

float exp2f(float);
float expf(float);
float expm1f(float);
float frexpf(float, int *);
int ilogbf(float) __attribute__((__const__));
float ldexpf(float, int);
float log10f(float);
float log1pf(float);
float log2f(float);
float logf(float);
float modff(float, float *);

float powf(float, float);
float sqrtf(float);

float ceilf(float);
float fabsf(float) __attribute__((__const__));
float floorf(float);
float fmodf(float, float);
float roundf(float);

float erff(float);
float erfcf(float);
float hypotf(float, float);
float lgammaf(float);
float tgammaf(float);

float acoshf(float);
float asinhf(float);
float atanhf(float);
float cbrtf(float);
float logbf(float);
float copysignf(float, float) __attribute__((__const__));
long long llrintf(float);
long long llroundf(float);
long lrintf(float);
long lroundf(float);
float nanf(const char *) __attribute__((__const__));
float nearbyintf(float);
float nextafterf(float, float);
float remainderf(float, float);
float remquof(float, float, int *);
float rintf(float);
float scalblnf(float, long);
float scalbnf(float, int);
float truncf(float);

float fdimf(float, float);
float fmaf(float, float, float);
float fmaxf(float, float) __attribute__((__const__));
float fminf(float, float) __attribute__((__const__));






float dremf(float, float);
int finitef(float) __attribute__((__const__));
float gammaf(float);
float j0f(float);
float j1f(float);
float jnf(int, float);
float scalbf(float, float);
float y0f(float);
float y1f(float);
float ynf(int, float);






float gammaf_r(float, int *);
float lgammaf_r(float, int *);




float significandf(float);
long double acosl(long double);



long double asinl(long double);
long double atan2l(long double, long double);



long double atanl(long double);
long double cbrtl(long double);
long double ceill(long double);
long double copysignl(long double, long double) __attribute__((__const__));



long double cosl(long double);




long double exp2l(long double);




long double fabsl(long double) __attribute__((__const__));
long double fdiml(long double, long double);
long double floorl(long double);
long double fmal(long double, long double, long double);
long double fmaxl(long double, long double) __attribute__((__const__));
long double fminl(long double, long double) __attribute__((__const__));
long double fmodl(long double, long double);
long double frexpl(long double value, int *);
long double hypotl(long double, long double);
int ilogbl(long double) __attribute__((__const__));
long double ldexpl(long double, int);



long long llrintl(long double);
long long llroundl(long double);





long double logbl(long double);



long lrintl(long double);
long lroundl(long double);
long double modfl(long double, long double *);
long double nanl(const char *) __attribute__((__const__));
long double nearbyintl(long double);
long double nextafterl(long double, long double);
double nexttoward(double, long double);
float nexttowardf(float, long double);
long double nexttowardl(long double, long double);



long double remainderl(long double, long double);
long double remquol(long double, long double, int *);
long double rintl(long double);
long double roundl(long double);
long double scalblnl(long double, long);
long double scalbnl(long double, int);



long double sinl(long double);
long double sqrtl(long double);



long double tanl(long double);



long double truncl(long double);


}
namespace std __attribute__ ((__visibility__ ("default"))) {



  template<typename _Tp> _Tp __cmath_power(_Tp, unsigned int);

  inline double
  abs(double __x)
  { return __builtin_fabs(__x); }

  inline float
  abs(float __x)
  { return __builtin_fabsf(__x); }

  inline long double
  abs(long double __x)
  { return __builtin_fabsl(__x); }

  using ::acos;

  inline float
  acos(float __x)
  { return __builtin_acosf(__x); }

  inline long double
  acos(long double __x)
  { return __builtin_acosl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    acos(_Tp __x)
    { return __builtin_acos(__x); }

  using ::asin;

  inline float
  asin(float __x)
  { return __builtin_asinf(__x); }

  inline long double
  asin(long double __x)
  { return __builtin_asinl(__x); }

  template<typename _Tp>
  inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
      double>::__type
    asin(_Tp __x)
    { return __builtin_asin(__x); }

  using ::atan;

  inline float
  atan(float __x)
  { return __builtin_atanf(__x); }

  inline long double
  atan(long double __x)
  { return __builtin_atanl(__x); }

  template<typename _Tp>
  inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
      double>::__type
    atan(_Tp __x)
    { return __builtin_atan(__x); }

  using ::atan2;

  inline float
  atan2(float __y, float __x)
  { return __builtin_atan2f(__y, __x); }

  inline long double
  atan2(long double __y, long double __x)
  { return __builtin_atan2l(__y, __x); }

  template<typename _Tp, typename _Up>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value
            && __is_integer<_Up>::__value,
        double>::__type
    atan2(_Tp __y, _Up __x)
    { return __builtin_atan2(__y, __x); }

  using ::ceil;

  inline float
  ceil(float __x)
  { return __builtin_ceilf(__x); }

  inline long double
  ceil(long double __x)
  { return __builtin_ceill(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    ceil(_Tp __x)
    { return __builtin_ceil(__x); }

  using ::cos;

  inline float
  cos(float __x)
  { return __builtin_cosf(__x); }

  inline long double
  cos(long double __x)
  { return __builtin_cosl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    cos(_Tp __x)
    { return __builtin_cos(__x); }

  using ::cosh;

  inline float
  cosh(float __x)
  { return __builtin_coshf(__x); }

  inline long double
  cosh(long double __x)
  { return __builtin_coshl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    cosh(_Tp __x)
    { return __builtin_cosh(__x); }

  using ::exp;

  inline float
  exp(float __x)
  { return __builtin_expf(__x); }

  inline long double
  exp(long double __x)
  { return __builtin_expl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    exp(_Tp __x)
    { return __builtin_exp(__x); }

  using ::fabs;

  inline float
  fabs(float __x)
  { return __builtin_fabsf(__x); }

  inline long double
  fabs(long double __x)
  { return __builtin_fabsl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    fabs(_Tp __x)
    { return __builtin_fabs(__x); }

  using ::floor;

  inline float
  floor(float __x)
  { return __builtin_floorf(__x); }

  inline long double
  floor(long double __x)
  { return __builtin_floorl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    floor(_Tp __x)
    { return __builtin_floor(__x); }

  using ::fmod;

  inline float
  fmod(float __x, float __y)
  { return __builtin_fmodf(__x, __y); }

  inline long double
  fmod(long double __x, long double __y)
  { return __builtin_fmodl(__x, __y); }

  using ::frexp;

  inline float
  frexp(float __x, int* __exp)
  { return __builtin_frexpf(__x, __exp); }

  inline long double
  frexp(long double __x, int* __exp)
  { return __builtin_frexpl(__x, __exp); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    frexp(_Tp __x, int* __exp)
    { return __builtin_frexp(__x, __exp); }

  using ::ldexp;

  inline float
  ldexp(float __x, int __exp)
  { return __builtin_ldexpf(__x, __exp); }

  inline long double
  ldexp(long double __x, int __exp)
  { return __builtin_ldexpl(__x, __exp); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
  ldexp(_Tp __x, int __exp)
  { return __builtin_ldexp(__x, __exp); }

  using ::log;

  inline float
  log(float __x)
  { return __builtin_logf(__x); }

  inline long double
  log(long double __x)
  { return __builtin_logl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    log(_Tp __x)
    { return __builtin_log(__x); }

  using ::log10;

  inline float
  log10(float __x)
  { return __builtin_log10f(__x); }

  inline long double
  log10(long double __x)
  { return __builtin_log10l(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    log10(_Tp __x)
    { return __builtin_log10(__x); }

  using ::modf;

  inline float
  modf(float __x, float* __iptr)
  { return __builtin_modff(__x, __iptr); }

  inline long double
  modf(long double __x, long double* __iptr)
  { return __builtin_modfl(__x, __iptr); }

  template<typename _Tp>
    inline _Tp
    __pow_helper(_Tp __x, int __n)
    {
      return __n < 0
        ? _Tp(1)/__cmath_power(__x, -__n)
        : __cmath_power(__x, __n);
    }

  using ::pow;

  inline float
  pow(float __x, float __y)
  { return __builtin_powf(__x, __y); }

  inline long double
  pow(long double __x, long double __y)
  { return __builtin_powl(__x, __y); }

  inline double
  pow(double __x, int __i)
  { return __builtin_powi(__x, __i); }

  inline float
  pow(float __x, int __n)
  { return __builtin_powif(__x, __n); }

  inline long double
  pow(long double __x, int __n)
  { return __builtin_powil(__x, __n); }

  using ::sin;

  inline float
  sin(float __x)
  { return __builtin_sinf(__x); }

  inline long double
  sin(long double __x)
  { return __builtin_sinl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    sin(_Tp __x)
    { return __builtin_sin(__x); }

  using ::sinh;

  inline float
  sinh(float __x)
  { return __builtin_sinhf(__x); }

  inline long double
  sinh(long double __x)
  { return __builtin_sinhl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    sinh(_Tp __x)
    { return __builtin_sinh(__x); }

  using ::sqrt;

  inline float
  sqrt(float __x)
  { return __builtin_sqrtf(__x); }

  inline long double
  sqrt(long double __x)
  { return __builtin_sqrtl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    sqrt(_Tp __x)
    { return __builtin_sqrt(__x); }

  using ::tan;

  inline float
  tan(float __x)
  { return __builtin_tanf(__x); }

  inline long double
  tan(long double __x)
  { return __builtin_tanl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    tan(_Tp __x)
    { return __builtin_tan(__x); }

  using ::tanh;

  inline float
  tanh(float __x)
  { return __builtin_tanhf(__x); }

  inline long double
  tanh(long double __x)
  { return __builtin_tanhl(__x); }

  template<typename _Tp>
    inline typename __gnu_cxx::__enable_if<__is_integer<_Tp>::__value,
        double>::__type
    tanh(_Tp __x)
    { return __builtin_tanh(__x); }

}







namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {

  template<typename _Tp>
    inline int
    __capture_fpclassify(_Tp __f) { return ((sizeof (__f) == sizeof (float)) ? __fpclassifyf(__f) : (sizeof (__f) == sizeof (double)) ? __fpclassifyd(__f) : __fpclassifyl(__f)); }

  template<typename _Tp>
    inline int
    __capture_isfinite(_Tp __f) { return ((sizeof (__f) == sizeof (float)) ? __isfinitef(__f) : (sizeof (__f) == sizeof (double)) ? __isfinite(__f) : __isfinitel(__f)); }

  template<typename _Tp>
    inline int
    __capture_isinf(_Tp __f) { return ((sizeof (__f) == sizeof (float)) ? __isinff(__f) : (sizeof (__f) == sizeof (double)) ? isinf(__f) : __isinfl(__f)); }

  template<typename _Tp>
    inline int
    __capture_isnan(_Tp __f) { return ((sizeof (__f) == sizeof (float)) ? __isnanf(__f) : (sizeof (__f) == sizeof (double)) ? isnan(__f) : __isnanl(__f)); }

  template<typename _Tp>
    inline int
    __capture_isnormal(_Tp __f) { return ((sizeof (__f) == sizeof (float)) ? __isnormalf(__f) : (sizeof (__f) == sizeof (double)) ? __isnormal(__f) : __isnormall(__f)); }

  template<typename _Tp>
    inline int
    __capture_signbit(_Tp __f) { return ((sizeof (__f) == sizeof (float)) ? __signbitf(__f) : (sizeof (__f) == sizeof (double)) ? __signbit(__f) : __signbitl(__f)); }

  template<typename _Tp>
    inline int
    __capture_isgreater(_Tp __f1, _Tp __f2)
    { return __builtin_isgreater((__f1), (__f2)); }

  template<typename _Tp>
    inline int
    __capture_isgreaterequal(_Tp __f1, _Tp __f2)
    { return __builtin_isgreaterequal((__f1), (__f2)); }

  template<typename _Tp>
    inline int
    __capture_isless(_Tp __f1, _Tp __f2) { return __builtin_isless((__f1), (__f2)); }

  template<typename _Tp>
    inline int
    __capture_islessequal(_Tp __f1, _Tp __f2)
    { return __builtin_islessequal((__f1), (__f2)); }

  template<typename _Tp>
    inline int
    __capture_islessgreater(_Tp __f1, _Tp __f2)
    { return __builtin_islessgreater((__f1), (__f2)); }

  template<typename _Tp>
    inline int
    __capture_isunordered(_Tp __f1, _Tp __f2)
    { return __builtin_isunordered((__f1), (__f2)); }

}
namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _Tp>
    inline int
    fpclassify(_Tp __f) { return ::__gnu_cxx::__capture_fpclassify(__f); }

  template<typename _Tp>
    inline int
    isfinite(_Tp __f) { return ::__gnu_cxx::__capture_isfinite(__f); }

  template<typename _Tp>
    inline int
    isinf(_Tp __f) { return ::__gnu_cxx::__capture_isinf(__f); }

  template<typename _Tp>
    inline int
    isnan(_Tp __f) { return ::__gnu_cxx::__capture_isnan(__f); }

  template<typename _Tp>
    inline int
    isnormal(_Tp __f) { return ::__gnu_cxx::__capture_isnormal(__f); }

  template<typename _Tp>
    inline int
    signbit(_Tp __f) { return ::__gnu_cxx::__capture_signbit(__f); }

  template<typename _Tp>
    inline int
    isgreater(_Tp __f1, _Tp __f2)
    { return ::__gnu_cxx::__capture_isgreater(__f1, __f2); }

  template<typename _Tp>
    inline int
    isgreaterequal(_Tp __f1, _Tp __f2)
    { return ::__gnu_cxx::__capture_isgreaterequal(__f1, __f2); }

  template<typename _Tp>
    inline int
    isless(_Tp __f1, _Tp __f2)
    { return ::__gnu_cxx::__capture_isless(__f1, __f2); }

  template<typename _Tp>
    inline int
    islessequal(_Tp __f1, _Tp __f2)
    { return ::__gnu_cxx::__capture_islessequal(__f1, __f2); }

  template<typename _Tp>
    inline int
    islessgreater(_Tp __f1, _Tp __f2)
    { return ::__gnu_cxx::__capture_islessgreater(__f1, __f2); }

  template<typename _Tp>
    inline int
    isunordered(_Tp __f1, _Tp __f2)
    { return ::__gnu_cxx::__capture_isunordered(__f1, __f2); }

}






namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _Tp>
    inline _Tp
    __cmath_power(_Tp __x, unsigned int __n)
    {
      _Tp __y = __n % 2 ? __x : 1;

      while (__n >>= 1)
        {
          __x = __x * __x;
          if (__n % 2)
            __y = __y * __x;
        }

      return __y;
    }

}
extern "C" {
static inline __uint64_t
__bswap64_var(__uint64_t _x)
{

 __asm ("bswap %0" : "+r" (_x));
 return (_x);
}

static inline __uint32_t
__bswap32_var(__uint32_t _x)
{

 __asm ("bswap %0" : "+r" (_x));
 return (_x);
}

static inline __uint16_t
__bswap16_var(__uint16_t _x)
{

 return ((__uint16_t)((_x) << 8 | (_x) >> 8));
}
}


struct pthread;
struct pthread_attr;
struct pthread_cond;
struct pthread_cond_attr;
struct pthread_mutex;
struct pthread_mutex_attr;
struct pthread_once;
struct pthread_rwlock;
struct pthread_rwlockattr;
struct pthread_barrier;
struct pthread_barrier_attr;
struct pthread_spinlock;
typedef struct pthread *pthread_t;


typedef struct pthread_attr *pthread_attr_t;
typedef struct pthread_mutex *pthread_mutex_t;
typedef struct pthread_mutex_attr *pthread_mutexattr_t;
typedef struct pthread_cond *pthread_cond_t;
typedef struct pthread_cond_attr *pthread_condattr_t;
typedef int pthread_key_t;
typedef struct pthread_once pthread_once_t;
typedef struct pthread_rwlock *pthread_rwlock_t;
typedef struct pthread_rwlockattr *pthread_rwlockattr_t;
typedef struct pthread_barrier *pthread_barrier_t;
typedef struct pthread_barrierattr *pthread_barrierattr_t;
typedef struct pthread_spinlock *pthread_spinlock_t;







typedef void *pthread_addr_t;
typedef void *(*pthread_startroutine_t)(void *);




struct pthread_once {
 int state;
 pthread_mutex_t mutex;
};


typedef unsigned char u_char;
typedef unsigned short u_short;
typedef unsigned int u_int;
typedef unsigned long u_long;

typedef unsigned short ushort;
typedef unsigned int uint;







typedef __int8_t int8_t;




typedef __int16_t int16_t;




typedef __int32_t int32_t;




typedef __int64_t int64_t;




typedef __uint8_t uint8_t;




typedef __uint16_t uint16_t;




typedef __uint32_t uint32_t;




typedef __uint64_t uint64_t;




typedef __intptr_t intptr_t;



typedef __uintptr_t uintptr_t;

typedef __uint8_t u_int8_t;
typedef __uint16_t u_int16_t;
typedef __uint32_t u_int32_t;
typedef __uint64_t u_int64_t;

typedef __uint64_t u_quad_t;
typedef __int64_t quad_t;
typedef quad_t * qaddr_t;

typedef char * caddr_t;
typedef const char * c_caddr_t;
typedef volatile char *v_caddr_t;


typedef __blksize_t blksize_t;



typedef __cpuwhich_t cpuwhich_t;
typedef __cpulevel_t cpulevel_t;
typedef __cpusetid_t cpusetid_t;


typedef __blkcnt_t blkcnt_t;



typedef __cap_rights_t cap_rights_t;


typedef __clock_t clock_t;




typedef __clockid_t clockid_t;



typedef __critical_t critical_t;
typedef __int64_t daddr_t;


typedef __dev_t dev_t;




typedef __fflags_t fflags_t;



typedef __fixpt_t fixpt_t;


typedef __fsblkcnt_t fsblkcnt_t;
typedef __fsfilcnt_t fsfilcnt_t;




typedef __gid_t gid_t;




typedef __uint32_t in_addr_t;




typedef __uint16_t in_port_t;




typedef __id_t id_t;




typedef __ino_t ino_t;




typedef __key_t key_t;




typedef __lwpid_t lwpid_t;




typedef __mode_t mode_t;




typedef __accmode_t accmode_t;




typedef __nlink_t nlink_t;




typedef __off_t off_t;




typedef __pid_t pid_t;



typedef __register_t register_t;


typedef __rlim_t rlim_t;



typedef __segsz_t segsz_t;







typedef __ssize_t ssize_t;




typedef __suseconds_t suseconds_t;




typedef __time_t time_t;




typedef __timer_t timer_t;




typedef __mqd_t mqd_t;



typedef __u_register_t u_register_t;


typedef __uid_t uid_t;




typedef __useconds_t useconds_t;



typedef __vm_offset_t vm_offset_t;
typedef __vm_ooffset_t vm_ooffset_t;
typedef __vm_paddr_t vm_paddr_t;
typedef __vm_pindex_t vm_pindex_t;
typedef __vm_size_t vm_size_t;
typedef struct __sigset {
 __uint32_t __bits[4];
} __sigset_t;
struct timeval {
 time_t tv_sec;
 suseconds_t tv_usec;
};
struct timespec {
 time_t tv_sec;
 long tv_nsec;
};
struct itimerspec {
 struct timespec it_interval;
 struct timespec it_value;
};

typedef unsigned long __fd_mask;

typedef __fd_mask fd_mask;




typedef __sigset_t sigset_t;
typedef struct fd_set {
 __fd_mask __fds_bits[(((1024U) + (((sizeof(__fd_mask) * 8)) - 1)) / ((sizeof(__fd_mask) * 8)))];
} fd_set;
extern "C" {
int pselect(int, fd_set *, fd_set *, fd_set *,
 const struct timespec *, const sigset_t *);



int select(int, fd_set *, fd_set *, fd_set *, struct timeval *);

}
extern "C" {


int ftruncate(int, off_t);



off_t lseek(int, off_t, int);



void * mmap(void *, size_t, int, int, int, off_t);



int truncate(const char *, off_t);

}










typedef __int_least8_t int_least8_t;
typedef __int_least16_t int_least16_t;
typedef __int_least32_t int_least32_t;
typedef __int_least64_t int_least64_t;

typedef __uint_least8_t uint_least8_t;
typedef __uint_least16_t uint_least16_t;
typedef __uint_least32_t uint_least32_t;
typedef __uint_least64_t uint_least64_t;

typedef __int_fast8_t int_fast8_t;
typedef __int_fast16_t int_fast16_t;
typedef __int_fast32_t int_fast32_t;
typedef __int_fast64_t int_fast64_t;

typedef __uint_fast8_t uint_fast8_t;
typedef __uint_fast16_t uint_fast16_t;
typedef __uint_fast32_t uint_fast32_t;
typedef __uint_fast64_t uint_fast64_t;


typedef __intmax_t intmax_t;



typedef __uintmax_t uintmax_t;








typedef struct {
 intmax_t quot;
 intmax_t rem;
} imaxdiv_t;

extern "C" {
intmax_t imaxabs(intmax_t) __attribute__((__const__));
imaxdiv_t imaxdiv(intmax_t, intmax_t) __attribute__((__const__));

intmax_t strtoimax(const char * , char ** , int);
uintmax_t strtoumax(const char * , char ** , int);
intmax_t wcstoimax(const wchar_t * ,
      wchar_t ** , int);
uintmax_t wcstoumax(const wchar_t * ,
      wchar_t ** , int);
}





namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _Alloc>
    class allocator;

  template<class _CharT>
    struct char_traits;

  template<typename _CharT, typename _Traits = char_traits<_CharT>,
           typename _Alloc = allocator<_CharT> >
    class basic_string;

  template<> struct char_traits<char>;

  typedef basic_string<char> string;


  template<> struct char_traits<wchar_t>;

  typedef basic_string<wchar_t> wstring;


}




extern "C" {

int bcmp(const void *, const void *, size_t) __attribute__((__pure__));
void bcopy(const void *, void *, size_t);
void bzero(void *, size_t);


int ffs(int) __attribute__((__const__));


int ffsl(long) __attribute__((__const__));
int ffsll(long long) __attribute__((__const__));
int fls(int) __attribute__((__const__));
int flsl(long) __attribute__((__const__));
int flsll(long long) __attribute__((__const__));


char *index(const char *, int) __attribute__((__pure__));
char *rindex(const char *, int) __attribute__((__pure__));

int strcasecmp(const char *, const char *) __attribute__((__pure__));
int strncasecmp(const char *, const char *, size_t) __attribute__((__pure__));
}







extern "C" {

void *memccpy(void * , const void * , int, size_t);

void *memchr(const void *, int, size_t) __attribute__((__pure__));

void *memrchr(const void *, int, size_t) __attribute__((__pure__));

int memcmp(const void *, const void *, size_t) __attribute__((__pure__));
void *memcpy(void * , const void * , size_t);

void *memmem(const void *, size_t, const void *, size_t) __attribute__((__pure__));

void *memmove(void *, const void *, size_t);
void *memset(void *, int, size_t);

char *stpcpy(char * , const char * );
char *stpncpy(char * , const char * , size_t);


char *strcasestr(const char *, const char *) __attribute__((__pure__));

char *strcat(char * , const char * );
char *strchr(const char *, int) __attribute__((__pure__));
int strcmp(const char *, const char *) __attribute__((__pure__));
int strcoll(const char *, const char *);
char *strcpy(char * , const char * );
size_t strcspn(const char *, const char *) __attribute__((__pure__));

char *strdup(const char *) __attribute__((__malloc__));

char *strerror(int);

int strerror_r(int, char *, size_t);


size_t strlcat(char * , const char * , size_t);
size_t strlcpy(char * , const char * , size_t);

size_t strlen(const char *) __attribute__((__pure__));

void strmode(int, char *);

char *strncat(char * , const char * , size_t);
int strncmp(const char *, const char *, size_t) __attribute__((__pure__));
char *strncpy(char * , const char * , size_t);

char *strndup(const char *, size_t) __attribute__((__malloc__));
size_t strnlen(const char *, size_t) __attribute__((__pure__));


char *strnstr(const char *, const char *, size_t) __attribute__((__pure__));

char *strpbrk(const char *, const char *) __attribute__((__pure__));
char *strrchr(const char *, int) __attribute__((__pure__));

char *strsep(char **, const char *);


char *strsignal(int);

size_t strspn(const char *, const char *) __attribute__((__pure__));
char *strstr(const char *, const char *) __attribute__((__pure__));
char *strtok(char * , const char * );

char *strtok_r(char *, const char *, char **);

size_t strxfrm(char * , const char * , size_t);
void swab(const void * , void * , ssize_t);



}
namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::memcpy;
  using ::memmove;
  using ::strcpy;
  using ::strncpy;
  using ::strcat;
  using ::strncat;
  using ::memcmp;
  using ::strcmp;
  using ::strcoll;
  using ::strncmp;
  using ::strxfrm;
  using ::strcspn;
  using ::strspn;
  using ::strtok;
  using ::memset;
  using ::strerror;
  using ::strlen;

  using ::memchr;

  inline void*
  memchr(void* __p, int __c, size_t __n)
  { return memchr(const_cast<const void*>(__p), __c, __n); }

  using ::strchr;

  inline char*
  strchr(char* __s1, int __n)
  { return __builtin_strchr(const_cast<const char*>(__s1), __n); }

  using ::strpbrk;

  inline char*
  strpbrk(char* __s1, const char* __s2)
  { return __builtin_strpbrk(const_cast<const char*>(__s1), __s2); }

  using ::strrchr;

  inline char*
  strrchr(char* __s1, int __n)
  { return __builtin_strrchr(const_cast<const char*>(__s1), __n); }

  using ::strstr;

  inline char*
  strstr(char* __s1, const char* __s2)
  { return __builtin_strstr(const_cast<const char*>(__s1), __s2); }

}



typedef struct {
 int quot;
 int rem;
} div_t;

typedef struct {
 long quot;
 long rem;
} ldiv_t;






extern "C" {
extern int __mb_cur_max;
extern int ___mb_cur_max(void);


__attribute__((__noreturn__)) void abort(void);
int abs(int) __attribute__((__const__));
int atexit(void (*)(void));
double atof(const char *);
int atoi(const char *);
long atol(const char *);
void *bsearch(const void *, const void *, size_t,
     size_t, int (*)(const void *, const void *));
void *calloc(size_t, size_t) __attribute__((__malloc__));
div_t div(int, int) __attribute__((__const__));
__attribute__((__noreturn__)) void exit(int);
void free(void *);
char *getenv(const char *);
long labs(long) __attribute__((__const__));
ldiv_t ldiv(long, long) __attribute__((__const__));
void *malloc(size_t) __attribute__((__malloc__));
int mblen(const char *, size_t);
size_t mbstowcs(wchar_t * , const char * , size_t);
int mbtowc(wchar_t * , const char * , size_t);
void qsort(void *, size_t, size_t,
     int (*)(const void *, const void *));
int rand(void);
void *realloc(void *, size_t);
void srand(unsigned);
double strtod(const char * , char ** );
float strtof(const char * , char ** );
long strtol(const char * , char ** , int);
long double
  strtold(const char * , char ** );
unsigned long
  strtoul(const char * , char ** , int);
int system(const char *);
int wctomb(char *, wchar_t);
size_t wcstombs(char * , const wchar_t * , size_t);
typedef struct {
 long long quot;
 long long rem;
} lldiv_t;


long long
  atoll(const char *);

long long
  llabs(long long) __attribute__((__const__));

lldiv_t lldiv(long long, long long) __attribute__((__const__));

long long
  strtoll(const char * , char ** , int);

unsigned long long
  strtoull(const char * , char ** , int);


__attribute__((__noreturn__)) void _Exit(int);






void * aligned_alloc(size_t, size_t);
int at_quick_exit(void (*)(void));
__attribute__((__noreturn__)) void
 quick_exit(int);







int posix_memalign(void **, size_t, size_t);
int rand_r(unsigned *);
char *realpath(const char * , char * );
int setenv(const char *, const char *, int);
int unsetenv(const char *);



int getsubopt(char **, char *const *, char **);

char *mkdtemp(char *);



int mkstemp(char *);
long a64l(const char *);
double drand48(void);

double erand48(unsigned short[3]);


int grantpt(int);
char *initstate(unsigned long , char *, long);
long jrand48(unsigned short[3]);
char *l64a(long);
void lcong48(unsigned short[7]);
long lrand48(void);

char *mktemp(char *);


long mrand48(void);
long nrand48(unsigned short[3]);
int posix_openpt(int);
char *ptsname(int);
int putenv(char *);
long random(void);
unsigned short
 *seed48(unsigned short[3]);

int setkey(const char *);


char *setstate( char *);
void srand48(long);
void srandom(unsigned long);
int unlockpt(int);



extern const char *_malloc_options;
extern void (*_malloc_message)(const char *, const char *, const char *,
     const char *);
void abort2(const char *, int, void **) __attribute__((__noreturn__));
__uint32_t
  arc4random(void);
void arc4random_addrandom(unsigned char *, int);
void arc4random_buf(void *, size_t);
void arc4random_stir(void);
__uint32_t
  arc4random_uniform(__uint32_t);
char *getbsize(int *, long *);

char *cgetcap(char *, const char *, int);
int cgetclose(void);
int cgetent(char **, char **, const char *);
int cgetfirst(char **, char **);
int cgetmatch(const char *, const char *);
int cgetnext(char **, char **);
int cgetnum(char *, const char *, long *);
int cgetset(const char *);
int cgetstr(char *, const char *, char **);
int cgetustr(char *, const char *, char **);

int daemon(int, int);
char *devname(__dev_t, __mode_t);
char *devname_r(__dev_t, __mode_t, char *, int);
char *fdevname(int);
char *fdevname_r(int, char *, int);
int getloadavg(double [], int);
const char *
  getprogname(void);

int heapsort(void *, size_t, size_t, int (*)(const void *, const void *));
int l64a_r(long, char *, int);
int mergesort(void *, size_t, size_t, int (*)(const void *, const void *));
void qsort_r(void *, size_t, size_t, void *,
     int (*)(void *, const void *, const void *));
int radixsort(const unsigned char **, int, const unsigned char *,
     unsigned);
void *reallocf(void *, size_t);
int rpmatch(const char *);
void setprogname(const char *);
int sradixsort(const unsigned char **, int, const unsigned char *,
     unsigned);
void sranddev(void);
void srandomdev(void);
long long
 strtonum(const char *, long long, long long, const char **);


__int64_t
  strtoq(const char *, char **, int);
__uint64_t
  strtouq(const char *, char **, int);

extern char *suboptarg;

}
namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::div_t;
  using ::ldiv_t;

  using ::abort;
  using ::abs;
  using ::atexit;
  using ::atof;
  using ::atoi;
  using ::atol;
  using ::bsearch;
  using ::calloc;
  using ::div;
  using ::exit;
  using ::free;
  using ::getenv;
  using ::labs;
  using ::ldiv;
  using ::malloc;

  using ::mblen;
  using ::mbstowcs;
  using ::mbtowc;

  using ::qsort;
  using ::rand;
  using ::realloc;
  using ::srand;
  using ::strtod;
  using ::strtol;
  using ::strtoul;
  using ::system;

  using ::wcstombs;
  using ::wctomb;


  inline long
  abs(long __i) { return labs(__i); }

  inline ldiv_t
  div(long __i, long __j) { return ldiv(__i, __j); }

}






struct lconv {
 char *decimal_point;
 char *thousands_sep;
 char *grouping;
 char *int_curr_symbol;
 char *currency_symbol;
 char *mon_decimal_point;
 char *mon_thousands_sep;
 char *mon_grouping;
 char *positive_sign;
 char *negative_sign;
 char int_frac_digits;
 char frac_digits;
 char p_cs_precedes;
 char p_sep_by_space;
 char n_cs_precedes;
 char n_sep_by_space;
 char p_sign_posn;
 char n_sign_posn;
 char int_p_cs_precedes;
 char int_n_cs_precedes;
 char int_p_sep_by_space;
 char int_n_sep_by_space;
 char int_p_sign_posn;
 char int_n_sign_posn;
};
extern "C" {
struct lconv *localeconv(void);
char *setlocale(int, const char *);
}
extern "C" {

typedef struct _xlocale *locale_t;



locale_t newlocale(int mask, const char *locale, locale_t base);






locale_t duplocale(locale_t base);




int freelocale(locale_t loc);




const char *querylocale(int mask, locale_t loc);




locale_t uselocale(locale_t loc);

}





namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::lconv;
  using ::setlocale;
  using ::localeconv;

}





typedef __off_t fpos_t;
typedef __va_list va_list;
struct __sbuf {
 unsigned char *_base;
 int _size;
};
struct __sFILE {
 unsigned char *_p;
 int _r;
 int _w;
 short _flags;
 short _file;
 struct __sbuf _bf;
 int _lbfsize;


 void *_cookie;
 int (*_close)(void *);
 int (*_read)(void *, char *, int);
 fpos_t (*_seek)(void *, fpos_t, int);
 int (*_write)(void *, const char *, int);


 struct __sbuf _ub;
 unsigned char *_up;
 int _ur;


 unsigned char _ubuf[3];
 unsigned char _nbuf[1];


 struct __sbuf _lb;


 int _blksize;
 fpos_t _offset;

 struct pthread_mutex *_fl_mutex;
 struct pthread *_fl_owner;
 int _fl_count;
 int _orientation;
 __mbstate_t _mbstate;
};


typedef struct __sFILE FILE;


extern "C" {
extern FILE *__stdinp;
extern FILE *__stdoutp;
extern FILE *__stderrp;
}
extern "C" {



void clearerr(FILE *);
int fclose(FILE *);
int feof(FILE *);
int ferror(FILE *);
int fflush(FILE *);
int fgetc(FILE *);
int fgetpos(FILE * , fpos_t * );
char *fgets(char * , int, FILE * );
FILE *fopen(const char * , const char * );
int fprintf(FILE * , const char * , ...);
int fputc(int, FILE *);
int fputs(const char * , FILE * );
size_t fread(void * , size_t, size_t, FILE * );
FILE *freopen(const char * , const char * , FILE * );
int fscanf(FILE * , const char * , ...);
int fseek(FILE *, long, int);
int fsetpos(FILE *, const fpos_t *);
long ftell(FILE *);
size_t fwrite(const void * , size_t, size_t, FILE * );
int getc(FILE *);
int getchar(void);
char *gets(char *);
void perror(const char *);
int printf(const char * , ...);
int putc(int, FILE *);
int putchar(int);
int puts(const char *);
int remove(const char *);
int rename(const char *, const char *);
void rewind(FILE *);
int scanf(const char * , ...);
void setbuf(FILE * , char * );
int setvbuf(FILE * , char * , int, size_t);
int sprintf(char * , const char * , ...);
int sscanf(const char * , const char * , ...);
FILE *tmpfile(void);
char *tmpnam(char *);
int ungetc(int, FILE *);
int vfprintf(FILE * , const char * ,
     __va_list);
int vprintf(const char * , __va_list);
int vsprintf(char * , const char * ,
     __va_list);


int snprintf(char * , size_t, const char * ,
     ...) __attribute__((__format__ (__printf__, 3, 4)));
int vfscanf(FILE * , const char * , __va_list)
     __attribute__((__format__ (__scanf__, 2, 0)));
int vscanf(const char * , __va_list) __attribute__((__format__ (__scanf__, 1, 0)));
int vsnprintf(char * , size_t, const char * ,
     __va_list) __attribute__((__format__ (__printf__, 3, 0)));
int vsscanf(const char * , const char * , __va_list)
     __attribute__((__format__ (__scanf__, 2, 0)));
char *ctermid(char *);
FILE *fdopen(int, const char *);
int fileno(FILE *);



int pclose(FILE *);
FILE *popen(const char *, const char *);



int ftrylockfile(FILE *);
void flockfile(FILE *);
void funlockfile(FILE *);





int getc_unlocked(FILE *);
int getchar_unlocked(void);
int putc_unlocked(int, FILE *);
int putchar_unlocked(int);


void clearerr_unlocked(FILE *);
int feof_unlocked(FILE *);
int ferror_unlocked(FILE *);
int fileno_unlocked(FILE *);



int fseeko(FILE *, __off_t, int);
__off_t ftello(FILE *);



int getw(FILE *);
int putw(int, FILE *);



char *tempnam(const char *, const char *);



ssize_t getdelim(char ** , size_t * , int,
     FILE * );
int renameat(int, const char *, int, const char *);
int vdprintf(int, const char * , __va_list);
int asprintf(char **, const char *, ...) __attribute__((__format__ (__printf__, 2, 3)));
char *ctermid_r(char *);
void fcloseall(void);
char *fgetln(FILE *, size_t *);
const char *fmtcheck(const char *, const char *) __attribute__((__format_arg__ (2)));
int fpurge(FILE *);
void setbuffer(FILE *, char *, int);
int setlinebuf(FILE *);
int vasprintf(char **, const char *, __va_list)
     __attribute__((__format__ (__printf__, 2, 0)));






extern const int sys_nerr;
extern const char * const sys_errlist[];




FILE *funopen(const void *,
     int (*)(void *, char *, int),
     int (*)(void *, const char *, int),
     fpos_t (*)(void *, fpos_t, int),
     int (*)(void *));
int __srget(FILE *);
int __swbuf(int, FILE *);







static inline int __sputc(int _c, FILE *_p) {
 if (--_p->_w >= 0 || (_p->_w >= _p->_lbfsize && (char)_c != '\n'))
  return (*_p->_p++ = _c);
 else
  return (__swbuf(_c, _p));
}
extern int __isthreaded;
}
namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::FILE;
  using ::fpos_t;

  using ::clearerr;
  using ::fclose;
  using ::feof;
  using ::ferror;
  using ::fflush;
  using ::fgetc;
  using ::fgetpos;
  using ::fgets;
  using ::fopen;
  using ::fprintf;
  using ::fputc;
  using ::fputs;
  using ::fread;
  using ::freopen;
  using ::fscanf;
  using ::fseek;
  using ::fsetpos;
  using ::ftell;
  using ::fwrite;
  using ::getc;
  using ::getchar;
  using ::gets;
  using ::perror;
  using ::printf;
  using ::putc;
  using ::putchar;
  using ::puts;
  using ::remove;
  using ::rename;
  using ::rewind;
  using ::scanf;
  using ::setbuf;
  using ::setvbuf;
  using ::sprintf;
  using ::sscanf;
  using ::tmpfile;
  using ::tmpnam;
  using ::ungetc;
  using ::vfprintf;
  using ::vprintf;
  using ::vsprintf;

}








namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::va_list;

}



namespace std __attribute__ ((__visibility__ ("default"))) {

  typedef int* __c_locale;





  inline int
  __convert_from_v(const __c_locale&, char* __out,
     const int __size __attribute__((__unused__)),
     const char* __fmt, ...)
  {
    char* __old = std::setlocale(4, __null);
    char* __sav = __null;
    if (std::strcmp(__old, "C"))
      {
 __sav = new char[std::strlen(__old) + 1];
 std::strcpy(__sav, __old);
 std::setlocale(4, "C");
      }

    va_list __args;
    __builtin_va_start((__args), (__fmt));




    const int __ret = std::vsprintf(__out, __fmt, __args);


    __builtin_va_end(__args);

    if (__sav)
      {
 std::setlocale(4, __sav);
 delete [] __sav;
      }
    return __ret;
  }

}
struct sched_param {
        int sched_priority;
};
struct timespec;

extern "C" {
int sched_get_priority_max(int);
int sched_get_priority_min(int);
int sched_getparam(pid_t, struct sched_param *);
int sched_getscheduler(pid_t);
int sched_rr_get_interval(pid_t, struct timespec *);
int sched_setparam(pid_t, const struct sched_param *);
int sched_setscheduler(pid_t, int, const struct sched_param *);
int sched_yield(void);
}
struct tm {
 int tm_sec;
 int tm_min;
 int tm_hour;
 int tm_mday;
 int tm_mon;
 int tm_year;
 int tm_wday;
 int tm_yday;
 int tm_isdst;
 long tm_gmtoff;
 char *tm_zone;
};


extern char *tzname[];


extern "C" {
char *asctime(const struct tm *);
clock_t clock(void);
char *ctime(const time_t *);
double difftime(time_t, time_t);

struct tm *gmtime(const time_t *);
struct tm *localtime(const time_t *);
time_t mktime(struct tm *);
size_t strftime(char * , size_t, const char * ,
    const struct tm * );
time_t time(time_t *);

struct sigevent;
int timer_create(clockid_t, struct sigevent *, timer_t *);
int timer_delete(timer_t);
int timer_gettime(timer_t, struct itimerspec *);
int timer_getoverrun(timer_t);
int timer_settime(timer_t, int, const struct itimerspec *,
 struct itimerspec *);


void tzset(void);



int clock_getres(clockid_t, struct timespec *);
int clock_gettime(clockid_t, struct timespec *);
int clock_settime(clockid_t, const struct timespec *);

int nanosleep(const struct timespec *, struct timespec *);



char *asctime_r(const struct tm *, char *);
char *ctime_r(const time_t *, char *);
struct tm *gmtime_r(const time_t *, struct tm *);
struct tm *localtime_r(const time_t *, struct tm *);



char *strptime(const char * , const char * ,
    struct tm * );



char *timezone(int, int);
void tzsetwall(void);
time_t timelocal(struct tm * const);
time_t timegm(struct tm * const);

}
enum pthread_mutextype {
 PTHREAD_MUTEX_ERRORCHECK = 1,
 PTHREAD_MUTEX_RECURSIVE = 2,
 PTHREAD_MUTEX_NORMAL = 3,
 PTHREAD_MUTEX_ADAPTIVE_NP = 4,
 PTHREAD_MUTEX_TYPE_MAX
};



struct _pthread_cleanup_info {
 __uintptr_t pthread_cleanup_pad[8];
};




extern "C" {
int pthread_atfork(void (*)(void), void (*)(void), void (*)(void));
int pthread_attr_destroy(pthread_attr_t *);
int pthread_attr_getstack(const pthread_attr_t * ,
   void ** , size_t * );
int pthread_attr_getstacksize(const pthread_attr_t *, size_t *);
int pthread_attr_getguardsize(const pthread_attr_t *, size_t *);
int pthread_attr_getstackaddr(const pthread_attr_t *, void **);
int pthread_attr_getdetachstate(const pthread_attr_t *, int *);
int pthread_attr_init(pthread_attr_t *);
int pthread_attr_setstacksize(pthread_attr_t *, size_t);
int pthread_attr_setguardsize(pthread_attr_t *, size_t);
int pthread_attr_setstack(pthread_attr_t *, void *, size_t);
int pthread_attr_setstackaddr(pthread_attr_t *, void *);
int pthread_attr_setdetachstate(pthread_attr_t *, int);
int pthread_barrier_destroy(pthread_barrier_t *);
int pthread_barrier_init(pthread_barrier_t *,
   const pthread_barrierattr_t *, unsigned);
int pthread_barrier_wait(pthread_barrier_t *);
int pthread_barrierattr_destroy(pthread_barrierattr_t *);
int pthread_barrierattr_getpshared(const pthread_barrierattr_t *,
   int *);
int pthread_barrierattr_init(pthread_barrierattr_t *);
int pthread_barrierattr_setpshared(pthread_barrierattr_t *, int);
int pthread_condattr_destroy(pthread_condattr_t *);
int pthread_condattr_getclock(const pthread_condattr_t *,
   clockid_t *);
int pthread_condattr_getpshared(const pthread_condattr_t *, int *);
int pthread_condattr_init(pthread_condattr_t *);
int pthread_condattr_setclock(pthread_condattr_t *, clockid_t);
int pthread_condattr_setpshared(pthread_condattr_t *, int);
int pthread_cond_broadcast(pthread_cond_t *);
int pthread_cond_destroy(pthread_cond_t *);
int pthread_cond_init(pthread_cond_t *,
   const pthread_condattr_t *);
int pthread_cond_signal(pthread_cond_t *);
int pthread_cond_timedwait(pthread_cond_t *,
   pthread_mutex_t *, const struct timespec *);
int pthread_cond_wait(pthread_cond_t *, pthread_mutex_t *);
int pthread_create(pthread_t *, const pthread_attr_t *,
   void *(*) (void *), void *);
int pthread_detach(pthread_t);
int pthread_equal(pthread_t, pthread_t);
void pthread_exit(void *) __attribute__((__noreturn__));
void *pthread_getspecific(pthread_key_t);
int pthread_getcpuclockid(pthread_t, clockid_t *);
int pthread_join(pthread_t, void **);
int pthread_key_create(pthread_key_t *,
   void (*) (void *));
int pthread_key_delete(pthread_key_t);
int pthread_mutexattr_init(pthread_mutexattr_t *);
int pthread_mutexattr_destroy(pthread_mutexattr_t *);
int pthread_mutexattr_getpshared(const pthread_mutexattr_t *,
   int *);
int pthread_mutexattr_gettype(pthread_mutexattr_t *, int *);
int pthread_mutexattr_settype(pthread_mutexattr_t *, int);
int pthread_mutexattr_setpshared(pthread_mutexattr_t *, int);
int pthread_mutex_destroy(pthread_mutex_t *);
int pthread_mutex_init(pthread_mutex_t *,
   const pthread_mutexattr_t *);
int pthread_mutex_lock(pthread_mutex_t *);
int pthread_mutex_trylock(pthread_mutex_t *);
int pthread_mutex_timedlock(pthread_mutex_t *,
   const struct timespec *);
int pthread_mutex_unlock(pthread_mutex_t *);
int pthread_once(pthread_once_t *, void (*) (void));
int pthread_rwlock_destroy(pthread_rwlock_t *);
int pthread_rwlock_init(pthread_rwlock_t *,
   const pthread_rwlockattr_t *);
int pthread_rwlock_rdlock(pthread_rwlock_t *);
int pthread_rwlock_timedrdlock(pthread_rwlock_t *,
   const struct timespec *);
int pthread_rwlock_timedwrlock(pthread_rwlock_t *,
   const struct timespec *);
int pthread_rwlock_tryrdlock(pthread_rwlock_t *);
int pthread_rwlock_trywrlock(pthread_rwlock_t *);
int pthread_rwlock_unlock(pthread_rwlock_t *);
int pthread_rwlock_wrlock(pthread_rwlock_t *);
int pthread_rwlockattr_destroy(pthread_rwlockattr_t *);
int pthread_rwlockattr_getkind_np(const pthread_rwlockattr_t *,
   int *);
int pthread_rwlockattr_getpshared(const pthread_rwlockattr_t *,
   int *);
int pthread_rwlockattr_init(pthread_rwlockattr_t *);
int pthread_rwlockattr_setkind_np(pthread_rwlockattr_t *, int);
int pthread_rwlockattr_setpshared(pthread_rwlockattr_t *, int);
pthread_t pthread_self(void);
int pthread_setspecific(pthread_key_t, const void *);

int pthread_spin_init(pthread_spinlock_t *, int);
int pthread_spin_destroy(pthread_spinlock_t *);
int pthread_spin_lock(pthread_spinlock_t *);
int pthread_spin_trylock(pthread_spinlock_t *);
int pthread_spin_unlock(pthread_spinlock_t *);
int pthread_cancel(pthread_t);
int pthread_setcancelstate(int, int *);
int pthread_setcanceltype(int, int *);
void pthread_testcancel(void);


int pthread_getprio(pthread_t);
int pthread_setprio(pthread_t, int);
void pthread_yield(void);


int pthread_mutexattr_getprioceiling(pthread_mutexattr_t *,
   int *);
int pthread_mutexattr_setprioceiling(pthread_mutexattr_t *,
   int);
int pthread_mutex_getprioceiling(pthread_mutex_t *, int *);
int pthread_mutex_setprioceiling(pthread_mutex_t *, int, int *);

int pthread_mutexattr_getprotocol(pthread_mutexattr_t *, int *);
int pthread_mutexattr_setprotocol(pthread_mutexattr_t *, int);

int pthread_attr_getinheritsched(const pthread_attr_t *, int *);
int pthread_attr_getschedparam(const pthread_attr_t *,
   struct sched_param *);
int pthread_attr_getschedpolicy(const pthread_attr_t *, int *);
int pthread_attr_getscope(const pthread_attr_t *, int *);
int pthread_attr_setinheritsched(pthread_attr_t *, int);
int pthread_attr_setschedparam(pthread_attr_t *,
   const struct sched_param *);
int pthread_attr_setschedpolicy(pthread_attr_t *, int);
int pthread_attr_setscope(pthread_attr_t *, int);
int pthread_getschedparam(pthread_t pthread, int *,
   struct sched_param *);
int pthread_setschedparam(pthread_t, int,
   const struct sched_param *);

int pthread_getconcurrency(void);
int pthread_setconcurrency(int);


void __pthread_cleanup_push_imp(void (*)(void *), void *,
   struct _pthread_cleanup_info *);
void __pthread_cleanup_pop_imp(int);
}
extern "C" {

void _exit(int) __attribute__((__noreturn__));
int access(const char *, int);
unsigned int alarm(unsigned int);
int chdir(const char *);
int chown(const char *, uid_t, gid_t);
int close(int);
void closefrom(int);
int dup(int);
int dup2(int, int);
int execl(const char *, const char *, ...);
int execle(const char *, const char *, ...);
int execlp(const char *, const char *, ...);
int execv(const char *, char * const *);
int execve(const char *, char * const *, char * const *);
int execvp(const char *, char * const *);
pid_t fork(void);
long fpathconf(int, int);
char *getcwd(char *, size_t);
gid_t getegid(void);
uid_t geteuid(void);
gid_t getgid(void);
int getgroups(int, gid_t []);
char *getlogin(void);
pid_t getpgrp(void);
pid_t getpid(void);
pid_t getppid(void);
uid_t getuid(void);
int isatty(int);
int link(const char *, const char *);




long pathconf(const char *, int);
int pause(void);
int pipe(int *);
ssize_t read(int, void *, size_t);
int rmdir(const char *);
int setgid(gid_t);
int setpgid(pid_t, pid_t);
pid_t setsid(void);
int setuid(uid_t);
unsigned int sleep(unsigned int);
long sysconf(int);
pid_t tcgetpgrp(int);
int tcsetpgrp(int, pid_t);
char *ttyname(int);
int ttyname_r(int, char *, size_t);
int unlink(const char *);
ssize_t write(int, const void *, size_t);



size_t confstr(int, char *, size_t);


int getopt(int, char * const [], const char *);

extern char *optarg;
extern int optind, opterr, optopt;





int fsync(int);
int getlogin_r(char *, int);




int fchown(int, uid_t, gid_t);
ssize_t readlink(const char * , char * , size_t);


int gethostname(char *, size_t);
int setegid(gid_t);
int seteuid(uid_t);




int getsid(pid_t _pid);
int fchdir(int);
int getpgid(pid_t _pid);
int lchown(const char *, uid_t, gid_t);
ssize_t pread(int, void *, size_t, off_t);
ssize_t pwrite(int, const void *, size_t, off_t);
int faccessat(int, const char *, int, int);
int fchownat(int, const char *, uid_t, gid_t, int);
int fexecve(int, char *const [], char *const []);
int linkat(int, const char *, int, const char *, int);
ssize_t readlinkat(int, const char * , char * , size_t);
int symlinkat(const char *, int, const char *);
int unlinkat(int, const char *, int);
int symlink(const char * , const char * );




char *crypt(const char *, const char *);

int encrypt(char *, int);
long gethostid(void);
int lockf(int, int, off_t);
int nice(int);
int setpgrp(pid_t _pid, pid_t _pgrp);
int setregid(gid_t, gid_t);
int setreuid(uid_t, uid_t);






void sync(void);




int brk(const void *);
int chroot(const char *);
int getdtablesize(void);
int getpagesize(void) __attribute__((__const__));
char *getpass(const char *);
void *sbrk(intptr_t);



char *getwd(char *);
useconds_t
  ualarm(useconds_t, useconds_t);
int usleep(useconds_t);
pid_t vfork(void);



struct timeval;
int acct(const char *);
int async_daemon(void);
int check_utility_compat(const char *);
const char *
  crypt_get_format(void);
int crypt_set_format(const char *);
int des_cipher(const char *, char *, long, int);
int des_setkey(const char *key);
int eaccess(const char *, int);
void endusershell(void);
int exect(const char *, char * const *, char * const *);
int execvP(const char *, const char *, char * const *);
int feature_present(const char *);
char *fflagstostr(u_long);
int getdomainname(char *, int);
int getgrouplist(const char *, gid_t, gid_t *, int *);
int getloginclass(char *, size_t);
mode_t getmode(const void *, mode_t);
int getosreldate(void);
int getpeereid(int, uid_t *, gid_t *);
int getresgid(gid_t *, gid_t *, gid_t *);
int getresuid(uid_t *, uid_t *, uid_t *);
char *getusershell(void);
int initgroups(const char *, gid_t);
int iruserok(unsigned long, int, const char *, const char *);
int iruserok_sa(const void *, int, int, const char *, const char *);
int issetugid(void);
void __FreeBSD_libc_enter_restricted_mode(void);
long lpathconf(const char *, int);





int mknod(const char *, mode_t, dev_t);






int mkstemps(char *, int);




int nfssvc(int, void *);
int nlm_syscall(int, int, int, char **);
int profil(char *, size_t, vm_offset_t, int);
int rcmd(char **, int, const char *, const char *, const char *, int *);
int rcmd_af(char **, int, const char *,
  const char *, const char *, int *, int);
int rcmdsh(char **, int, const char *,
  const char *, const char *, const char *);
char *re_comp(const char *);
int re_exec(const char *);
int reboot(int);
int revoke(const char *);
pid_t rfork(int);
pid_t rfork_thread(int, void *, int (*)(void *), void *);
int rresvport(int *);
int rresvport_af(int *, int);
int ruserok(const char *, int, const char *, const char *);






int setdomainname(const char *, int);
int setgroups(int, const gid_t *);
void sethostid(long);
int sethostname(const char *, int);




int setlogin(const char *);
int setloginclass(const char *);
void *setmode(const char *);
void setproctitle(const char *_fmt, ...) __attribute__((__format__ (__printf0__, 1, 2)));
int setresgid(gid_t, gid_t, gid_t);
int setresuid(uid_t, uid_t, uid_t);
int setrgid(gid_t);
int setruid(uid_t);
void setusershell(void);
int strtofflags(char **, u_long *, u_long *);
int swapon(const char *);
int swapoff(const char *);
int syscall(int, ...);
off_t __syscall(quad_t, ...);
int undelete(const char *);
int unwhiteout(const char *);
void *valloc(size_t);



extern int optreset;


}

typedef pthread_key_t __gthread_key_t;
typedef pthread_once_t __gthread_once_t;
typedef pthread_mutex_t __gthread_mutex_t;
typedef pthread_mutex_t __gthread_recursive_mutex_t;
static __typeof(pthread_once) __gthrw_pthread_once __attribute__ ((__weakref__("pthread_once")));
static __typeof(pthread_getspecific) __gthrw_pthread_getspecific __attribute__ ((__weakref__("pthread_getspecific")));
static __typeof(pthread_setspecific) __gthrw_pthread_setspecific __attribute__ ((__weakref__("pthread_setspecific")));
static __typeof(pthread_create) __gthrw_pthread_create __attribute__ ((__weakref__("pthread_create")));
static __typeof(pthread_cancel) __gthrw_pthread_cancel __attribute__ ((__weakref__("pthread_cancel")));
static __typeof(pthread_mutex_lock) __gthrw_pthread_mutex_lock __attribute__ ((__weakref__("pthread_mutex_lock")));
static __typeof(pthread_mutex_trylock) __gthrw_pthread_mutex_trylock __attribute__ ((__weakref__("pthread_mutex_trylock")));
static __typeof(pthread_mutex_unlock) __gthrw_pthread_mutex_unlock __attribute__ ((__weakref__("pthread_mutex_unlock")));
static __typeof(pthread_mutex_init) __gthrw_pthread_mutex_init __attribute__ ((__weakref__("pthread_mutex_init")));


static __typeof(pthread_key_create) __gthrw_pthread_key_create __attribute__ ((__weakref__("pthread_key_create")));
static __typeof(pthread_key_delete) __gthrw_pthread_key_delete __attribute__ ((__weakref__("pthread_key_delete")));
static __typeof(pthread_mutexattr_init) __gthrw_pthread_mutexattr_init __attribute__ ((__weakref__("pthread_mutexattr_init")));
static __typeof(pthread_mutexattr_settype) __gthrw_pthread_mutexattr_settype __attribute__ ((__weakref__("pthread_mutexattr_settype")));
static __typeof(pthread_mutexattr_destroy) __gthrw_pthread_mutexattr_destroy __attribute__ ((__weakref__("pthread_mutexattr_destroy")));
static volatile int __gthread_active = -1;

static void
__gthread_trigger (void)
{
  __gthread_active = 1;
}

static inline int
__gthread_active_p (void)
{
  static pthread_mutex_t __gthread_active_mutex = __null;
  static pthread_once_t __gthread_active_once = { 0, __null };


  int __gthread_active_latest_value = __gthread_active;




  if (__builtin_expect (__gthread_active_latest_value < 0, 0))
    {
      if (__gthrw_pthread_once)
 {


   __gthrw_pthread_mutex_lock (&__gthread_active_mutex);
   __gthrw_pthread_once (&__gthread_active_once, __gthread_trigger);
   __gthrw_pthread_mutex_unlock (&__gthread_active_mutex);
 }


      if (__gthread_active < 0)
 __gthread_active = 0;

      __gthread_active_latest_value = __gthread_active;
    }

  return __gthread_active_latest_value != 0;
}
static inline int
__gthread_once (__gthread_once_t *once, void (*func) (void))
{
  if (__gthread_active_p ())
    return __gthrw_pthread_once (once, func);
  else
    return -1;
}

static inline int
__gthread_key_create (__gthread_key_t *key, void (*dtor) (void *))
{
  return __gthrw_pthread_key_create (key, dtor);
}

static inline int
__gthread_key_delete (__gthread_key_t key)
{
  return __gthrw_pthread_key_delete (key);
}

static inline void *
__gthread_getspecific (__gthread_key_t key)
{
  return __gthrw_pthread_getspecific (key);
}

static inline int
__gthread_setspecific (__gthread_key_t key, const void *ptr)
{
  return __gthrw_pthread_setspecific (key, ptr);
}

static inline int
__gthread_mutex_lock (__gthread_mutex_t *mutex)
{
  if (__gthread_active_p ())
    return __gthrw_pthread_mutex_lock (mutex);
  else
    return 0;
}

static inline int
__gthread_mutex_trylock (__gthread_mutex_t *mutex)
{
  if (__gthread_active_p ())
    return __gthrw_pthread_mutex_trylock (mutex);
  else
    return 0;
}

static inline int
__gthread_mutex_unlock (__gthread_mutex_t *mutex)
{
  if (__gthread_active_p ())
    return __gthrw_pthread_mutex_unlock (mutex);
  else
    return 0;
}


static inline int
__gthread_recursive_mutex_init_function (__gthread_recursive_mutex_t *mutex)
{
  if (__gthread_active_p ())
    {
      pthread_mutexattr_t attr;
      int r;

      r = __gthrw_pthread_mutexattr_init (&attr);
      if (!r)
 r = __gthrw_pthread_mutexattr_settype (&attr, PTHREAD_MUTEX_RECURSIVE);
      if (!r)
 r = __gthrw_pthread_mutex_init (mutex, &attr);
      if (!r)
 r = __gthrw_pthread_mutexattr_destroy (&attr);
      return r;
    }
  return 0;
}


static inline int
__gthread_recursive_mutex_lock (__gthread_recursive_mutex_t *mutex)
{
  return __gthread_mutex_lock (mutex);
}

static inline int
__gthread_recursive_mutex_trylock (__gthread_recursive_mutex_t *mutex)
{
  return __gthread_mutex_trylock (mutex);
}

static inline int
__gthread_recursive_mutex_unlock (__gthread_recursive_mutex_t *mutex)
{
  return __gthread_mutex_unlock (mutex);
}








namespace std __attribute__ ((__visibility__ ("default"))) {

  typedef __gthread_mutex_t __c_lock;


  typedef FILE __c_file;

}


extern "C" {
unsigned long ___runetype(__ct_rune_t) __attribute__((__pure__));
__ct_rune_t ___tolower(__ct_rune_t) __attribute__((__pure__));
__ct_rune_t ___toupper(__ct_rune_t) __attribute__((__pure__));
}
extern int __mb_sb_limit;








typedef struct {
 __rune_t __min;
 __rune_t __max;
 __rune_t __map;
 unsigned long *__types;
} _RuneEntry;

typedef struct {
 int __nranges;
 _RuneEntry *__ranges;
} _RuneRange;

typedef struct {
 char __magic[8];
 char __encoding[32];

 __rune_t (*__sgetrune)(const char *, __size_t, char const **);
 int (*__sputrune)(__rune_t, char *, __size_t, char **);
 __rune_t __invalid_rune;

 unsigned long __runetype[(1 <<8 )];
 __rune_t __maplower[(1 <<8 )];
 __rune_t __mapupper[(1 <<8 )];






 _RuneRange __runetype_ext;
 _RuneRange __maplower_ext;
 _RuneRange __mapupper_ext;

 void *__variable;
 int __variable_len;
} _RuneLocale;


extern "C" {
extern const _RuneLocale _DefaultRuneLocale;
__attribute__((deprecated))
extern _RuneLocale *_CurrentRuneLocale;


extern _RuneLocale *__getCurrentRuneLocale(void);

}

static inline int
__maskrune(__ct_rune_t _c, unsigned long _f)
{
 return ((_c < 0 || _c >= (1 <<8 )) ? ___runetype(_c) :
  (__getCurrentRuneLocale())->__runetype[_c]) & _f;
}

static inline int
__sbmaskrune(__ct_rune_t _c, unsigned long _f)
{
 return (_c < 0 || _c >= __mb_sb_limit) ? 0 :
        (__getCurrentRuneLocale())->__runetype[_c] & _f;
}

static inline int
__istype(__ct_rune_t _c, unsigned long _f)
{
 return (!!__maskrune(_c, _f));
}

static inline int
__sbistype(__ct_rune_t _c, unsigned long _f)
{
 return (!!__sbmaskrune(_c, _f));
}

static inline int
__isctype(__ct_rune_t _c, unsigned long _f)
{
 return (_c < 0 || _c >= 128) ? 0 :
        !!(_DefaultRuneLocale.__runetype[_c] & _f);
}

static inline __ct_rune_t
__toupper(__ct_rune_t _c)
{
 return (_c < 0 || _c >= (1 <<8 )) ? ___toupper(_c) :
        (__getCurrentRuneLocale())->__mapupper[_c];
}

static inline __ct_rune_t
__sbtoupper(__ct_rune_t _c)
{
 return (_c < 0 || _c >= __mb_sb_limit) ? _c :
        (__getCurrentRuneLocale())->__mapupper[_c];
}

static inline __ct_rune_t
__tolower(__ct_rune_t _c)
{
 return (_c < 0 || _c >= (1 <<8 )) ? ___tolower(_c) :
        (__getCurrentRuneLocale())->__maplower[_c];
}

static inline __ct_rune_t
__sbtolower(__ct_rune_t _c)
{
 return (_c < 0 || _c >= __mb_sb_limit) ? _c :
        (__getCurrentRuneLocale())->__maplower[_c];
}

static inline int
__wcwidth(__ct_rune_t _c)
{
 unsigned int _x;

 if (_c == 0)
  return (0);
 _x = (unsigned int)__maskrune(_c, 0xe0000000L|0x00040000L);
 if ((_x & 0xe0000000L) != 0)
  return ((_x & 0xe0000000L) >> 30);
 return ((_x & 0x00040000L) != 0 ? 1 : -1);
}

extern "C" {
int isalnum(int);
int isalpha(int);
int iscntrl(int);
int isdigit(int);
int isgraph(int);
int islower(int);
int isprint(int);
int ispunct(int);
int isspace(int);
int isupper(int);
int isxdigit(int);
int tolower(int);
int toupper(int);


int isascii(int);
int toascii(int);



int isblank(int);



int digittoint(int);
int ishexnumber(int);
int isideogram(int);
int isnumber(int);
int isphonogram(int);
int isrune(int);
int isspecial(int);

}
namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::isalnum;
  using ::isalpha;
  using ::iscntrl;
  using ::isdigit;
  using ::isgraph;
  using ::islower;
  using ::isprint;
  using ::ispunct;
  using ::isspace;
  using ::isupper;
  using ::isxdigit;
  using ::tolower;
  using ::toupper;

}





namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::clock_t;
  using ::time_t;
  using ::tm;

  using ::clock;
  using ::difftime;
  using ::mktime;
  using ::time;
  using ::asctime;
  using ::ctime;
  using ::gmtime;
  using ::localtime;
  using ::strftime;

}


typedef __mbstate_t mbstate_t;
typedef __wint_t wint_t;
struct tm;

extern "C" {
wint_t btowc(int);
wint_t fgetwc(FILE *);
wchar_t *
 fgetws(wchar_t * , int, FILE * );
wint_t fputwc(wchar_t, FILE *);
int fputws(const wchar_t * , FILE * );
int fwide(FILE *, int);
int fwprintf(FILE * , const wchar_t * , ...);
int fwscanf(FILE * , const wchar_t * , ...);
wint_t getwc(FILE *);
wint_t getwchar(void);
size_t mbrlen(const char * , size_t, mbstate_t * );
size_t mbrtowc(wchar_t * , const char * , size_t,
     mbstate_t * );
int mbsinit(const mbstate_t *);
size_t mbsrtowcs(wchar_t * , const char ** , size_t,
     mbstate_t * );
wint_t putwc(wchar_t, FILE *);
wint_t putwchar(wchar_t);
int swprintf(wchar_t * , size_t n, const wchar_t * ,
     ...);
int swscanf(const wchar_t * , const wchar_t * , ...);
wint_t ungetwc(wint_t, FILE *);
int vfwprintf(FILE * , const wchar_t * ,
     __va_list);
int vswprintf(wchar_t * , size_t n, const wchar_t * ,
     __va_list);
int vwprintf(const wchar_t * , __va_list);
size_t wcrtomb(char * , wchar_t, mbstate_t * );
wchar_t *wcscat(wchar_t * , const wchar_t * );
wchar_t *wcschr(const wchar_t *, wchar_t) __attribute__((__pure__));
int wcscmp(const wchar_t *, const wchar_t *) __attribute__((__pure__));
int wcscoll(const wchar_t *, const wchar_t *);
wchar_t *wcscpy(wchar_t * , const wchar_t * );
size_t wcscspn(const wchar_t *, const wchar_t *) __attribute__((__pure__));
size_t wcsftime(wchar_t * , size_t, const wchar_t * ,
     const struct tm * );
size_t wcslen(const wchar_t *) __attribute__((__pure__));
wchar_t *wcsncat(wchar_t * , const wchar_t * ,
     size_t);
int wcsncmp(const wchar_t *, const wchar_t *, size_t) __attribute__((__pure__));
wchar_t *wcsncpy(wchar_t * , const wchar_t * , size_t);
wchar_t *wcspbrk(const wchar_t *, const wchar_t *) __attribute__((__pure__));
wchar_t *wcsrchr(const wchar_t *, wchar_t) __attribute__((__pure__));
size_t wcsrtombs(char * , const wchar_t ** , size_t,
     mbstate_t * );
size_t wcsspn(const wchar_t *, const wchar_t *) __attribute__((__pure__));
wchar_t *wcsstr(const wchar_t * , const wchar_t * )
     __attribute__((__pure__));
size_t wcsxfrm(wchar_t * , const wchar_t * , size_t);
int wctob(wint_t);
double wcstod(const wchar_t * , wchar_t ** );
wchar_t *wcstok(wchar_t * , const wchar_t * ,
     wchar_t ** );
long wcstol(const wchar_t * , wchar_t ** , int);
unsigned long
  wcstoul(const wchar_t * , wchar_t ** , int);
wchar_t *wmemchr(const wchar_t *, wchar_t, size_t) __attribute__((__pure__));
int wmemcmp(const wchar_t *, const wchar_t *, size_t) __attribute__((__pure__));
wchar_t *wmemcpy(wchar_t * , const wchar_t * , size_t);
wchar_t *wmemmove(wchar_t *, const wchar_t *, size_t);
wchar_t *wmemset(wchar_t *, wchar_t, size_t);
int wprintf(const wchar_t * , ...);
int wscanf(const wchar_t * , ...);
int vfwscanf(FILE * , const wchar_t * ,
     __va_list);
int vswscanf(const wchar_t * , const wchar_t * ,
     __va_list);
int vwscanf(const wchar_t * , __va_list);
float wcstof(const wchar_t * , wchar_t ** );
long double
 wcstold(const wchar_t * , wchar_t ** );


long long
 wcstoll(const wchar_t * , wchar_t ** , int);

unsigned long long
  wcstoull(const wchar_t * , wchar_t ** , int);




int wcswidth(const wchar_t *, size_t);
int wcwidth(wchar_t);




size_t mbsnrtowcs(wchar_t * , const char ** , size_t,
     size_t, mbstate_t * );
wchar_t *wcpcpy(wchar_t * , const wchar_t * );
wchar_t *wcpncpy(wchar_t * , const wchar_t * , size_t);
wchar_t *wcsdup(const wchar_t *) __attribute__((__malloc__));
int wcscasecmp(const wchar_t *, const wchar_t *);
int wcsncasecmp(const wchar_t *, const wchar_t *, size_t n);
size_t wcsnlen(const wchar_t *, size_t) __attribute__((__pure__));
size_t wcsnrtombs(char * , const wchar_t ** , size_t,
     size_t, mbstate_t * );



wchar_t *fgetwln(FILE * , size_t * );
size_t wcslcat(wchar_t *, const wchar_t *, size_t);
size_t wcslcpy(wchar_t *, const wchar_t *, size_t);

}
namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::mbstate_t;

}
namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::wint_t;

  using ::btowc;
  using ::fgetwc;
  using ::fgetws;
  using ::fputwc;
  using ::fputws;
  using ::fwide;
  using ::fwprintf;
  using ::fwscanf;
  using ::getwc;
  using ::getwchar;
  using ::mbrlen;
  using ::mbrtowc;
  using ::mbsinit;
  using ::mbsrtowcs;
  using ::putwc;
  using ::putwchar;
  using ::swprintf;
  using ::swscanf;
  using ::ungetwc;
  using ::vfwprintf;

  using ::vfwscanf;

  using ::vswprintf;

  using ::vswscanf;

  using ::vwprintf;

  using ::vwscanf;

  using ::wcrtomb;
  using ::wcscat;
  using ::wcscmp;
  using ::wcscoll;
  using ::wcscpy;
  using ::wcscspn;
  using ::wcsftime;
  using ::wcslen;
  using ::wcsncat;
  using ::wcsncmp;
  using ::wcsncpy;
  using ::wcsrtombs;
  using ::wcsspn;
  using ::wcstod;

  using ::wcstof;

  using ::wcstok;
  using ::wcstol;
  using ::wcstoul;
  using ::wcsxfrm;
  using ::wctob;
  using ::wmemcmp;
  using ::wmemcpy;
  using ::wmemmove;
  using ::wmemset;
  using ::wprintf;
  using ::wscanf;

  using ::wcschr;

  inline wchar_t*
  wcschr(wchar_t* __p, wchar_t __c)
  { return wcschr(const_cast<const wchar_t*>(__p), __c); }

  using ::wcspbrk;

  inline wchar_t*
  wcspbrk(wchar_t* __s1, const wchar_t* __s2)
  { return wcspbrk(const_cast<const wchar_t*>(__s1), __s2); }

  using ::wcsrchr;

  inline wchar_t*
  wcsrchr(wchar_t* __p, wchar_t __c)
  { return wcsrchr(const_cast<const wchar_t*>(__p), __c); }

  using ::wcsstr;

  inline wchar_t*
  wcsstr(wchar_t* __s1, const wchar_t* __s2)
  { return wcsstr(const_cast<const wchar_t*>(__s1), __s2); }

  using ::wmemchr;

  inline wchar_t*
  wmemchr(wchar_t* __p, wchar_t __c, size_t __n)
  { return wmemchr(const_cast<const wchar_t*>(__p), __c, __n); }

}





namespace std __attribute__ ((__visibility__ ("default"))) {
  typedef int64_t streamoff;





  typedef ptrdiff_t streamsize;

  template<typename _StateT>
    class fpos;
  template<typename _StateT>
    class fpos
    {
    private:
      streamoff _M_off;
      _StateT _M_state;

    public:




      fpos()
      : _M_off(0), _M_state() { }
      fpos(streamoff __off)
      : _M_off(__off), _M_state() { }


      operator streamoff() const { return _M_off; }


      void
      state(_StateT __st)
      { _M_state = __st; }


      _StateT
      state() const
      { return _M_state; }





      fpos&
      operator+=(streamoff __off)
      {
 _M_off += __off;
 return *this;
      }





      fpos&
      operator-=(streamoff __off)
      {
 _M_off -= __off;
 return *this;
      }







      fpos
      operator+(streamoff __off) const
      {
 fpos __pos(*this);
 __pos += __off;
 return __pos;
      }







      fpos
      operator-(streamoff __off) const
      {
 fpos __pos(*this);
 __pos -= __off;
 return __pos;
      }






      streamoff
      operator-(const fpos& __other) const
      { return _M_off - __other._M_off; }
    };






  template<typename _StateT>
    inline bool
    operator==(const fpos<_StateT>& __lhs, const fpos<_StateT>& __rhs)
    { return streamoff(__lhs) == streamoff(__rhs); }

  template<typename _StateT>
    inline bool
    operator!=(const fpos<_StateT>& __lhs, const fpos<_StateT>& __rhs)
    { return streamoff(__lhs) != streamoff(__rhs); }





  typedef fpos<mbstate_t> streampos;

  typedef fpos<mbstate_t> wstreampos;

}

namespace std __attribute__ ((__visibility__ ("default"))) {


  void
  __throw_bad_exception(void) __attribute__((__noreturn__));


  void
  __throw_bad_alloc(void) __attribute__((__noreturn__));


  void
  __throw_bad_cast(void) __attribute__((__noreturn__));

  void
  __throw_bad_typeid(void) __attribute__((__noreturn__));


  void
  __throw_logic_error(const char*) __attribute__((__noreturn__));

  void
  __throw_domain_error(const char*) __attribute__((__noreturn__));

  void
  __throw_invalid_argument(const char*) __attribute__((__noreturn__));

  void
  __throw_length_error(const char*) __attribute__((__noreturn__));

  void
  __throw_out_of_range(const char*) __attribute__((__noreturn__));

  void
  __throw_runtime_error(const char*) __attribute__((__noreturn__));

  void
  __throw_range_error(const char*) __attribute__((__noreturn__));

  void
  __throw_overflow_error(const char*) __attribute__((__noreturn__));

  void
  __throw_underflow_error(const char*) __attribute__((__noreturn__));


  void
  __throw_ios_failure(const char*) __attribute__((__noreturn__));

}

namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_ios;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_streambuf;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_istream;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_ostream;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_iostream;

  template<typename _CharT, typename _Traits = char_traits<_CharT>,
     typename _Alloc = allocator<_CharT> >
    class basic_stringbuf;

  template<typename _CharT, typename _Traits = char_traits<_CharT>,
    typename _Alloc = allocator<_CharT> >
    class basic_istringstream;

  template<typename _CharT, typename _Traits = char_traits<_CharT>,
    typename _Alloc = allocator<_CharT> >
    class basic_ostringstream;

  template<typename _CharT, typename _Traits = char_traits<_CharT>,
    typename _Alloc = allocator<_CharT> >
    class basic_stringstream;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_filebuf;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_ifstream;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_ofstream;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class basic_fstream;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class istreambuf_iterator;

  template<typename _CharT, typename _Traits = char_traits<_CharT> >
    class ostreambuf_iterator;



  class ios_base;
  typedef basic_ios<char> ios;
  typedef basic_streambuf<char> streambuf;
  typedef basic_istream<char> istream;
  typedef basic_ostream<char> ostream;
  typedef basic_iostream<char> iostream;
  typedef basic_stringbuf<char> stringbuf;
  typedef basic_istringstream<char> istringstream;
  typedef basic_ostringstream<char> ostringstream;
  typedef basic_stringstream<char> stringstream;
  typedef basic_filebuf<char> filebuf;
  typedef basic_ifstream<char> ifstream;
  typedef basic_ofstream<char> ofstream;
  typedef basic_fstream<char> fstream;


  typedef basic_ios<wchar_t> wios;
  typedef basic_streambuf<wchar_t> wstreambuf;
  typedef basic_istream<wchar_t> wistream;
  typedef basic_ostream<wchar_t> wostream;
  typedef basic_iostream<wchar_t> wiostream;
  typedef basic_stringbuf<wchar_t> wstringbuf;
  typedef basic_istringstream<wchar_t> wistringstream;
  typedef basic_ostringstream<wchar_t> wostringstream;
  typedef basic_stringstream<wchar_t> wstringstream;
  typedef basic_filebuf<wchar_t> wfilebuf;
  typedef basic_ifstream<wchar_t> wifstream;
  typedef basic_ofstream<wchar_t> wofstream;
  typedef basic_fstream<wchar_t> wfstream;



}




namespace std __attribute__ ((__visibility__ ("default"))) {
  struct input_iterator_tag {};

  struct output_iterator_tag {};

  struct forward_iterator_tag : public input_iterator_tag {};


  struct bidirectional_iterator_tag : public forward_iterator_tag {};


  struct random_access_iterator_tag : public bidirectional_iterator_tag {};
  template<typename _Category, typename _Tp, typename _Distance = ptrdiff_t,
           typename _Pointer = _Tp*, typename _Reference = _Tp&>
    struct iterator
    {

      typedef _Category iterator_category;

      typedef _Tp value_type;

      typedef _Distance difference_type;

      typedef _Pointer pointer;

      typedef _Reference reference;
    };







  template<typename _Iterator>
    struct iterator_traits
    {
      typedef typename _Iterator::iterator_category iterator_category;
      typedef typename _Iterator::value_type value_type;
      typedef typename _Iterator::difference_type difference_type;
      typedef typename _Iterator::pointer pointer;
      typedef typename _Iterator::reference reference;
    };

  template<typename _Tp>
    struct iterator_traits<_Tp*>
    {
      typedef random_access_iterator_tag iterator_category;
      typedef _Tp value_type;
      typedef ptrdiff_t difference_type;
      typedef _Tp* pointer;
      typedef _Tp& reference;
    };

  template<typename _Tp>
    struct iterator_traits<const _Tp*>
    {
      typedef random_access_iterator_tag iterator_category;
      typedef _Tp value_type;
      typedef ptrdiff_t difference_type;
      typedef const _Tp* pointer;
      typedef const _Tp& reference;
    };







  template<typename _Iter>
    inline typename iterator_traits<_Iter>::iterator_category
    __iterator_category(const _Iter&)
    { return typename iterator_traits<_Iter>::iterator_category(); }

}

namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _InputIterator>
    inline typename iterator_traits<_InputIterator>::difference_type
    __distance(_InputIterator __first, _InputIterator __last,
               input_iterator_tag)
    {



      typename iterator_traits<_InputIterator>::difference_type __n = 0;
      while (__first != __last)
 {
   ++__first;
   ++__n;
 }
      return __n;
    }

  template<typename _RandomAccessIterator>
    inline typename iterator_traits<_RandomAccessIterator>::difference_type
    __distance(_RandomAccessIterator __first, _RandomAccessIterator __last,
               random_access_iterator_tag)
    {



      return __last - __first;
    }
  template<typename _InputIterator>
    inline typename iterator_traits<_InputIterator>::difference_type
    distance(_InputIterator __first, _InputIterator __last)
    {

      return std::__distance(__first, __last,
        std::__iterator_category(__first));
    }

  template<typename _InputIterator, typename _Distance>
    inline void
    __advance(_InputIterator& __i, _Distance __n, input_iterator_tag)
    {


      while (__n--)
 ++__i;
    }

  template<typename _BidirectionalIterator, typename _Distance>
    inline void
    __advance(_BidirectionalIterator& __i, _Distance __n,
       bidirectional_iterator_tag)
    {



      if (__n > 0)
        while (__n--)
   ++__i;
      else
        while (__n++)
   --__i;
    }

  template<typename _RandomAccessIterator, typename _Distance>
    inline void
    __advance(_RandomAccessIterator& __i, _Distance __n,
              random_access_iterator_tag)
    {



      __i += __n;
    }
  template<typename _InputIterator, typename _Distance>
    inline void
    advance(_InputIterator& __i, _Distance __n)
    {

      typename iterator_traits<_InputIterator>::difference_type __d = __n;
      std::__advance(__i, __d, std::__iterator_category(__i));
    }

}
namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _Iterator>
    class reverse_iterator
    : public iterator<typename iterator_traits<_Iterator>::iterator_category,
        typename iterator_traits<_Iterator>::value_type,
        typename iterator_traits<_Iterator>::difference_type,
        typename iterator_traits<_Iterator>::pointer,
                      typename iterator_traits<_Iterator>::reference>
    {
    protected:
      _Iterator current;

    public:
      typedef _Iterator iterator_type;
      typedef typename iterator_traits<_Iterator>::difference_type
              difference_type;
      typedef typename iterator_traits<_Iterator>::reference reference;
      typedef typename iterator_traits<_Iterator>::pointer pointer;

    public:






      reverse_iterator() : current() { }




      explicit
      reverse_iterator(iterator_type __x) : current(__x) { }




      reverse_iterator(const reverse_iterator& __x)
      : current(__x.current) { }





      template<typename _Iter>
        reverse_iterator(const reverse_iterator<_Iter>& __x)
 : current(__x.base()) { }




      iterator_type
      base() const
      { return current; }






      reference
      operator*() const
      {
 _Iterator __tmp = current;
 return *--__tmp;
      }






      pointer
      operator->() const
      { return &(operator*()); }






      reverse_iterator&
      operator++()
      {
 --current;
 return *this;
      }






      reverse_iterator
      operator++(int)
      {
 reverse_iterator __tmp = *this;
 --current;
 return __tmp;
      }






      reverse_iterator&
      operator--()
      {
 ++current;
 return *this;
      }






      reverse_iterator
      operator--(int)
      {
 reverse_iterator __tmp = *this;
 ++current;
 return __tmp;
      }






      reverse_iterator
      operator+(difference_type __n) const
      { return reverse_iterator(current - __n); }






      reverse_iterator&
      operator+=(difference_type __n)
      {
 current -= __n;
 return *this;
      }






      reverse_iterator
      operator-(difference_type __n) const
      { return reverse_iterator(current + __n); }






      reverse_iterator&
      operator-=(difference_type __n)
      {
 current += __n;
 return *this;
      }






      reference
      operator[](difference_type __n) const
      { return *(*this + __n); }
    };
  template<typename _Iterator>
    inline bool
    operator==(const reverse_iterator<_Iterator>& __x,
        const reverse_iterator<_Iterator>& __y)
    { return __x.base() == __y.base(); }

  template<typename _Iterator>
    inline bool
    operator<(const reverse_iterator<_Iterator>& __x,
       const reverse_iterator<_Iterator>& __y)
    { return __y.base() < __x.base(); }

  template<typename _Iterator>
    inline bool
    operator!=(const reverse_iterator<_Iterator>& __x,
        const reverse_iterator<_Iterator>& __y)
    { return !(__x == __y); }

  template<typename _Iterator>
    inline bool
    operator>(const reverse_iterator<_Iterator>& __x,
       const reverse_iterator<_Iterator>& __y)
    { return __y < __x; }

  template<typename _Iterator>
    inline bool
    operator<=(const reverse_iterator<_Iterator>& __x,
        const reverse_iterator<_Iterator>& __y)
    { return !(__y < __x); }

  template<typename _Iterator>
    inline bool
    operator>=(const reverse_iterator<_Iterator>& __x,
        const reverse_iterator<_Iterator>& __y)
    { return !(__x < __y); }

  template<typename _Iterator>
    inline typename reverse_iterator<_Iterator>::difference_type
    operator-(const reverse_iterator<_Iterator>& __x,
       const reverse_iterator<_Iterator>& __y)
    { return __y.base() - __x.base(); }

  template<typename _Iterator>
    inline reverse_iterator<_Iterator>
    operator+(typename reverse_iterator<_Iterator>::difference_type __n,
       const reverse_iterator<_Iterator>& __x)
    { return reverse_iterator<_Iterator>(__x.base() - __n); }



  template<typename _IteratorL, typename _IteratorR>
    inline bool
    operator==(const reverse_iterator<_IteratorL>& __x,
        const reverse_iterator<_IteratorR>& __y)
    { return __x.base() == __y.base(); }

  template<typename _IteratorL, typename _IteratorR>
    inline bool
    operator<(const reverse_iterator<_IteratorL>& __x,
       const reverse_iterator<_IteratorR>& __y)
    { return __y.base() < __x.base(); }

  template<typename _IteratorL, typename _IteratorR>
    inline bool
    operator!=(const reverse_iterator<_IteratorL>& __x,
        const reverse_iterator<_IteratorR>& __y)
    { return !(__x == __y); }

  template<typename _IteratorL, typename _IteratorR>
    inline bool
    operator>(const reverse_iterator<_IteratorL>& __x,
       const reverse_iterator<_IteratorR>& __y)
    { return __y < __x; }

  template<typename _IteratorL, typename _IteratorR>
    inline bool
    operator<=(const reverse_iterator<_IteratorL>& __x,
        const reverse_iterator<_IteratorR>& __y)
    { return !(__y < __x); }

  template<typename _IteratorL, typename _IteratorR>
    inline bool
    operator>=(const reverse_iterator<_IteratorL>& __x,
        const reverse_iterator<_IteratorR>& __y)
    { return !(__x < __y); }

  template<typename _IteratorL, typename _IteratorR>
    inline typename reverse_iterator<_IteratorL>::difference_type
    operator-(const reverse_iterator<_IteratorL>& __x,
       const reverse_iterator<_IteratorR>& __y)
    { return __y.base() - __x.base(); }
  template<typename _Container>
    class back_insert_iterator
    : public iterator<output_iterator_tag, void, void, void, void>
    {
    protected:
      _Container* container;

    public:

      typedef _Container container_type;


      explicit
      back_insert_iterator(_Container& __x) : container(&__x) { }
      back_insert_iterator&
      operator=(typename _Container::const_reference __value)
      {
 container->push_back(__value);
 return *this;
      }


      back_insert_iterator&
      operator*()
      { return *this; }


      back_insert_iterator&
      operator++()
      { return *this; }


      back_insert_iterator
      operator++(int)
      { return *this; }
    };
  template<typename _Container>
    inline back_insert_iterator<_Container>
    back_inserter(_Container& __x)
    { return back_insert_iterator<_Container>(__x); }
  template<typename _Container>
    class front_insert_iterator
    : public iterator<output_iterator_tag, void, void, void, void>
    {
    protected:
      _Container* container;

    public:

      typedef _Container container_type;


      explicit front_insert_iterator(_Container& __x) : container(&__x) { }
      front_insert_iterator&
      operator=(typename _Container::const_reference __value)
      {
 container->push_front(__value);
 return *this;
      }


      front_insert_iterator&
      operator*()
      { return *this; }


      front_insert_iterator&
      operator++()
      { return *this; }


      front_insert_iterator
      operator++(int)
      { return *this; }
    };
  template<typename _Container>
    inline front_insert_iterator<_Container>
    front_inserter(_Container& __x)
    { return front_insert_iterator<_Container>(__x); }
  template<typename _Container>
    class insert_iterator
    : public iterator<output_iterator_tag, void, void, void, void>
    {
    protected:
      _Container* container;
      typename _Container::iterator iter;

    public:

      typedef _Container container_type;





      insert_iterator(_Container& __x, typename _Container::iterator __i)
      : container(&__x), iter(__i) {}
      insert_iterator&
      operator=(const typename _Container::const_reference __value)
      {
 iter = container->insert(iter, __value);
 ++iter;
 return *this;
      }


      insert_iterator&
      operator*()
      { return *this; }


      insert_iterator&
      operator++()
      { return *this; }


      insert_iterator&
      operator++(int)
      { return *this; }
    };
  template<typename _Container, typename _Iterator>
    inline insert_iterator<_Container>
    inserter(_Container& __x, _Iterator __i)
    {
      return insert_iterator<_Container>(__x,
      typename _Container::iterator(__i));
    }

}

namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {
  using std::iterator_traits;
  using std::iterator;
  template<typename _Iterator, typename _Container>
    class __normal_iterator
    {
    protected:
      _Iterator _M_current;

    public:
      typedef typename iterator_traits<_Iterator>::iterator_category
                                                             iterator_category;
      typedef typename iterator_traits<_Iterator>::value_type value_type;
      typedef typename iterator_traits<_Iterator>::difference_type
                                                             difference_type;
      typedef typename iterator_traits<_Iterator>::reference reference;
      typedef typename iterator_traits<_Iterator>::pointer pointer;

      __normal_iterator() : _M_current(_Iterator()) { }

      explicit
      __normal_iterator(const _Iterator& __i) : _M_current(__i) { }


      template<typename _Iter>
        __normal_iterator(const __normal_iterator<_Iter,
     typename __enable_if<
              (std::__are_same<_Iter, typename _Container::pointer>::__value),
        _Container>::__type>& __i)
        : _M_current(__i.base()) { }


      reference
      operator*() const
      { return *_M_current; }

      pointer
      operator->() const
      { return _M_current; }

      __normal_iterator&
      operator++()
      {
 ++_M_current;
 return *this;
      }

      __normal_iterator
      operator++(int)
      { return __normal_iterator(_M_current++); }


      __normal_iterator&
      operator--()
      {
 --_M_current;
 return *this;
      }

      __normal_iterator
      operator--(int)
      { return __normal_iterator(_M_current--); }


      reference
      operator[](const difference_type& __n) const
      { return _M_current[__n]; }

      __normal_iterator&
      operator+=(const difference_type& __n)
      { _M_current += __n; return *this; }

      __normal_iterator
      operator+(const difference_type& __n) const
      { return __normal_iterator(_M_current + __n); }

      __normal_iterator&
      operator-=(const difference_type& __n)
      { _M_current -= __n; return *this; }

      __normal_iterator
      operator-(const difference_type& __n) const
      { return __normal_iterator(_M_current - __n); }

      const _Iterator&
      base() const
      { return _M_current; }
    };
  template<typename _IteratorL, typename _IteratorR, typename _Container>
    inline bool
    operator==(const __normal_iterator<_IteratorL, _Container>& __lhs,
        const __normal_iterator<_IteratorR, _Container>& __rhs)
    { return __lhs.base() == __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline bool
    operator==(const __normal_iterator<_Iterator, _Container>& __lhs,
        const __normal_iterator<_Iterator, _Container>& __rhs)
    { return __lhs.base() == __rhs.base(); }

  template<typename _IteratorL, typename _IteratorR, typename _Container>
    inline bool
    operator!=(const __normal_iterator<_IteratorL, _Container>& __lhs,
        const __normal_iterator<_IteratorR, _Container>& __rhs)
    { return __lhs.base() != __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline bool
    operator!=(const __normal_iterator<_Iterator, _Container>& __lhs,
        const __normal_iterator<_Iterator, _Container>& __rhs)
    { return __lhs.base() != __rhs.base(); }


  template<typename _IteratorL, typename _IteratorR, typename _Container>
    inline bool
    operator<(const __normal_iterator<_IteratorL, _Container>& __lhs,
       const __normal_iterator<_IteratorR, _Container>& __rhs)
    { return __lhs.base() < __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline bool
    operator<(const __normal_iterator<_Iterator, _Container>& __lhs,
       const __normal_iterator<_Iterator, _Container>& __rhs)
    { return __lhs.base() < __rhs.base(); }

  template<typename _IteratorL, typename _IteratorR, typename _Container>
    inline bool
    operator>(const __normal_iterator<_IteratorL, _Container>& __lhs,
       const __normal_iterator<_IteratorR, _Container>& __rhs)
    { return __lhs.base() > __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline bool
    operator>(const __normal_iterator<_Iterator, _Container>& __lhs,
       const __normal_iterator<_Iterator, _Container>& __rhs)
    { return __lhs.base() > __rhs.base(); }

  template<typename _IteratorL, typename _IteratorR, typename _Container>
    inline bool
    operator<=(const __normal_iterator<_IteratorL, _Container>& __lhs,
        const __normal_iterator<_IteratorR, _Container>& __rhs)
    { return __lhs.base() <= __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline bool
    operator<=(const __normal_iterator<_Iterator, _Container>& __lhs,
        const __normal_iterator<_Iterator, _Container>& __rhs)
    { return __lhs.base() <= __rhs.base(); }

  template<typename _IteratorL, typename _IteratorR, typename _Container>
    inline bool
    operator>=(const __normal_iterator<_IteratorL, _Container>& __lhs,
        const __normal_iterator<_IteratorR, _Container>& __rhs)
    { return __lhs.base() >= __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline bool
    operator>=(const __normal_iterator<_Iterator, _Container>& __lhs,
        const __normal_iterator<_Iterator, _Container>& __rhs)
    { return __lhs.base() >= __rhs.base(); }





  template<typename _IteratorL, typename _IteratorR, typename _Container>
    inline typename __normal_iterator<_IteratorL, _Container>::difference_type
    operator-(const __normal_iterator<_IteratorL, _Container>& __lhs,
       const __normal_iterator<_IteratorR, _Container>& __rhs)
    { return __lhs.base() - __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline typename __normal_iterator<_Iterator, _Container>::difference_type
    operator-(const __normal_iterator<_Iterator, _Container>& __lhs,
       const __normal_iterator<_Iterator, _Container>& __rhs)
    { return __lhs.base() - __rhs.base(); }

  template<typename _Iterator, typename _Container>
    inline __normal_iterator<_Iterator, _Container>
    operator+(typename __normal_iterator<_Iterator, _Container>::difference_type
       __n, const __normal_iterator<_Iterator, _Container>& __i)
    { return __normal_iterator<_Iterator, _Container>(__i.base() + __n); }

}

namespace std
{
  namespace __debug { }
}

namespace __gnu_cxx
{
  namespace __debug { };
}

namespace __gnu_debug
{
  using namespace std::__debug;
  using namespace __gnu_cxx::__debug;
}

namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _Tp>
    inline void
    swap(_Tp& __a, _Tp& __b)
    {



      _Tp __tmp = __a;
      __a = __b;
      __b = __tmp;
    }




  template<bool _BoolType>
    struct __iter_swap
    {
      template<typename _ForwardIterator1, typename _ForwardIterator2>
        static void
        iter_swap(_ForwardIterator1 __a, _ForwardIterator2 __b)
        {
          typedef typename iterator_traits<_ForwardIterator1>::value_type
            _ValueType1;
          _ValueType1 __tmp = *__a;
          *__a = *__b;
          *__b = __tmp;
 }
    };

  template<>
    struct __iter_swap<true>
    {
      template<typename _ForwardIterator1, typename _ForwardIterator2>
        static void
        iter_swap(_ForwardIterator1 __a, _ForwardIterator2 __b)
        {
          swap(*__a, *__b);
        }
    };
  template<typename _ForwardIterator1, typename _ForwardIterator2>
    inline void
    iter_swap(_ForwardIterator1 __a, _ForwardIterator2 __b)
    {
      typedef typename iterator_traits<_ForwardIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_ForwardIterator2>::value_type
 _ValueType2;
      typedef typename iterator_traits<_ForwardIterator1>::reference
 _ReferenceType1;
      typedef typename iterator_traits<_ForwardIterator2>::reference
 _ReferenceType2;
      std::__iter_swap<__are_same<_ValueType1, _ValueType2>::__value &&
 __are_same<_ValueType1 &, _ReferenceType1>::__value &&
 __are_same<_ValueType2 &, _ReferenceType2>::__value>::
 iter_swap(__a, __b);
    }
  template<typename _Tp>
    inline const _Tp&
    min(const _Tp& __a, const _Tp& __b)
    {



      if (__b < __a)
 return __b;
      return __a;
    }
  template<typename _Tp>
    inline const _Tp&
    max(const _Tp& __a, const _Tp& __b)
    {



      if (__a < __b)
 return __b;
      return __a;
    }
  template<typename _Tp, typename _Compare>
    inline const _Tp&
    min(const _Tp& __a, const _Tp& __b, _Compare __comp)
    {

      if (__comp(__b, __a))
 return __b;
      return __a;
    }
  template<typename _Tp, typename _Compare>
    inline const _Tp&
    max(const _Tp& __a, const _Tp& __b, _Compare __comp)
    {

      if (__comp(__a, __b))
 return __b;
      return __a;
    }







  template<bool, typename>
    struct __copy
    {
      template<typename _II, typename _OI>
        static _OI
        copy(_II __first, _II __last, _OI __result)
        {
   for (; __first != __last; ++__result, ++__first)
     *__result = *__first;
   return __result;
 }
    };

  template<bool _BoolType>
    struct __copy<_BoolType, random_access_iterator_tag>
    {
      template<typename _II, typename _OI>
        static _OI
        copy(_II __first, _II __last, _OI __result)
        {
   typedef typename iterator_traits<_II>::difference_type _Distance;
   for(_Distance __n = __last - __first; __n > 0; --__n)
     {
       *__result = *__first;
       ++__first;
       ++__result;
     }
   return __result;
 }
    };

  template<>
    struct __copy<true, random_access_iterator_tag>
    {
      template<typename _Tp>
        static _Tp*
        copy(const _Tp* __first, const _Tp* __last, _Tp* __result)
        {
   std::memmove(__result, __first, sizeof(_Tp) * (__last - __first));
   return __result + (__last - __first);
 }
    };

  template<typename _II, typename _OI>
    inline _OI
    __copy_aux(_II __first, _II __last, _OI __result)
    {
      typedef typename iterator_traits<_II>::value_type _ValueTypeI;
      typedef typename iterator_traits<_OI>::value_type _ValueTypeO;
      typedef typename iterator_traits<_II>::iterator_category _Category;
      const bool __simple = (__is_scalar<_ValueTypeI>::__value
                      && __is_pointer<_II>::__value
                      && __is_pointer<_OI>::__value
        && __are_same<_ValueTypeI, _ValueTypeO>::__value);

      return std::__copy<__simple, _Category>::copy(__first, __last, __result);
    }


  template<typename _CharT>
  typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
      ostreambuf_iterator<_CharT> >::__type
    __copy_aux(_CharT*, _CharT*, ostreambuf_iterator<_CharT>);

  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
        ostreambuf_iterator<_CharT> >::__type
    __copy_aux(const _CharT*, const _CharT*, ostreambuf_iterator<_CharT>);

  template<typename _CharT>
  typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value, _CharT*>::__type
    __copy_aux(istreambuf_iterator<_CharT>, istreambuf_iterator<_CharT>,
        _CharT*);

  template<bool, bool>
    struct __copy_normal
    {
      template<typename _II, typename _OI>
        static _OI
        __copy_n(_II __first, _II __last, _OI __result)
        { return std::__copy_aux(__first, __last, __result); }
    };

  template<>
    struct __copy_normal<true, false>
    {
      template<typename _II, typename _OI>
        static _OI
        __copy_n(_II __first, _II __last, _OI __result)
        { return std::__copy_aux(__first.base(), __last.base(), __result); }
    };

  template<>
    struct __copy_normal<false, true>
    {
      template<typename _II, typename _OI>
        static _OI
        __copy_n(_II __first, _II __last, _OI __result)
        { return _OI(std::__copy_aux(__first, __last, __result.base())); }
    };

  template<>
    struct __copy_normal<true, true>
    {
      template<typename _II, typename _OI>
        static _OI
        __copy_n(_II __first, _II __last, _OI __result)
        { return _OI(std::__copy_aux(__first.base(), __last.base(),
         __result.base())); }
    };
  template<typename _InputIterator, typename _OutputIterator>
    inline _OutputIterator
    copy(_InputIterator __first, _InputIterator __last,
  _OutputIterator __result)
    {




                                                     ;

       const bool __in = __is_normal_iterator<_InputIterator>::__value;
       const bool __out = __is_normal_iterator<_OutputIterator>::__value;
       return std::__copy_normal<__in, __out>::__copy_n(__first, __last,
       __result);
    }


  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
                 ostreambuf_iterator<_CharT> >::__type
    copy(istreambuf_iterator<_CharT>, istreambuf_iterator<_CharT>,
  ostreambuf_iterator<_CharT>);

  template<bool, typename>
    struct __copy_backward
    {
      template<typename _BI1, typename _BI2>
        static _BI2
        __copy_b(_BI1 __first, _BI1 __last, _BI2 __result)
        {
   while (__first != __last)
     *--__result = *--__last;
   return __result;
 }
    };

  template<bool _BoolType>
    struct __copy_backward<_BoolType, random_access_iterator_tag>
    {
      template<typename _BI1, typename _BI2>
        static _BI2
        __copy_b(_BI1 __first, _BI1 __last, _BI2 __result)
        {
   typename iterator_traits<_BI1>::difference_type __n;
   for (__n = __last - __first; __n > 0; --__n)
     *--__result = *--__last;
   return __result;
 }
    };

  template<>
    struct __copy_backward<true, random_access_iterator_tag>
    {
      template<typename _Tp>
        static _Tp*
        __copy_b(const _Tp* __first, const _Tp* __last, _Tp* __result)
        {
   const ptrdiff_t _Num = __last - __first;
   std::memmove(__result - _Num, __first, sizeof(_Tp) * _Num);
   return __result - _Num;
 }
    };

  template<typename _BI1, typename _BI2>
    inline _BI2
    __copy_backward_aux(_BI1 __first, _BI1 __last, _BI2 __result)
    {
      typedef typename iterator_traits<_BI1>::value_type _ValueType1;
      typedef typename iterator_traits<_BI2>::value_type _ValueType2;
      typedef typename iterator_traits<_BI1>::iterator_category _Category;
      const bool __simple = (__is_scalar<_ValueType1>::__value
                      && __is_pointer<_BI1>::__value
                      && __is_pointer<_BI2>::__value
        && __are_same<_ValueType1, _ValueType2>::__value);

      return std::__copy_backward<__simple, _Category>::__copy_b(__first,
         __last,
         __result);
    }

  template<bool, bool>
    struct __copy_backward_normal
    {
      template<typename _BI1, typename _BI2>
        static _BI2
        __copy_b_n(_BI1 __first, _BI1 __last, _BI2 __result)
        { return std::__copy_backward_aux(__first, __last, __result); }
    };

  template<>
    struct __copy_backward_normal<true, false>
    {
      template<typename _BI1, typename _BI2>
        static _BI2
        __copy_b_n(_BI1 __first, _BI1 __last, _BI2 __result)
        { return std::__copy_backward_aux(__first.base(), __last.base(),
       __result); }
    };

  template<>
    struct __copy_backward_normal<false, true>
    {
      template<typename _BI1, typename _BI2>
        static _BI2
        __copy_b_n(_BI1 __first, _BI1 __last, _BI2 __result)
        { return _BI2(std::__copy_backward_aux(__first, __last,
            __result.base())); }
    };

  template<>
    struct __copy_backward_normal<true, true>
    {
      template<typename _BI1, typename _BI2>
        static _BI2
        __copy_b_n(_BI1 __first, _BI1 __last, _BI2 __result)
        { return _BI2(std::__copy_backward_aux(__first.base(), __last.base(),
            __result.base())); }
    };
  template <typename _BI1, typename _BI2>
    inline _BI2
    copy_backward(_BI1 __first, _BI1 __last, _BI2 __result)
    {






                                                     ;

      const bool __bi1 = __is_normal_iterator<_BI1>::__value;
      const bool __bi2 = __is_normal_iterator<_BI2>::__value;
      return std::__copy_backward_normal<__bi1, __bi2>::__copy_b_n(__first,
           __last,
           __result);
    }

  template<bool>
    struct __fill
    {
      template<typename _ForwardIterator, typename _Tp>
        static void
        fill(_ForwardIterator __first, _ForwardIterator __last,
      const _Tp& __value)
        {
   for (; __first != __last; ++__first)
     *__first = __value;
 }
    };

  template<>
    struct __fill<true>
    {
      template<typename _ForwardIterator, typename _Tp>
        static void
        fill(_ForwardIterator __first, _ForwardIterator __last,
      const _Tp& __value)
        {
   const _Tp __tmp = __value;
   for (; __first != __last; ++__first)
     *__first = __tmp;
 }
    };
  template<typename _ForwardIterator, typename _Tp>
    void
    fill(_ForwardIterator __first, _ForwardIterator __last, const _Tp& __value)
    {



                                                     ;

      const bool __scalar = __is_scalar<_Tp>::__value;
      std::__fill<__scalar>::fill(__first, __last, __value);
    }


  inline void
  fill(unsigned char* __first, unsigned char* __last, const unsigned char& __c)
  {
                                                   ;
    const unsigned char __tmp = __c;
    std::memset(__first, __tmp, __last - __first);
  }

  inline void
  fill(signed char* __first, signed char* __last, const signed char& __c)
  {
                                                   ;
    const signed char __tmp = __c;
    std::memset(__first, static_cast<unsigned char>(__tmp), __last - __first);
  }

  inline void
  fill(char* __first, char* __last, const char& __c)
  {
                                                   ;
    const char __tmp = __c;
    std::memset(__first, static_cast<unsigned char>(__tmp), __last - __first);
  }

  template<bool>
    struct __fill_n
    {
      template<typename _OutputIterator, typename _Size, typename _Tp>
        static _OutputIterator
        fill_n(_OutputIterator __first, _Size __n, const _Tp& __value)
        {
   for (; __n > 0; --__n, ++__first)
     *__first = __value;
   return __first;
 }
    };

  template<>
    struct __fill_n<true>
    {
      template<typename _OutputIterator, typename _Size, typename _Tp>
        static _OutputIterator
        fill_n(_OutputIterator __first, _Size __n, const _Tp& __value)
        {
   const _Tp __tmp = __value;
   for (; __n > 0; --__n, ++__first)
     *__first = __tmp;
   return __first;
 }
    };
  template<typename _OutputIterator, typename _Size, typename _Tp>
    _OutputIterator
    fill_n(_OutputIterator __first, _Size __n, const _Tp& __value)
    {



      const bool __scalar = __is_scalar<_Tp>::__value;
      return std::__fill_n<__scalar>::fill_n(__first, __n, __value);
    }

  template<typename _Size>
    inline unsigned char*
    fill_n(unsigned char* __first, _Size __n, const unsigned char& __c)
    {
      std::fill(__first, __first + __n, __c);
      return __first + __n;
    }

  template<typename _Size>
    inline signed char*
    fill_n(signed char* __first, _Size __n, const signed char& __c)
    {
      std::fill(__first, __first + __n, __c);
      return __first + __n;
    }

  template<typename _Size>
    inline char*
    fill_n(char* __first, _Size __n, const char& __c)
    {
      std::fill(__first, __first + __n, __c);
      return __first + __n;
    }
  template<typename _InputIterator1, typename _InputIterator2>
    pair<_InputIterator1, _InputIterator2>
    mismatch(_InputIterator1 __first1, _InputIterator1 __last1,
      _InputIterator2 __first2)
    {






                                                       ;

      while (__first1 != __last1 && *__first1 == *__first2)
        {
   ++__first1;
   ++__first2;
        }
      return pair<_InputIterator1, _InputIterator2>(__first1, __first2);
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _BinaryPredicate>
    pair<_InputIterator1, _InputIterator2>
    mismatch(_InputIterator1 __first1, _InputIterator1 __last1,
      _InputIterator2 __first2, _BinaryPredicate __binary_pred)
    {



                                                       ;

      while (__first1 != __last1 && __binary_pred(*__first1, *__first2))
        {
   ++__first1;
   ++__first2;
        }
      return pair<_InputIterator1, _InputIterator2>(__first1, __first2);
    }
  template<typename _InputIterator1, typename _InputIterator2>
    inline bool
    equal(_InputIterator1 __first1, _InputIterator1 __last1,
   _InputIterator2 __first2)
    {






                                                       ;

      for (; __first1 != __last1; ++__first1, ++__first2)
 if (!(*__first1 == *__first2))
   return false;
      return true;
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _BinaryPredicate>
    inline bool
    equal(_InputIterator1 __first1, _InputIterator1 __last1,
   _InputIterator2 __first2,
   _BinaryPredicate __binary_pred)
    {



                                                       ;

      for (; __first1 != __last1; ++__first1, ++__first2)
 if (!__binary_pred(*__first1, *__first2))
   return false;
      return true;
    }
  template<typename _InputIterator1, typename _InputIterator2>
    bool
    lexicographical_compare(_InputIterator1 __first1, _InputIterator1 __last1,
       _InputIterator2 __first2, _InputIterator2 __last2)
    {
                                                       ;
                                                       ;

      for (; __first1 != __last1 && __first2 != __last2;
    ++__first1, ++__first2)
 {
   if (*__first1 < *__first2)
     return true;
   if (*__first2 < *__first1)
     return false;
 }
      return __first1 == __last1 && __first2 != __last2;
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _Compare>
    bool
    lexicographical_compare(_InputIterator1 __first1, _InputIterator1 __last1,
       _InputIterator2 __first2, _InputIterator2 __last2,
       _Compare __comp)
    {



                                                       ;
                                                       ;

      for (; __first1 != __last1 && __first2 != __last2;
    ++__first1, ++__first2)
 {
   if (__comp(*__first1, *__first2))
     return true;
   if (__comp(*__first2, *__first1))
     return false;
 }
      return __first1 == __last1 && __first2 != __last2;
    }

  inline bool
  lexicographical_compare(const unsigned char* __first1,
     const unsigned char* __last1,
     const unsigned char* __first2,
     const unsigned char* __last2)
  {
                                                     ;
                                                     ;

    const size_t __len1 = __last1 - __first1;
    const size_t __len2 = __last2 - __first2;
    const int __result = std::memcmp(__first1, __first2,
         std::min(__len1, __len2));
    return __result != 0 ? __result < 0 : __len1 < __len2;
  }

  inline bool
  lexicographical_compare(const char* __first1, const char* __last1,
     const char* __first2, const char* __last2)
  {
                                                     ;
                                                     ;


    return std::lexicographical_compare((const signed char*) __first1,
     (const signed char*) __last1,
     (const signed char*) __first2,
     (const signed char*) __last2);






  }

}


namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {
  template <class _CharT>
    struct _Char_types
    {
      typedef unsigned long int_type;
      typedef std::streampos pos_type;
      typedef std::streamoff off_type;
      typedef std::mbstate_t state_type;
    };
  template<typename _CharT>
    struct char_traits
    {
      typedef _CharT char_type;
      typedef typename _Char_types<_CharT>::int_type int_type;
      typedef typename _Char_types<_CharT>::pos_type pos_type;
      typedef typename _Char_types<_CharT>::off_type off_type;
      typedef typename _Char_types<_CharT>::state_type state_type;

      static void
      assign(char_type& __c1, const char_type& __c2)
      { __c1 = __c2; }

      static bool
      eq(const char_type& __c1, const char_type& __c2)
      { return __c1 == __c2; }

      static bool
      lt(const char_type& __c1, const char_type& __c2)
      { return __c1 < __c2; }

      static int
      compare(const char_type* __s1, const char_type* __s2, std::size_t __n);

      static std::size_t
      length(const char_type* __s);

      static const char_type*
      find(const char_type* __s, std::size_t __n, const char_type& __a);

      static char_type*
      move(char_type* __s1, const char_type* __s2, std::size_t __n);

      static char_type*
      copy(char_type* __s1, const char_type* __s2, std::size_t __n);

      static char_type*
      assign(char_type* __s, std::size_t __n, char_type __a);

      static char_type
      to_char_type(const int_type& __c)
      { return static_cast<char_type>(__c); }

      static int_type
      to_int_type(const char_type& __c)
      { return static_cast<int_type>(__c); }

      static bool
      eq_int_type(const int_type& __c1, const int_type& __c2)
      { return __c1 == __c2; }

      static int_type
      eof()
      { return static_cast<int_type>((-1)); }

      static int_type
      not_eof(const int_type& __c)
      { return !eq_int_type(__c, eof()) ? __c : to_int_type(char_type()); }
    };

  template<typename _CharT>
    int
    char_traits<_CharT>::
    compare(const char_type* __s1, const char_type* __s2, std::size_t __n)
    {
      for (std::size_t __i = 0; __i < __n; ++__i)
 if (lt(__s1[__i], __s2[__i]))
   return -1;
 else if (lt(__s2[__i], __s1[__i]))
   return 1;
      return 0;
    }

  template<typename _CharT>
    std::size_t
    char_traits<_CharT>::
    length(const char_type* __p)
    {
      std::size_t __i = 0;
      while (!eq(__p[__i], char_type()))
        ++__i;
      return __i;
    }

  template<typename _CharT>
    const typename char_traits<_CharT>::char_type*
    char_traits<_CharT>::
    find(const char_type* __s, std::size_t __n, const char_type& __a)
    {
      for (std::size_t __i = 0; __i < __n; ++__i)
        if (eq(__s[__i], __a))
          return __s + __i;
      return 0;
    }

  template<typename _CharT>
    typename char_traits<_CharT>::char_type*
    char_traits<_CharT>::
    move(char_type* __s1, const char_type* __s2, std::size_t __n)
    {
      return static_cast<_CharT*>(std::memmove(__s1, __s2,
            __n * sizeof(char_type)));
    }

  template<typename _CharT>
    typename char_traits<_CharT>::char_type*
    char_traits<_CharT>::
    copy(char_type* __s1, const char_type* __s2, std::size_t __n)
    {
      std::copy(__s2, __s2 + __n, __s1);
      return __s1;
    }

  template<typename _CharT>
    typename char_traits<_CharT>::char_type*
    char_traits<_CharT>::
    assign(char_type* __s, std::size_t __n, char_type __a)
    {
      std::fill_n(__s, __n, __a);
      return __s;
    }

}

namespace std __attribute__ ((__visibility__ ("default"))) {
  template<class _CharT>
    struct char_traits : public __gnu_cxx::char_traits<_CharT>
    { };



  template<>
    struct char_traits<char>
    {
      typedef char char_type;
      typedef int int_type;
      typedef streampos pos_type;
      typedef streamoff off_type;
      typedef mbstate_t state_type;

      static void
      assign(char_type& __c1, const char_type& __c2)
      { __c1 = __c2; }

      static bool
      eq(const char_type& __c1, const char_type& __c2)
      { return __c1 == __c2; }

      static bool
      lt(const char_type& __c1, const char_type& __c2)
      { return __c1 < __c2; }

      static int
      compare(const char_type* __s1, const char_type* __s2, size_t __n)
      { return memcmp(__s1, __s2, __n); }

      static size_t
      length(const char_type* __s)
      { return strlen(__s); }

      static const char_type*
      find(const char_type* __s, size_t __n, const char_type& __a)
      { return static_cast<const char_type*>(memchr(__s, __a, __n)); }

      static char_type*
      move(char_type* __s1, const char_type* __s2, size_t __n)
      { return static_cast<char_type*>(memmove(__s1, __s2, __n)); }

      static char_type*
      copy(char_type* __s1, const char_type* __s2, size_t __n)
      { return static_cast<char_type*>(memcpy(__s1, __s2, __n)); }

      static char_type*
      assign(char_type* __s, size_t __n, char_type __a)
      { return static_cast<char_type*>(memset(__s, __a, __n)); }

      static char_type
      to_char_type(const int_type& __c)
      { return static_cast<char_type>(__c); }



      static int_type
      to_int_type(const char_type& __c)
      { return static_cast<int_type>(static_cast<unsigned char>(__c)); }

      static bool
      eq_int_type(const int_type& __c1, const int_type& __c2)
      { return __c1 == __c2; }

      static int_type
      eof() { return static_cast<int_type>((-1)); }

      static int_type
      not_eof(const int_type& __c)
      { return (__c == eof()) ? 0 : __c; }
  };




  template<>
    struct char_traits<wchar_t>
    {
      typedef wchar_t char_type;
      typedef wint_t int_type;
      typedef streamoff off_type;
      typedef wstreampos pos_type;
      typedef mbstate_t state_type;

      static void
      assign(char_type& __c1, const char_type& __c2)
      { __c1 = __c2; }

      static bool
      eq(const char_type& __c1, const char_type& __c2)
      { return __c1 == __c2; }

      static bool
      lt(const char_type& __c1, const char_type& __c2)
      { return __c1 < __c2; }

      static int
      compare(const char_type* __s1, const char_type* __s2, size_t __n)
      { return wmemcmp(__s1, __s2, __n); }

      static size_t
      length(const char_type* __s)
      { return wcslen(__s); }

      static const char_type*
      find(const char_type* __s, size_t __n, const char_type& __a)
      { return wmemchr(__s, __a, __n); }

      static char_type*
      move(char_type* __s1, const char_type* __s2, size_t __n)
      { return wmemmove(__s1, __s2, __n); }

      static char_type*
      copy(char_type* __s1, const char_type* __s2, size_t __n)
      { return wmemcpy(__s1, __s2, __n); }

      static char_type*
      assign(char_type* __s, size_t __n, char_type __a)
      { return wmemset(__s, __a, __n); }

      static char_type
      to_char_type(const int_type& __c) { return char_type(__c); }

      static int_type
      to_int_type(const char_type& __c) { return int_type(__c); }

      static bool
      eq_int_type(const int_type& __c1, const int_type& __c2)
      { return __c1 == __c2; }

      static int_type
      eof() { return static_cast<int_type>(((wint_t)-1)); }

      static int_type
      not_eof(const int_type& __c)
      { return eq_int_type(__c, eof()) ? 0 : __c; }
  };


}





extern "C++" {

namespace std
{
  class exception
  {
  public:
    exception() throw() { }
    virtual ~exception() throw();



    virtual const char* what() const throw();
  };



  class bad_exception : public exception
  {
  public:
    bad_exception() throw() { }



    virtual ~bad_exception() throw();


    virtual const char* what() const throw();
  };


  typedef void (*terminate_handler) ();


  typedef void (*unexpected_handler) ();


  terminate_handler set_terminate(terminate_handler) throw();



  void terminate() __attribute__ ((__noreturn__));


  unexpected_handler set_unexpected(unexpected_handler) throw();



  void unexpected() __attribute__ ((__noreturn__));
  bool uncaught_exception() throw();
}

namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {
  void __verbose_terminate_handler ();

}

}



extern "C++" {

namespace std
{





  class bad_alloc : public exception
  {
  public:
    bad_alloc() throw() { }



    virtual ~bad_alloc() throw();


    virtual const char* what() const throw();
  };

  struct nothrow_t { };

  extern const nothrow_t nothrow;



  typedef void (*new_handler)();



  new_handler set_new_handler(new_handler) throw();
}
void* operator new(std::size_t) throw (std::bad_alloc);
void* operator new[](std::size_t) throw (std::bad_alloc);
void operator delete(void*) throw();
void operator delete[](void*) throw();
void* operator new(std::size_t, const std::nothrow_t&) throw();
void* operator new[](std::size_t, const std::nothrow_t&) throw();
void operator delete(void*, const std::nothrow_t&) throw();
void operator delete[](void*, const std::nothrow_t&) throw();


inline void* operator new(std::size_t, void* __p) throw() { return __p; }
inline void* operator new[](std::size_t, void* __p) throw() { return __p; }


inline void operator delete (void*, void*) throw() { }
inline void operator delete[](void*, void*) throw() { }

}



namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {

  using std::size_t;
  using std::ptrdiff_t;
  template<typename _Tp>
    class new_allocator
    {
    public:
      typedef size_t size_type;
      typedef ptrdiff_t difference_type;
      typedef _Tp* pointer;
      typedef const _Tp* const_pointer;
      typedef _Tp& reference;
      typedef const _Tp& const_reference;
      typedef _Tp value_type;

      template<typename _Tp1>
        struct rebind
        { typedef new_allocator<_Tp1> other; };

      new_allocator() throw() { }

      new_allocator(const new_allocator&) throw() { }

      template<typename _Tp1>
        new_allocator(const new_allocator<_Tp1>&) throw() { }

      ~new_allocator() throw() { }

      pointer
      address(reference __x) const { return &__x; }

      const_pointer
      address(const_reference __x) const { return &__x; }



      pointer
      allocate(size_type __n, const void* = 0)
      {
 if (__builtin_expect(__n > this->max_size(), false))
   std::__throw_bad_alloc();

 return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));
      }


      void
      deallocate(pointer __p, size_type)
      { ::operator delete(__p); }

      size_type
      max_size() const throw()
      { return size_t(-1) / sizeof(_Tp); }



      void
      construct(pointer __p, const _Tp& __val)
      { ::new(__p) _Tp(__val); }

      void
      destroy(pointer __p) { __p->~_Tp(); }
    };

  template<typename _Tp>
    inline bool
    operator==(const new_allocator<_Tp>&, const new_allocator<_Tp>&)
    { return true; }

  template<typename _Tp>
    inline bool
    operator!=(const new_allocator<_Tp>&, const new_allocator<_Tp>&)
    { return false; }

}



namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _Tp>
    class allocator;


  template<>
    class allocator<void>
    {
    public:
      typedef size_t size_type;
      typedef ptrdiff_t difference_type;
      typedef void* pointer;
      typedef const void* const_pointer;
      typedef void value_type;

      template<typename _Tp1>
        struct rebind
        { typedef allocator<_Tp1> other; };
    };







  template<typename _Tp>
    class allocator: public __gnu_cxx::new_allocator<_Tp>
    {
   public:
      typedef size_t size_type;
      typedef ptrdiff_t difference_type;
      typedef _Tp* pointer;
      typedef const _Tp* const_pointer;
      typedef _Tp& reference;
      typedef const _Tp& const_reference;
      typedef _Tp value_type;

      template<typename _Tp1>
        struct rebind
        { typedef allocator<_Tp1> other; };

      allocator() throw() { }

      allocator(const allocator& __a) throw()
      : __gnu_cxx::new_allocator<_Tp>(__a) { }

      template<typename _Tp1>
        allocator(const allocator<_Tp1>&) throw() { }

      ~allocator() throw() { }


    };

  template<typename _T1, typename _T2>
    inline bool
    operator==(const allocator<_T1>&, const allocator<_T2>&)
    { return true; }

  template<typename _Tp>
    inline bool
    operator==(const allocator<_Tp>&, const allocator<_Tp>&)
    { return true; }

  template<typename _T1, typename _T2>
    inline bool
    operator!=(const allocator<_T1>&, const allocator<_T2>&)
    { return false; }

  template<typename _Tp>
    inline bool
    operator!=(const allocator<_Tp>&, const allocator<_Tp>&)
    { return false; }





  extern template class allocator<char>;
  extern template class allocator<wchar_t>;






  template<typename _Alloc, bool = std::__is_empty<_Alloc>::__value>
    struct __alloc_swap
    { static void _S_do_it(_Alloc&, _Alloc&) { } };

  template<typename _Alloc>
    struct __alloc_swap<_Alloc, false>
    {
      static void
      _S_do_it(_Alloc& __one, _Alloc& __two)
      {

 if (__one != __two)
   swap(__one, __two);
      }
    };

}
namespace std __attribute__ ((__visibility__ ("default"))) {







  template<typename _T1, typename _T2>
    inline void
    _Construct(_T1* __p, const _T2& __value)
    {


      ::new(static_cast<void*>(__p)) _T1(__value);
    }







  template<typename _T1>
    inline void
    _Construct(_T1* __p)
    {


      ::new(static_cast<void*>(__p)) _T1();
    }






  template<typename _Tp>
    inline void
    _Destroy(_Tp* __pointer)
    { __pointer->~_Tp(); }
  template<typename _ForwardIterator>
    inline void
    __destroy_aux(_ForwardIterator __first, _ForwardIterator __last,
    __false_type)
    {
      for (; __first != __last; ++__first)
 std::_Destroy(&*__first);
    }
  template<typename _ForwardIterator>
    inline void
    __destroy_aux(_ForwardIterator, _ForwardIterator, __true_type)
    { }
  template<typename _ForwardIterator>
    inline void
    _Destroy(_ForwardIterator __first, _ForwardIterator __last)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
                       _Value_type;
      typedef typename std::__is_scalar<_Value_type>::__type
                _Has_trivial_destructor;

      std::__destroy_aux(__first, __last, _Has_trivial_destructor());
    }
  template <typename _Tp> class allocator;

  template<typename _ForwardIterator, typename _Allocator>
    void
    _Destroy(_ForwardIterator __first, _ForwardIterator __last,
      _Allocator __alloc)
    {
      for (; __first != __last; ++__first)
 __alloc.destroy(&*__first);
    }

  template<typename _ForwardIterator, typename _Tp>
    inline void
    _Destroy(_ForwardIterator __first, _ForwardIterator __last,
      allocator<_Tp>)
    {
      _Destroy(__first, __last);
    }

}

namespace std __attribute__ ((__visibility__ ("default"))) {


  template<typename _InputIterator, typename _ForwardIterator>
    inline _ForwardIterator
    __uninitialized_copy_aux(_InputIterator __first, _InputIterator __last,
        _ForwardIterator __result,
        __true_type)
    { return std::copy(__first, __last, __result); }

  template<typename _InputIterator, typename _ForwardIterator>
    inline _ForwardIterator
    __uninitialized_copy_aux(_InputIterator __first, _InputIterator __last,
        _ForwardIterator __result,
        __false_type)
    {
      _ForwardIterator __cur = __result;
      if (true)
 {
   for (; __first != __last; ++__first, ++__cur)
     std::_Construct(&*__cur, *__first);
   return __cur;
 }
      if (false)
 {
   std::_Destroy(__result, __cur);
                          ;
 }
    }
  template<typename _InputIterator, typename _ForwardIterator>
    inline _ForwardIterator
    uninitialized_copy(_InputIterator __first, _InputIterator __last,
         _ForwardIterator __result)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type _ValueType;
      typedef typename std::__is_scalar<_ValueType>::__type _Is_POD;
      return std::__uninitialized_copy_aux(__first, __last, __result,
        _Is_POD());
    }

  inline char*
  uninitialized_copy(const char* __first, const char* __last, char* __result)
  {
    std::memmove(__result, __first, __last - __first);
    return __result + (__last - __first);
  }

  inline wchar_t*
  uninitialized_copy(const wchar_t* __first, const wchar_t* __last,
       wchar_t* __result)
  {
    std::memmove(__result, __first, sizeof(wchar_t) * (__last - __first));
    return __result + (__last - __first);
  }



  template<typename _ForwardIterator, typename _Tp>
    inline void
    __uninitialized_fill_aux(_ForwardIterator __first,
        _ForwardIterator __last,
        const _Tp& __x, __true_type)
    { std::fill(__first, __last, __x); }

  template<typename _ForwardIterator, typename _Tp>
    void
    __uninitialized_fill_aux(_ForwardIterator __first, _ForwardIterator __last,
        const _Tp& __x, __false_type)
    {
      _ForwardIterator __cur = __first;
      if (true)
 {
   for (; __cur != __last; ++__cur)
     std::_Construct(&*__cur, __x);
 }
      if (false)
 {
   std::_Destroy(__first, __cur);
                          ;
 }
    }
  template<typename _ForwardIterator, typename _Tp>
    inline void
    uninitialized_fill(_ForwardIterator __first, _ForwardIterator __last,
         const _Tp& __x)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type _ValueType;
      typedef typename std::__is_scalar<_ValueType>::__type _Is_POD;
      std::__uninitialized_fill_aux(__first, __last, __x, _Is_POD());
    }



  template<typename _ForwardIterator, typename _Size, typename _Tp>
    inline void
    __uninitialized_fill_n_aux(_ForwardIterator __first, _Size __n,
          const _Tp& __x, __true_type)
    { std::fill_n(__first, __n, __x); }

  template<typename _ForwardIterator, typename _Size, typename _Tp>
    void
    __uninitialized_fill_n_aux(_ForwardIterator __first, _Size __n,
          const _Tp& __x, __false_type)
    {
      _ForwardIterator __cur = __first;
      if (true)
 {
   for (; __n > 0; --__n, ++__cur)
     std::_Construct(&*__cur, __x);
 }
      if (false)
 {
   std::_Destroy(__first, __cur);
                          ;
 }
    }
  template<typename _ForwardIterator, typename _Size, typename _Tp>
    inline void
    uninitialized_fill_n(_ForwardIterator __first, _Size __n, const _Tp& __x)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type _ValueType;
      typedef typename std::__is_scalar<_ValueType>::__type _Is_POD;
      std::__uninitialized_fill_n_aux(__first, __n, __x, _Is_POD());
    }







  template<typename _InputIterator, typename _ForwardIterator,
    typename _Allocator>
    _ForwardIterator
    __uninitialized_copy_a(_InputIterator __first, _InputIterator __last,
      _ForwardIterator __result,
      _Allocator __alloc)
    {
      _ForwardIterator __cur = __result;
      if (true)
 {
   for (; __first != __last; ++__first, ++__cur)
     __alloc.construct(&*__cur, *__first);
   return __cur;
 }
      if (false)
 {
   std::_Destroy(__result, __cur, __alloc);
                          ;
 }
    }

  template<typename _InputIterator, typename _ForwardIterator, typename _Tp>
    inline _ForwardIterator
    __uninitialized_copy_a(_InputIterator __first, _InputIterator __last,
      _ForwardIterator __result,
      allocator<_Tp>)
    { return std::uninitialized_copy(__first, __last, __result); }

  template<typename _ForwardIterator, typename _Tp, typename _Allocator>
    void
    __uninitialized_fill_a(_ForwardIterator __first, _ForwardIterator __last,
      const _Tp& __x, _Allocator __alloc)
    {
      _ForwardIterator __cur = __first;
      if (true)
 {
   for (; __cur != __last; ++__cur)
     __alloc.construct(&*__cur, __x);
 }
      if (false)
 {
   std::_Destroy(__first, __cur, __alloc);
                          ;
 }
    }

  template<typename _ForwardIterator, typename _Tp, typename _Tp2>
    inline void
    __uninitialized_fill_a(_ForwardIterator __first, _ForwardIterator __last,
      const _Tp& __x, allocator<_Tp2>)
    { std::uninitialized_fill(__first, __last, __x); }

  template<typename _ForwardIterator, typename _Size, typename _Tp,
    typename _Allocator>
    void
    __uninitialized_fill_n_a(_ForwardIterator __first, _Size __n,
        const _Tp& __x,
        _Allocator __alloc)
    {
      _ForwardIterator __cur = __first;
      if (true)
 {
   for (; __n > 0; --__n, ++__cur)
     __alloc.construct(&*__cur, __x);
 }
      if (false)
 {
   std::_Destroy(__first, __cur, __alloc);
                          ;
 }
    }

  template<typename _ForwardIterator, typename _Size, typename _Tp,
    typename _Tp2>
    inline void
    __uninitialized_fill_n_a(_ForwardIterator __first, _Size __n,
        const _Tp& __x,
        allocator<_Tp2>)
    { std::uninitialized_fill_n(__first, __n, __x); }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _ForwardIterator, typename _Allocator>
    inline _ForwardIterator
    __uninitialized_copy_copy(_InputIterator1 __first1,
         _InputIterator1 __last1,
         _InputIterator2 __first2,
         _InputIterator2 __last2,
         _ForwardIterator __result,
         _Allocator __alloc)
    {
      _ForwardIterator __mid = std::__uninitialized_copy_a(__first1, __last1,
          __result,
          __alloc);
      if (true)
 {
   return std::__uninitialized_copy_a(__first2, __last2, __mid, __alloc);
 }
      if (false)
 {
   std::_Destroy(__result, __mid, __alloc);
                          ;
 }
    }




  template<typename _ForwardIterator, typename _Tp, typename _InputIterator,
    typename _Allocator>
    inline _ForwardIterator
    __uninitialized_fill_copy(_ForwardIterator __result, _ForwardIterator __mid,
         const _Tp& __x, _InputIterator __first,
         _InputIterator __last,
         _Allocator __alloc)
    {
      std::__uninitialized_fill_a(__result, __mid, __x, __alloc);
      if (true)
 {
   return std::__uninitialized_copy_a(__first, __last, __mid, __alloc);
 }
      if (false)
 {
   std::_Destroy(__result, __mid, __alloc);
                          ;
 }
    }




  template<typename _InputIterator, typename _ForwardIterator, typename _Tp,
    typename _Allocator>
    inline void
    __uninitialized_copy_fill(_InputIterator __first1, _InputIterator __last1,
         _ForwardIterator __first2,
         _ForwardIterator __last2, const _Tp& __x,
         _Allocator __alloc)
    {
      _ForwardIterator __mid2 = std::__uninitialized_copy_a(__first1, __last1,
           __first2,
           __alloc);
      if (true)
 {
   std::__uninitialized_fill_a(__mid2, __last2, __x, __alloc);
 }
      if (false)
 {
   std::_Destroy(__first2, __mid2, __alloc);
                          ;
 }
    }

}
namespace std __attribute__ ((__visibility__ ("default"))) {





  template <class _ForwardIterator, class _Tp>
    class raw_storage_iterator
    : public iterator<output_iterator_tag, void, void, void, void>
    {
    protected:
      _ForwardIterator _M_iter;

    public:
      explicit
      raw_storage_iterator(_ForwardIterator __x)
      : _M_iter(__x) {}

      raw_storage_iterator&
      operator*() { return *this; }

      raw_storage_iterator&
      operator=(const _Tp& __element)
      {
 std::_Construct(&*_M_iter, __element);
 return *this;
      }

      raw_storage_iterator<_ForwardIterator, _Tp>&
      operator++()
      {
 ++_M_iter;
 return *this;
      }

      raw_storage_iterator<_ForwardIterator, _Tp>
      operator++(int)
      {
 raw_storage_iterator<_ForwardIterator, _Tp> __tmp = *this;
 ++_M_iter;
 return __tmp;
      }
    };

}

namespace std __attribute__ ((__visibility__ ("default"))) {






  enum float_round_style
  {
    round_indeterminate = -1,
    round_toward_zero = 0,
    round_to_nearest = 1,
    round_toward_infinity = 2,
    round_toward_neg_infinity = 3
  };







  enum float_denorm_style
  {

    denorm_indeterminate = -1,

    denorm_absent = 0,

    denorm_present = 1
  };
  struct __numeric_limits_base
  {


    static const bool is_specialized = false;




    static const int digits = 0;

    static const int digits10 = 0;

    static const bool is_signed = false;





    static const bool is_integer = false;




    static const bool is_exact = false;


    static const int radix = 0;



    static const int min_exponent = 0;


    static const int min_exponent10 = 0;



    static const int max_exponent = 0;


    static const int max_exponent10 = 0;


    static const bool has_infinity = false;


    static const bool has_quiet_NaN = false;


    static const bool has_signaling_NaN = false;

    static const float_denorm_style has_denorm = denorm_absent;


    static const bool has_denorm_loss = false;



    static const bool is_iec559 = false;



    static const bool is_bounded = false;




    static const bool is_modulo = false;


    static const bool traps = false;

    static const bool tinyness_before = false;



    static const float_round_style round_style = round_toward_zero;
  };
  template<typename _Tp>
    struct numeric_limits : public __numeric_limits_base
    {


      static _Tp min() throw() { return static_cast<_Tp>(0); }

      static _Tp max() throw() { return static_cast<_Tp>(0); }


      static _Tp epsilon() throw() { return static_cast<_Tp>(0); }

      static _Tp round_error() throw() { return static_cast<_Tp>(0); }

      static _Tp infinity() throw() { return static_cast<_Tp>(0); }

      static _Tp quiet_NaN() throw() { return static_cast<_Tp>(0); }


      static _Tp signaling_NaN() throw() { return static_cast<_Tp>(0); }



      static _Tp denorm_min() throw() { return static_cast<_Tp>(0); }
    };





  template<>
    struct numeric_limits<bool>
    {
      static const bool is_specialized = true;

      static bool min() throw()
      { return false; }
      static bool max() throw()
      { return true; }

      static const int digits = 1;
      static const int digits10 = 0;
      static const bool is_signed = false;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static bool epsilon() throw()
      { return false; }
      static bool round_error() throw()
      { return false; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static bool infinity() throw()
      { return false; }
      static bool quiet_NaN() throw()
      { return false; }
      static bool signaling_NaN() throw()
      { return false; }
      static bool denorm_min() throw()
      { return false; }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = false;




      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<char>
    {
      static const bool is_specialized = true;

      static char min() throw()
      { return (((char)(-1) < 0) ? (char)1 << (sizeof(char) * 8 - ((char)(-1) < 0)) : (char)0); }
      static char max() throw()
      { return (((char)(-1) < 0) ? ((char)1 << (sizeof(char) * 8 - ((char)(-1) < 0))) - 1 : ~(char)0); }

      static const int digits = (sizeof(char) * 8 - ((char)(-1) < 0));
      static const int digits10 = ((sizeof(char) * 8 - ((char)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = ((char)(-1) < 0);
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static char epsilon() throw()
      { return 0; }
      static char round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static char infinity() throw()
      { return char(); }
      static char quiet_NaN() throw()
      { return char(); }
      static char signaling_NaN() throw()
      { return char(); }
      static char denorm_min() throw()
      { return static_cast<char>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<signed char>
    {
      static const bool is_specialized = true;

      static signed char min() throw()
      { return -127 - 1; }
      static signed char max() throw()
      { return 127; }

      static const int digits = (sizeof(signed char) * 8 - ((signed char)(-1) < 0));
      static const int digits10 = ((sizeof(signed char) * 8 - ((signed char)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = true;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static signed char epsilon() throw()
      { return 0; }
      static signed char round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static signed char infinity() throw()
      { return static_cast<signed char>(0); }
      static signed char quiet_NaN() throw()
      { return static_cast<signed char>(0); }
      static signed char signaling_NaN() throw()
      { return static_cast<signed char>(0); }
      static signed char denorm_min() throw()
      { return static_cast<signed char>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<unsigned char>
    {
      static const bool is_specialized = true;

      static unsigned char min() throw()
      { return 0; }
      static unsigned char max() throw()
      { return 127 * 2U + 1; }

      static const int digits = (sizeof(unsigned char) * 8 - ((unsigned char)(-1) < 0));
      static const int digits10 = ((sizeof(unsigned char) * 8 - ((unsigned char)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = false;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static unsigned char epsilon() throw()
      { return 0; }
      static unsigned char round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static unsigned char infinity() throw()
      { return static_cast<unsigned char>(0); }
      static unsigned char quiet_NaN() throw()
      { return static_cast<unsigned char>(0); }
      static unsigned char signaling_NaN() throw()
      { return static_cast<unsigned char>(0); }
      static unsigned char denorm_min() throw()
      { return static_cast<unsigned char>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<wchar_t>
    {
      static const bool is_specialized = true;

      static wchar_t min() throw()
      { return (((wchar_t)(-1) < 0) ? (wchar_t)1 << (sizeof(wchar_t) * 8 - ((wchar_t)(-1) < 0)) : (wchar_t)0); }
      static wchar_t max() throw()
      { return (((wchar_t)(-1) < 0) ? ((wchar_t)1 << (sizeof(wchar_t) * 8 - ((wchar_t)(-1) < 0))) - 1 : ~(wchar_t)0); }

      static const int digits = (sizeof(wchar_t) * 8 - ((wchar_t)(-1) < 0));
      static const int digits10 = ((sizeof(wchar_t) * 8 - ((wchar_t)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = ((wchar_t)(-1) < 0);
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static wchar_t epsilon() throw()
      { return 0; }
      static wchar_t round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static wchar_t infinity() throw()
      { return wchar_t(); }
      static wchar_t quiet_NaN() throw()
      { return wchar_t(); }
      static wchar_t signaling_NaN() throw()
      { return wchar_t(); }
      static wchar_t denorm_min() throw()
      { return wchar_t(); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<short>
    {
      static const bool is_specialized = true;

      static short min() throw()
      { return -32767 - 1; }
      static short max() throw()
      { return 32767; }

      static const int digits = (sizeof(short) * 8 - ((short)(-1) < 0));
      static const int digits10 = ((sizeof(short) * 8 - ((short)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = true;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static short epsilon() throw()
      { return 0; }
      static short round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static short infinity() throw()
      { return short(); }
      static short quiet_NaN() throw()
      { return short(); }
      static short signaling_NaN() throw()
      { return short(); }
      static short denorm_min() throw()
      { return short(); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<unsigned short>
    {
      static const bool is_specialized = true;

      static unsigned short min() throw()
      { return 0; }
      static unsigned short max() throw()
      { return 32767 * 2U + 1; }

      static const int digits = (sizeof(unsigned short) * 8 - ((unsigned short)(-1) < 0));
      static const int digits10 = ((sizeof(unsigned short) * 8 - ((unsigned short)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = false;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static unsigned short epsilon() throw()
      { return 0; }
      static unsigned short round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static unsigned short infinity() throw()
      { return static_cast<unsigned short>(0); }
      static unsigned short quiet_NaN() throw()
      { return static_cast<unsigned short>(0); }
      static unsigned short signaling_NaN() throw()
      { return static_cast<unsigned short>(0); }
      static unsigned short denorm_min() throw()
      { return static_cast<unsigned short>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<int>
    {
      static const bool is_specialized = true;

      static int min() throw()
      { return -2147483647 - 1; }
      static int max() throw()
      { return 2147483647; }

      static const int digits = (sizeof(int) * 8 - ((int)(-1) < 0));
      static const int digits10 = ((sizeof(int) * 8 - ((int)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = true;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static int epsilon() throw()
      { return 0; }
      static int round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static int infinity() throw()
      { return static_cast<int>(0); }
      static int quiet_NaN() throw()
      { return static_cast<int>(0); }
      static int signaling_NaN() throw()
      { return static_cast<int>(0); }
      static int denorm_min() throw()
      { return static_cast<int>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<unsigned int>
    {
      static const bool is_specialized = true;

      static unsigned int min() throw()
      { return 0; }
      static unsigned int max() throw()
      { return 2147483647 * 2U + 1; }

      static const int digits = (sizeof(unsigned int) * 8 - ((unsigned int)(-1) < 0));
      static const int digits10 = ((sizeof(unsigned int) * 8 - ((unsigned int)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = false;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static unsigned int epsilon() throw()
      { return 0; }
      static unsigned int round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static unsigned int infinity() throw()
      { return static_cast<unsigned int>(0); }
      static unsigned int quiet_NaN() throw()
      { return static_cast<unsigned int>(0); }
      static unsigned int signaling_NaN() throw()
      { return static_cast<unsigned int>(0); }
      static unsigned int denorm_min() throw()
      { return static_cast<unsigned int>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<long>
    {
      static const bool is_specialized = true;

      static long min() throw()
      { return -9223372036854775807L - 1; }
      static long max() throw()
      { return 9223372036854775807L; }

      static const int digits = (sizeof(long) * 8 - ((long)(-1) < 0));
      static const int digits10 = ((sizeof(long) * 8 - ((long)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = true;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static long epsilon() throw()
      { return 0; }
      static long round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static long infinity() throw()
      { return static_cast<long>(0); }
      static long quiet_NaN() throw()
      { return static_cast<long>(0); }
      static long signaling_NaN() throw()
      { return static_cast<long>(0); }
      static long denorm_min() throw()
      { return static_cast<long>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<unsigned long>
    {
      static const bool is_specialized = true;

      static unsigned long min() throw()
      { return 0; }
      static unsigned long max() throw()
      { return 9223372036854775807L * 2UL + 1; }

      static const int digits = (sizeof(unsigned long) * 8 - ((unsigned long)(-1) < 0));
      static const int digits10 = ((sizeof(unsigned long) * 8 - ((unsigned long)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = false;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static unsigned long epsilon() throw()
      { return 0; }
      static unsigned long round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static unsigned long infinity() throw()
      { return static_cast<unsigned long>(0); }
      static unsigned long quiet_NaN() throw()
      { return static_cast<unsigned long>(0); }
      static unsigned long signaling_NaN() throw()
      { return static_cast<unsigned long>(0); }
      static unsigned long denorm_min() throw()
      { return static_cast<unsigned long>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<long long>
    {
      static const bool is_specialized = true;

      static long long min() throw()
      { return -9223372036854775807LL - 1; }
      static long long max() throw()
      { return 9223372036854775807LL; }

      static const int digits = (sizeof(long long) * 8 - ((long long)(-1) < 0));
      static const int digits10 = ((sizeof(long long) * 8 - ((long long)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = true;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static long long epsilon() throw()
      { return 0; }
      static long long round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static long long infinity() throw()
      { return static_cast<long long>(0); }
      static long long quiet_NaN() throw()
      { return static_cast<long long>(0); }
      static long long signaling_NaN() throw()
      { return static_cast<long long>(0); }
      static long long denorm_min() throw()
      { return static_cast<long long>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<unsigned long long>
    {
      static const bool is_specialized = true;

      static unsigned long long min() throw()
      { return 0; }
      static unsigned long long max() throw()
      { return 9223372036854775807LL * 2ULL + 1; }

      static const int digits = (sizeof(unsigned long long) * 8 - ((unsigned long long)(-1) < 0));
      static const int digits10 = ((sizeof(unsigned long long) * 8 - ((unsigned long long)(-1) < 0)) * 643 / 2136);
      static const bool is_signed = false;
      static const bool is_integer = true;
      static const bool is_exact = true;
      static const int radix = 2;
      static unsigned long long epsilon() throw()
      { return 0; }
      static unsigned long long round_error() throw()
      { return 0; }

      static const int min_exponent = 0;
      static const int min_exponent10 = 0;
      static const int max_exponent = 0;
      static const int max_exponent10 = 0;

      static const bool has_infinity = false;
      static const bool has_quiet_NaN = false;
      static const bool has_signaling_NaN = false;
      static const float_denorm_style has_denorm = denorm_absent;
      static const bool has_denorm_loss = false;

      static unsigned long long infinity() throw()
      { return static_cast<unsigned long long>(0); }
      static unsigned long long quiet_NaN() throw()
      { return static_cast<unsigned long long>(0); }
      static unsigned long long signaling_NaN() throw()
      { return static_cast<unsigned long long>(0); }
      static unsigned long long denorm_min() throw()
      { return static_cast<unsigned long long>(0); }

      static const bool is_iec559 = false;
      static const bool is_bounded = true;
      static const bool is_modulo = true;

      static const bool traps = true;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_toward_zero;
    };


  template<>
    struct numeric_limits<float>
    {
      static const bool is_specialized = true;

      static float min() throw()
      { return 1.17549435e-38F; }
      static float max() throw()
      { return 3.40282347e+38F; }

      static const int digits = 24;
      static const int digits10 = 6;
      static const bool is_signed = true;
      static const bool is_integer = false;
      static const bool is_exact = false;
      static const int radix = 2;
      static float epsilon() throw()
      { return 1.19209290e-7F; }
      static float round_error() throw()
      { return 0.5F; }

      static const int min_exponent = (-125);
      static const int min_exponent10 = (-37);
      static const int max_exponent = 128;
      static const int max_exponent10 = 38;

      static const bool has_infinity = 1;
      static const bool has_quiet_NaN = 1;
      static const bool has_signaling_NaN = has_quiet_NaN;
      static const float_denorm_style has_denorm
 = bool(1) ? denorm_present : denorm_absent;
      static const bool has_denorm_loss = false;

      static float infinity() throw()
      { return __builtin_huge_valf (); }
      static float quiet_NaN() throw()
      { return __builtin_nanf (""); }
      static float signaling_NaN() throw()
      { return __builtin_nansf (""); }
      static float denorm_min() throw()
      { return 1.40129846e-45F; }

      static const bool is_iec559
 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
      static const bool is_bounded = true;
      static const bool is_modulo = false;

      static const bool traps = false;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_to_nearest;
    };






  template<>
    struct numeric_limits<double>
    {
      static const bool is_specialized = true;

      static double min() throw()
      { return 2.2250738585072014e-308; }
      static double max() throw()
      { return 1.7976931348623157e+308; }

      static const int digits = 53;
      static const int digits10 = 15;
      static const bool is_signed = true;
      static const bool is_integer = false;
      static const bool is_exact = false;
      static const int radix = 2;
      static double epsilon() throw()
      { return 2.2204460492503131e-16; }
      static double round_error() throw()
      { return 0.5; }

      static const int min_exponent = (-1021);
      static const int min_exponent10 = (-307);
      static const int max_exponent = 1024;
      static const int max_exponent10 = 308;

      static const bool has_infinity = 1;
      static const bool has_quiet_NaN = 1;
      static const bool has_signaling_NaN = has_quiet_NaN;
      static const float_denorm_style has_denorm
 = bool(1) ? denorm_present : denorm_absent;
      static const bool has_denorm_loss = false;

      static double infinity() throw()
      { return __builtin_huge_val(); }
      static double quiet_NaN() throw()
      { return __builtin_nan (""); }
      static double signaling_NaN() throw()
      { return __builtin_nans (""); }
      static double denorm_min() throw()
      { return 4.9406564584124654e-324; }

      static const bool is_iec559
 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
      static const bool is_bounded = true;
      static const bool is_modulo = false;

      static const bool traps = false;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_to_nearest;
    };






  template<>
    struct numeric_limits<long double>
    {
      static const bool is_specialized = true;

      static long double min() throw()
      { return 3.36210314311209350626e-4932L; }
      static long double max() throw()
      { return 1.18973149535723176502e+4932L; }

      static const int digits = 64;
      static const int digits10 = 18;
      static const bool is_signed = true;
      static const bool is_integer = false;
      static const bool is_exact = false;
      static const int radix = 2;
      static long double epsilon() throw()
      { return 1.08420217248550443401e-19L; }
      static long double round_error() throw()
      { return 0.5L; }

      static const int min_exponent = (-16381);
      static const int min_exponent10 = (-4931);
      static const int max_exponent = 16384;
      static const int max_exponent10 = 4932;

      static const bool has_infinity = 1;
      static const bool has_quiet_NaN = 1;
      static const bool has_signaling_NaN = has_quiet_NaN;
      static const float_denorm_style has_denorm
 = bool(1) ? denorm_present : denorm_absent;
      static const bool has_denorm_loss
 = false;

      static long double infinity() throw()
      { return __builtin_huge_vall (); }
      static long double quiet_NaN() throw()
      { return __builtin_nanl (""); }
      static long double signaling_NaN() throw()
      { return __builtin_nansl (""); }
      static long double denorm_min() throw()
      { return 3.64519953188247460253e-4951L; }

      static const bool is_iec559
 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
      static const bool is_bounded = true;
      static const bool is_modulo = false;

      static const bool traps = false;
      static const bool tinyness_before = false;
      static const float_round_style round_style = round_to_nearest;
    };





}

namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _Tp>
    pair<_Tp*, ptrdiff_t>
    __get_temporary_buffer(ptrdiff_t __len, _Tp*)
    {
      const ptrdiff_t __max = numeric_limits<ptrdiff_t>::max() / sizeof(_Tp);
      if (__len > __max)
 __len = __max;

      while (__len > 0)
 {
   _Tp* __tmp = static_cast<_Tp*>(::operator new(__len * sizeof(_Tp),
       nothrow));
   if (__tmp != 0)
     return pair<_Tp*, ptrdiff_t>(__tmp, __len);
   __len /= 2;
 }
      return pair<_Tp*, ptrdiff_t>(static_cast<_Tp*>(0), 0);
    }
  template<typename _Tp>
    inline pair<_Tp*, ptrdiff_t>
    get_temporary_buffer(ptrdiff_t __len)
    { return std::__get_temporary_buffer(__len, static_cast<_Tp*>(0)); }
  template<typename _Tp>
    void
    return_temporary_buffer(_Tp* __p)
    { ::operator delete(__p, nothrow); }
  template<typename _Tp1>
    struct auto_ptr_ref
    {
      _Tp1* _M_ptr;

      explicit
      auto_ptr_ref(_Tp1* __p): _M_ptr(__p) { }
    };
  template<typename _Tp>
    class auto_ptr
    {
    private:
      _Tp* _M_ptr;

    public:

      typedef _Tp element_type;







      explicit
      auto_ptr(element_type* __p = 0) throw() : _M_ptr(__p) { }
      auto_ptr(auto_ptr& __a) throw() : _M_ptr(__a.release()) { }
      template<typename _Tp1>
        auto_ptr(auto_ptr<_Tp1>& __a) throw() : _M_ptr(__a.release()) { }
      auto_ptr&
      operator=(auto_ptr& __a) throw()
      {
 reset(__a.release());
 return *this;
      }
      template<typename _Tp1>
        auto_ptr&
        operator=(auto_ptr<_Tp1>& __a) throw()
        {
   reset(__a.release());
   return *this;
 }
      ~auto_ptr() { delete _M_ptr; }
      element_type&
      operator*() const throw()
      {
                                   ;
 return *_M_ptr;
      }







      element_type*
      operator->() const throw()
      {
                                   ;
 return _M_ptr;
      }
      element_type*
      get() const throw() { return _M_ptr; }
      element_type*
      release() throw()
      {
 element_type* __tmp = _M_ptr;
 _M_ptr = 0;
 return __tmp;
      }
      void
      reset(element_type* __p = 0) throw()
      {
 if (__p != _M_ptr)
   {
     delete _M_ptr;
     _M_ptr = __p;
   }
      }
      auto_ptr(auto_ptr_ref<element_type> __ref) throw()
      : _M_ptr(__ref._M_ptr) { }

      auto_ptr&
      operator=(auto_ptr_ref<element_type> __ref) throw()
      {
 if (__ref._M_ptr != this->get())
   {
     delete _M_ptr;
     _M_ptr = __ref._M_ptr;
   }
 return *this;
      }

      template<typename _Tp1>
        operator auto_ptr_ref<_Tp1>() throw()
        { return auto_ptr_ref<_Tp1>(this->release()); }

      template<typename _Tp1>
        operator auto_ptr<_Tp1>() throw()
        { return auto_ptr<_Tp1>(this->release()); }
  };

}





namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _CharT, typename _Traits>
    inline void
    __ostream_write(basic_ostream<_CharT, _Traits>& __out,
      const _CharT* __s, streamsize __n)
    {
      typedef basic_ostream<_CharT, _Traits> __ostream_type;
      typedef typename __ostream_type::ios_base __ios_base;

      const streamsize __put = __out.rdbuf()->sputn(__s, __n);
      if (__put != __n)
 __out.setstate(__ios_base::badbit);
    }

  template<typename _CharT, typename _Traits>
    inline void
    __ostream_fill(basic_ostream<_CharT, _Traits>& __out, streamsize __n)
    {
      typedef basic_ostream<_CharT, _Traits> __ostream_type;
      typedef typename __ostream_type::ios_base __ios_base;

      const _CharT __c = __out.fill();
      for (; __n > 0; --__n)
 {
   const typename _Traits::int_type __put = __out.rdbuf()->sputc(__c);
   if (_Traits::eq_int_type(__put, _Traits::eof()))
     {
       __out.setstate(__ios_base::badbit);
       break;
     }
 }
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    __ostream_insert(basic_ostream<_CharT, _Traits>& __out,
       const _CharT* __s, streamsize __n)
    {
      typedef basic_ostream<_CharT, _Traits> __ostream_type;
      typedef typename __ostream_type::ios_base __ios_base;

      typename __ostream_type::sentry __cerb(__out);
      if (__cerb)
 {
   if (true)
     {
       const streamsize __w = __out.width();
       if (__w > __n)
  {
    const bool __left = ((__out.flags()
     & __ios_base::adjustfield)
           == __ios_base::left);
    if (!__left)
      __ostream_fill(__out, __w - __n);
    if (__out.good())
      __ostream_write(__out, __s, __n);
    if (__left && __out.good())
      __ostream_fill(__out, __w - __n);
  }
       else
  __ostream_write(__out, __s, __n);
       __out.width(0);
     }
   if (false)
     { __out._M_setstate(__ios_base::badbit); }
 }
      return __out;
    }





  extern template ostream& __ostream_insert(ostream&, const char*, streamsize);


  extern template wostream& __ostream_insert(wostream&, const wchar_t*,
          streamsize);



}

namespace std __attribute__ ((__visibility__ ("default"))) {
  template <class _Arg, class _Result>
    struct unary_function
    {
      typedef _Arg argument_type;


      typedef _Result result_type;
    };




  template <class _Arg1, class _Arg2, class _Result>
    struct binary_function
    {
      typedef _Arg1 first_argument_type;


      typedef _Arg2 second_argument_type;
      typedef _Result result_type;
    };
  template <class _Tp>
    struct plus : public binary_function<_Tp, _Tp, _Tp>
    {
      _Tp
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x + __y; }
    };


  template <class _Tp>
    struct minus : public binary_function<_Tp, _Tp, _Tp>
    {
      _Tp
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x - __y; }
    };


  template <class _Tp>
    struct multiplies : public binary_function<_Tp, _Tp, _Tp>
    {
      _Tp
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x * __y; }
    };


  template <class _Tp>
    struct divides : public binary_function<_Tp, _Tp, _Tp>
    {
      _Tp
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x / __y; }
    };


  template <class _Tp>
    struct modulus : public binary_function<_Tp, _Tp, _Tp>
    {
      _Tp
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x % __y; }
    };


  template <class _Tp>
    struct negate : public unary_function<_Tp, _Tp>
    {
      _Tp
      operator()(const _Tp& __x) const
      { return -__x; }
    };
  template <class _Tp>
    struct equal_to : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x == __y; }
    };


  template <class _Tp>
    struct not_equal_to : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x != __y; }
    };


  template <class _Tp>
    struct greater : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x > __y; }
    };


  template <class _Tp>
    struct less : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x < __y; }
    };


  template <class _Tp>
    struct greater_equal : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x >= __y; }
    };


  template <class _Tp>
    struct less_equal : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x <= __y; }
    };
  template <class _Tp>
    struct logical_and : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x && __y; }
    };


  template <class _Tp>
    struct logical_or : public binary_function<_Tp, _Tp, bool>
    {
      bool
      operator()(const _Tp& __x, const _Tp& __y) const
      { return __x || __y; }
    };


  template <class _Tp>
    struct logical_not : public unary_function<_Tp, bool>
    {
      bool
      operator()(const _Tp& __x) const
      { return !__x; }
    };
  template <class _Predicate>
    class unary_negate
    : public unary_function<typename _Predicate::argument_type, bool>
    {
    protected:
      _Predicate _M_pred;
    public:
      explicit
      unary_negate(const _Predicate& __x) : _M_pred(__x) {}

      bool
      operator()(const typename _Predicate::argument_type& __x) const
      { return !_M_pred(__x); }
    };


  template <class _Predicate>
    inline unary_negate<_Predicate>
    not1(const _Predicate& __pred)
    { return unary_negate<_Predicate>(__pred); }


  template <class _Predicate>
    class binary_negate
    : public binary_function<typename _Predicate::first_argument_type,
        typename _Predicate::second_argument_type,
        bool>
    {
    protected:
      _Predicate _M_pred;
    public:
      explicit
      binary_negate(const _Predicate& __x)
      : _M_pred(__x) { }

      bool
      operator()(const typename _Predicate::first_argument_type& __x,
   const typename _Predicate::second_argument_type& __y) const
      { return !_M_pred(__x, __y); }
    };


  template <class _Predicate>
    inline binary_negate<_Predicate>
    not2(const _Predicate& __pred)
    { return binary_negate<_Predicate>(__pred); }
  template <class _Operation>
    class binder1st
    : public unary_function<typename _Operation::second_argument_type,
       typename _Operation::result_type>
    {
    protected:
      _Operation op;
      typename _Operation::first_argument_type value;
    public:
      binder1st(const _Operation& __x,
  const typename _Operation::first_argument_type& __y)
      : op(__x), value(__y) {}

      typename _Operation::result_type
      operator()(const typename _Operation::second_argument_type& __x) const
      { return op(value, __x); }



      typename _Operation::result_type
      operator()(typename _Operation::second_argument_type& __x) const
      { return op(value, __x); }
    };


  template <class _Operation, class _Tp>
    inline binder1st<_Operation>
    bind1st(const _Operation& __fn, const _Tp& __x)
    {
      typedef typename _Operation::first_argument_type _Arg1_type;
      return binder1st<_Operation>(__fn, _Arg1_type(__x));
    }


  template <class _Operation>
    class binder2nd
    : public unary_function<typename _Operation::first_argument_type,
       typename _Operation::result_type>
    {
    protected:
      _Operation op;
      typename _Operation::second_argument_type value;
    public:
      binder2nd(const _Operation& __x,
  const typename _Operation::second_argument_type& __y)
      : op(__x), value(__y) {}

      typename _Operation::result_type
      operator()(const typename _Operation::first_argument_type& __x) const
      { return op(__x, value); }



      typename _Operation::result_type
      operator()(typename _Operation::first_argument_type& __x) const
      { return op(__x, value); }
    };


  template <class _Operation, class _Tp>
    inline binder2nd<_Operation>
    bind2nd(const _Operation& __fn, const _Tp& __x)
    {
      typedef typename _Operation::second_argument_type _Arg2_type;
      return binder2nd<_Operation>(__fn, _Arg2_type(__x));
    }
  template <class _Arg, class _Result>
    class pointer_to_unary_function : public unary_function<_Arg, _Result>
    {
    protected:
      _Result (*_M_ptr)(_Arg);
    public:
      pointer_to_unary_function() {}

      explicit
      pointer_to_unary_function(_Result (*__x)(_Arg))
      : _M_ptr(__x) {}

      _Result
      operator()(_Arg __x) const
      { return _M_ptr(__x); }
    };


  template <class _Arg, class _Result>
    inline pointer_to_unary_function<_Arg, _Result>
    ptr_fun(_Result (*__x)(_Arg))
    { return pointer_to_unary_function<_Arg, _Result>(__x); }


  template <class _Arg1, class _Arg2, class _Result>
    class pointer_to_binary_function
    : public binary_function<_Arg1, _Arg2, _Result>
    {
    protected:
      _Result (*_M_ptr)(_Arg1, _Arg2);
    public:
      pointer_to_binary_function() {}

      explicit
      pointer_to_binary_function(_Result (*__x)(_Arg1, _Arg2))
      : _M_ptr(__x) {}

      _Result
      operator()(_Arg1 __x, _Arg2 __y) const
      { return _M_ptr(__x, __y); }
    };


  template <class _Arg1, class _Arg2, class _Result>
    inline pointer_to_binary_function<_Arg1, _Arg2, _Result>
    ptr_fun(_Result (*__x)(_Arg1, _Arg2))
    { return pointer_to_binary_function<_Arg1, _Arg2, _Result>(__x); }


  template <class _Tp>
    struct _Identity : public unary_function<_Tp,_Tp>
    {
      _Tp&
      operator()(_Tp& __x) const
      { return __x; }

      const _Tp&
      operator()(const _Tp& __x) const
      { return __x; }
    };

  template <class _Pair>
    struct _Select1st : public unary_function<_Pair,
           typename _Pair::first_type>
    {
      typename _Pair::first_type&
      operator()(_Pair& __x) const
      { return __x.first; }

      const typename _Pair::first_type&
      operator()(const _Pair& __x) const
      { return __x.first; }
    };

  template <class _Pair>
    struct _Select2nd : public unary_function<_Pair,
           typename _Pair::second_type>
    {
      typename _Pair::second_type&
      operator()(_Pair& __x) const
      { return __x.second; }

      const typename _Pair::second_type&
      operator()(const _Pair& __x) const
      { return __x.second; }
    };
  template <class _Ret, class _Tp>
    class mem_fun_t : public unary_function<_Tp*, _Ret>
    {
    public:
      explicit
      mem_fun_t(_Ret (_Tp::*__pf)())
      : _M_f(__pf) {}

      _Ret
      operator()(_Tp* __p) const
      { return (__p->*_M_f)(); }
    private:
      _Ret (_Tp::*_M_f)();
    };


  template <class _Ret, class _Tp>
    class const_mem_fun_t : public unary_function<const _Tp*, _Ret>
    {
    public:
      explicit
      const_mem_fun_t(_Ret (_Tp::*__pf)() const)
      : _M_f(__pf) {}

      _Ret
      operator()(const _Tp* __p) const
      { return (__p->*_M_f)(); }
    private:
      _Ret (_Tp::*_M_f)() const;
    };


  template <class _Ret, class _Tp>
    class mem_fun_ref_t : public unary_function<_Tp, _Ret>
    {
    public:
      explicit
      mem_fun_ref_t(_Ret (_Tp::*__pf)())
      : _M_f(__pf) {}

      _Ret
      operator()(_Tp& __r) const
      { return (__r.*_M_f)(); }
    private:
      _Ret (_Tp::*_M_f)();
  };


  template <class _Ret, class _Tp>
    class const_mem_fun_ref_t : public unary_function<_Tp, _Ret>
    {
    public:
      explicit
      const_mem_fun_ref_t(_Ret (_Tp::*__pf)() const)
      : _M_f(__pf) {}

      _Ret
      operator()(const _Tp& __r) const
      { return (__r.*_M_f)(); }
    private:
      _Ret (_Tp::*_M_f)() const;
    };


  template <class _Ret, class _Tp, class _Arg>
    class mem_fun1_t : public binary_function<_Tp*, _Arg, _Ret>
    {
    public:
      explicit
      mem_fun1_t(_Ret (_Tp::*__pf)(_Arg))
      : _M_f(__pf) {}

      _Ret
      operator()(_Tp* __p, _Arg __x) const
      { return (__p->*_M_f)(__x); }
    private:
      _Ret (_Tp::*_M_f)(_Arg);
    };


  template <class _Ret, class _Tp, class _Arg>
    class const_mem_fun1_t : public binary_function<const _Tp*, _Arg, _Ret>
    {
    public:
      explicit
      const_mem_fun1_t(_Ret (_Tp::*__pf)(_Arg) const)
      : _M_f(__pf) {}

      _Ret
      operator()(const _Tp* __p, _Arg __x) const
      { return (__p->*_M_f)(__x); }
    private:
      _Ret (_Tp::*_M_f)(_Arg) const;
    };


  template <class _Ret, class _Tp, class _Arg>
    class mem_fun1_ref_t : public binary_function<_Tp, _Arg, _Ret>
    {
    public:
      explicit
      mem_fun1_ref_t(_Ret (_Tp::*__pf)(_Arg))
      : _M_f(__pf) {}

      _Ret
      operator()(_Tp& __r, _Arg __x) const
      { return (__r.*_M_f)(__x); }
    private:
      _Ret (_Tp::*_M_f)(_Arg);
    };


  template <class _Ret, class _Tp, class _Arg>
    class const_mem_fun1_ref_t : public binary_function<_Tp, _Arg, _Ret>
    {
    public:
      explicit
      const_mem_fun1_ref_t(_Ret (_Tp::*__pf)(_Arg) const)
      : _M_f(__pf) {}

      _Ret
      operator()(const _Tp& __r, _Arg __x) const
      { return (__r.*_M_f)(__x); }
    private:
      _Ret (_Tp::*_M_f)(_Arg) const;
    };



  template <class _Ret, class _Tp>
    inline mem_fun_t<_Ret, _Tp>
    mem_fun(_Ret (_Tp::*__f)())
    { return mem_fun_t<_Ret, _Tp>(__f); }

  template <class _Ret, class _Tp>
    inline const_mem_fun_t<_Ret, _Tp>
    mem_fun(_Ret (_Tp::*__f)() const)
    { return const_mem_fun_t<_Ret, _Tp>(__f); }

  template <class _Ret, class _Tp>
    inline mem_fun_ref_t<_Ret, _Tp>
    mem_fun_ref(_Ret (_Tp::*__f)())
    { return mem_fun_ref_t<_Ret, _Tp>(__f); }

  template <class _Ret, class _Tp>
    inline const_mem_fun_ref_t<_Ret, _Tp>
    mem_fun_ref(_Ret (_Tp::*__f)() const)
    { return const_mem_fun_ref_t<_Ret, _Tp>(__f); }

  template <class _Ret, class _Tp, class _Arg>
    inline mem_fun1_t<_Ret, _Tp, _Arg>
    mem_fun(_Ret (_Tp::*__f)(_Arg))
    { return mem_fun1_t<_Ret, _Tp, _Arg>(__f); }

  template <class _Ret, class _Tp, class _Arg>
    inline const_mem_fun1_t<_Ret, _Tp, _Arg>
    mem_fun(_Ret (_Tp::*__f)(_Arg) const)
    { return const_mem_fun1_t<_Ret, _Tp, _Arg>(__f); }

  template <class _Ret, class _Tp, class _Arg>
    inline mem_fun1_ref_t<_Ret, _Tp, _Arg>
    mem_fun_ref(_Ret (_Tp::*__f)(_Arg))
    { return mem_fun1_ref_t<_Ret, _Tp, _Arg>(__f); }

  template <class _Ret, class _Tp, class _Arg>
    inline const_mem_fun1_ref_t<_Ret, _Tp, _Arg>
    mem_fun_ref(_Ret (_Tp::*__f)(_Arg) const)
    { return const_mem_fun1_ref_t<_Ret, _Tp, _Arg>(__f); }



}

typedef int _Atomic_word;

namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {






  static inline _Atomic_word
  __exchange_and_add(volatile _Atomic_word* __mem, int __val)
  { return __sync_fetch_and_add(__mem, __val); }

  static inline void
  __atomic_add(volatile _Atomic_word* __mem, int __val)
  { __sync_fetch_and_add(__mem, __val); }
  static inline _Atomic_word
  __exchange_and_add_single(_Atomic_word* __mem, int __val)
  {
    _Atomic_word __result = *__mem;
    *__mem += __val;
    return __result;
  }

  static inline void
  __atomic_add_single(_Atomic_word* __mem, int __val)
  { *__mem += __val; }

  static inline _Atomic_word
  __attribute__ ((__unused__))
  __exchange_and_add_dispatch(_Atomic_word* __mem, int __val)
  {

    if (__gthread_active_p())
      return __exchange_and_add(__mem, __val);
    else
      return __exchange_and_add_single(__mem, __val);



  }

  static inline void
  __attribute__ ((__unused__))
  __atomic_add_dispatch(_Atomic_word* __mem, int __val)
  {

    if (__gthread_active_p())
      __atomic_add(__mem, __val);
    else
      __atomic_add_single(__mem, __val);



  }

}


namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _CharT, typename _Traits, typename _Alloc>
    class basic_string
    {
      typedef typename _Alloc::template rebind<_CharT>::other _CharT_alloc_type;


    public:
      typedef _Traits traits_type;
      typedef typename _Traits::char_type value_type;
      typedef _Alloc allocator_type;
      typedef typename _CharT_alloc_type::size_type size_type;
      typedef typename _CharT_alloc_type::difference_type difference_type;
      typedef typename _CharT_alloc_type::reference reference;
      typedef typename _CharT_alloc_type::const_reference const_reference;
      typedef typename _CharT_alloc_type::pointer pointer;
      typedef typename _CharT_alloc_type::const_pointer const_pointer;
      typedef __gnu_cxx::__normal_iterator<pointer, basic_string> iterator;
      typedef __gnu_cxx::__normal_iterator<const_pointer, basic_string>
                                                            const_iterator;
      typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
      typedef std::reverse_iterator<iterator> reverse_iterator;

    private:
      struct _Rep_base
      {
 size_type _M_length;
 size_type _M_capacity;
 _Atomic_word _M_refcount;
      };

      struct _Rep : _Rep_base
      {

 typedef typename _Alloc::template rebind<char>::other _Raw_bytes_alloc;
 static const size_type _S_max_size;
 static const _CharT _S_terminal;



        static size_type _S_empty_rep_storage[];

        static _Rep&
        _S_empty_rep()
        {



   void* __p = reinterpret_cast<void*>(&_S_empty_rep_storage);
   return *reinterpret_cast<_Rep*>(__p);
 }

        bool
 _M_is_leaked() const
        { return this->_M_refcount < 0; }

        bool
 _M_is_shared() const
        { return this->_M_refcount > 0; }

        void
 _M_set_leaked()
        { this->_M_refcount = -1; }

        void
 _M_set_sharable()
        { this->_M_refcount = 0; }

 void
 _M_set_length_and_sharable(size_type __n)
 {
   this->_M_set_sharable();
   this->_M_length = __n;
   traits_type::assign(this->_M_refdata()[__n], _S_terminal);


 }

 _CharT*
 _M_refdata() throw()
 { return reinterpret_cast<_CharT*>(this + 1); }

 _CharT*
 _M_grab(const _Alloc& __alloc1, const _Alloc& __alloc2)
 {
   return (!_M_is_leaked() && __alloc1 == __alloc2)
           ? _M_refcopy() : _M_clone(__alloc1);
 }


 static _Rep*
 _S_create(size_type, size_type, const _Alloc&);

 void
 _M_dispose(const _Alloc& __a)
 {

   if (__builtin_expect(this != &_S_empty_rep(), false))

     if (__gnu_cxx::__exchange_and_add_dispatch(&this->_M_refcount,
             -1) <= 0)
       _M_destroy(__a);
 }

 void
 _M_destroy(const _Alloc&) throw();

 _CharT*
 _M_refcopy() throw()
 {

   if (__builtin_expect(this != &_S_empty_rep(), false))

            __gnu_cxx::__atomic_add_dispatch(&this->_M_refcount, 1);
   return _M_refdata();
 }

 _CharT*
 _M_clone(const _Alloc&, size_type __res = 0);
      };


      struct _Alloc_hider : _Alloc
      {
 _Alloc_hider(_CharT* __dat, const _Alloc& __a)
 : _Alloc(__a), _M_p(__dat) { }

 _CharT* _M_p;
      };

    public:




      static const size_type npos = static_cast<size_type>(-1);

    private:

      mutable _Alloc_hider _M_dataplus;

      _CharT*
      _M_data() const
      { return _M_dataplus._M_p; }

      _CharT*
      _M_data(_CharT* __p)
      { return (_M_dataplus._M_p = __p); }

      _Rep*
      _M_rep() const
      { return &((reinterpret_cast<_Rep*> (_M_data()))[-1]); }



      iterator
      _M_ibegin() const
      { return iterator(_M_data()); }

      iterator
      _M_iend() const
      { return iterator(_M_data() + this->size()); }

      void
      _M_leak()
      {
 if (!_M_rep()->_M_is_leaked())
   _M_leak_hard();
      }

      size_type
      _M_check(size_type __pos, const char* __s) const
      {
 if (__pos > this->size())
   __throw_out_of_range((__s));
 return __pos;
      }

      void
      _M_check_length(size_type __n1, size_type __n2, const char* __s) const
      {
 if (this->max_size() - (this->size() - __n1) < __n2)
   __throw_length_error((__s));
      }


      size_type
      _M_limit(size_type __pos, size_type __off) const
      {
 const bool __testoff = __off < this->size() - __pos;
 return __testoff ? __off : this->size() - __pos;
      }


      bool
      _M_disjunct(const _CharT* __s) const
      {
 return (less<const _CharT*>()(__s, _M_data())
  || less<const _CharT*>()(_M_data() + this->size(), __s));
      }



      static void
      _M_copy(_CharT* __d, const _CharT* __s, size_type __n)
      {
 if (__n == 1)
   traits_type::assign(*__d, *__s);
 else
   traits_type::copy(__d, __s, __n);
      }

      static void
      _M_move(_CharT* __d, const _CharT* __s, size_type __n)
      {
 if (__n == 1)
   traits_type::assign(*__d, *__s);
 else
   traits_type::move(__d, __s, __n);
      }

      static void
      _M_assign(_CharT* __d, size_type __n, _CharT __c)
      {
 if (__n == 1)
   traits_type::assign(*__d, __c);
 else
   traits_type::assign(__d, __n, __c);
      }



      template<class _Iterator>
        static void
        _S_copy_chars(_CharT* __p, _Iterator __k1, _Iterator __k2)
        {
   for (; __k1 != __k2; ++__k1, ++__p)
     traits_type::assign(*__p, *__k1);
 }

      static void
      _S_copy_chars(_CharT* __p, iterator __k1, iterator __k2)
      { _S_copy_chars(__p, __k1.base(), __k2.base()); }

      static void
      _S_copy_chars(_CharT* __p, const_iterator __k1, const_iterator __k2)
      { _S_copy_chars(__p, __k1.base(), __k2.base()); }

      static void
      _S_copy_chars(_CharT* __p, _CharT* __k1, _CharT* __k2)
      { _M_copy(__p, __k1, __k2 - __k1); }

      static void
      _S_copy_chars(_CharT* __p, const _CharT* __k1, const _CharT* __k2)
      { _M_copy(__p, __k1, __k2 - __k1); }

      void
      _M_mutate(size_type __pos, size_type __len1, size_type __len2);

      void
      _M_leak_hard();

      static _Rep&
      _S_empty_rep()
      { return _Rep::_S_empty_rep(); }

    public:







      inline
      basic_string();




      explicit
      basic_string(const _Alloc& __a);






      basic_string(const basic_string& __str);






      basic_string(const basic_string& __str, size_type __pos,
     size_type __n = npos);







      basic_string(const basic_string& __str, size_type __pos,
     size_type __n, const _Alloc& __a);
      basic_string(const _CharT* __s, size_type __n,
     const _Alloc& __a = _Alloc());





      basic_string(const _CharT* __s, const _Alloc& __a = _Alloc());






      basic_string(size_type __n, _CharT __c, const _Alloc& __a = _Alloc());







      template<class _InputIterator>
        basic_string(_InputIterator __beg, _InputIterator __end,
       const _Alloc& __a = _Alloc());




      ~basic_string()
      { _M_rep()->_M_dispose(this->get_allocator()); }





      basic_string&
      operator=(const basic_string& __str)
      { return this->assign(__str); }





      basic_string&
      operator=(const _CharT* __s)
      { return this->assign(__s); }
      basic_string&
      operator=(_CharT __c)
      {
 this->assign(1, __c);
 return *this;
      }






      iterator
      begin()
      {
 _M_leak();
 return iterator(_M_data());
      }





      const_iterator
      begin() const
      { return const_iterator(_M_data()); }





      iterator
      end()
      {
 _M_leak();
 return iterator(_M_data() + this->size());
      }





      const_iterator
      end() const
      { return const_iterator(_M_data() + this->size()); }






      reverse_iterator
      rbegin()
      { return reverse_iterator(this->end()); }






      const_reverse_iterator
      rbegin() const
      { return const_reverse_iterator(this->end()); }






      reverse_iterator
      rend()
      { return reverse_iterator(this->begin()); }






      const_reverse_iterator
      rend() const
      { return const_reverse_iterator(this->begin()); }

    public:



      size_type
      size() const
      { return _M_rep()->_M_length; }



      size_type
      length() const
      { return _M_rep()->_M_length; }


      size_type
      max_size() const
      { return _Rep::_S_max_size; }
      void
      resize(size_type __n, _CharT __c);
      void
      resize(size_type __n)
      { this->resize(__n, _CharT()); }





      size_type
      capacity() const
      { return _M_rep()->_M_capacity; }
      void
      reserve(size_type __res_arg = 0);




      void
      clear()
      { _M_mutate(0, this->size(), 0); }




      bool
      empty() const
      { return this->size() == 0; }
      const_reference
      operator[] (size_type __pos) const
      {
                                       ;
 return _M_data()[__pos];
      }
      reference
      operator[](size_type __pos)
      {

                                       ;

                                         ;
 _M_leak();
 return _M_data()[__pos];
      }
      const_reference
      at(size_type __n) const
      {
 if (__n >= this->size())
   __throw_out_of_range(("basic_string::at"));
 return _M_data()[__n];
      }
      reference
      at(size_type __n)
      {
 if (__n >= size())
   __throw_out_of_range(("basic_string::at"));
 _M_leak();
 return _M_data()[__n];
      }







      basic_string&
      operator+=(const basic_string& __str)
      { return this->append(__str); }






      basic_string&
      operator+=(const _CharT* __s)
      { return this->append(__s); }






      basic_string&
      operator+=(_CharT __c)
      {
 this->push_back(__c);
 return *this;
      }






      basic_string&
      append(const basic_string& __str);
      basic_string&
      append(const basic_string& __str, size_type __pos, size_type __n);







      basic_string&
      append(const _CharT* __s, size_type __n);






      basic_string&
      append(const _CharT* __s)
      {
                               ;
 return this->append(__s, traits_type::length(__s));
      }
      basic_string&
      append(size_type __n, _CharT __c);
      template<class _InputIterator>
        basic_string&
        append(_InputIterator __first, _InputIterator __last)
        { return this->replace(_M_iend(), _M_iend(), __first, __last); }





      void
      push_back(_CharT __c)
      {
 const size_type __len = 1 + this->size();
 if (__len > this->capacity() || _M_rep()->_M_is_shared())
   this->reserve(__len);
 traits_type::assign(_M_data()[this->size()], __c);
 _M_rep()->_M_set_length_and_sharable(__len);
      }






      basic_string&
      assign(const basic_string& __str);
      basic_string&
      assign(const basic_string& __str, size_type __pos, size_type __n)
      { return this->assign(__str._M_data()
       + __str._M_check(__pos, "basic_string::assign"),
       __str._M_limit(__pos, __n)); }
      basic_string&
      assign(const _CharT* __s, size_type __n);
      basic_string&
      assign(const _CharT* __s)
      {
                               ;
 return this->assign(__s, traits_type::length(__s));
      }
      basic_string&
      assign(size_type __n, _CharT __c)
      { return _M_replace_aux(size_type(0), this->size(), __n, __c); }
      template<class _InputIterator>
        basic_string&
        assign(_InputIterator __first, _InputIterator __last)
        { return this->replace(_M_ibegin(), _M_iend(), __first, __last); }
      void
      insert(iterator __p, size_type __n, _CharT __c)
      { this->replace(__p, __p, __n, __c); }
      template<class _InputIterator>
        void
        insert(iterator __p, _InputIterator __beg, _InputIterator __end)
        { this->replace(__p, __p, __beg, __end); }
      basic_string&
      insert(size_type __pos1, const basic_string& __str)
      { return this->insert(__pos1, __str, size_type(0), __str.size()); }
      basic_string&
      insert(size_type __pos1, const basic_string& __str,
      size_type __pos2, size_type __n)
      { return this->insert(__pos1, __str._M_data()
       + __str._M_check(__pos2, "basic_string::insert"),
       __str._M_limit(__pos2, __n)); }
      basic_string&
      insert(size_type __pos, const _CharT* __s, size_type __n);
      basic_string&
      insert(size_type __pos, const _CharT* __s)
      {
                               ;
 return this->insert(__pos, __s, traits_type::length(__s));
      }
      basic_string&
      insert(size_type __pos, size_type __n, _CharT __c)
      { return _M_replace_aux(_M_check(__pos, "basic_string::insert"),
         size_type(0), __n, __c); }
      iterator
      insert(iterator __p, _CharT __c)
      {
                                                                 ;
 const size_type __pos = __p - _M_ibegin();
 _M_replace_aux(__pos, size_type(0), size_type(1), __c);
 _M_rep()->_M_set_leaked();
 return iterator(_M_data() + __pos);
      }
      basic_string&
      erase(size_type __pos = 0, size_type __n = npos)
      {
 _M_mutate(_M_check(__pos, "basic_string::erase"),
    _M_limit(__pos, __n), size_type(0));
 return *this;
      }
      iterator
      erase(iterator __position)
      {

                               ;
 const size_type __pos = __position - _M_ibegin();
 _M_mutate(__pos, size_type(1), size_type(0));
 _M_rep()->_M_set_leaked();
 return iterator(_M_data() + __pos);
      }
      iterator
      erase(iterator __first, iterator __last)
      {

                            ;
        const size_type __pos = __first - _M_ibegin();
 _M_mutate(__pos, __last - __first, size_type(0));
 _M_rep()->_M_set_leaked();
 return iterator(_M_data() + __pos);
      }
      basic_string&
      replace(size_type __pos, size_type __n, const basic_string& __str)
      { return this->replace(__pos, __n, __str._M_data(), __str.size()); }
      basic_string&
      replace(size_type __pos1, size_type __n1, const basic_string& __str,
       size_type __pos2, size_type __n2)
      { return this->replace(__pos1, __n1, __str._M_data()
        + __str._M_check(__pos2, "basic_string::replace"),
        __str._M_limit(__pos2, __n2)); }
      basic_string&
      replace(size_type __pos, size_type __n1, const _CharT* __s,
       size_type __n2);
      basic_string&
      replace(size_type __pos, size_type __n1, const _CharT* __s)
      {
                               ;
 return this->replace(__pos, __n1, __s, traits_type::length(__s));
      }
      basic_string&
      replace(size_type __pos, size_type __n1, size_type __n2, _CharT __c)
      { return _M_replace_aux(_M_check(__pos, "basic_string::replace"),
         _M_limit(__pos, __n1), __n2, __c); }
      basic_string&
      replace(iterator __i1, iterator __i2, const basic_string& __str)
      { return this->replace(__i1, __i2, __str._M_data(), __str.size()); }
      basic_string&
      replace(iterator __i1, iterator __i2, const _CharT* __s, size_type __n)
      {

                          ;
 return this->replace(__i1 - _M_ibegin(), __i2 - __i1, __s, __n);
      }
      basic_string&
      replace(iterator __i1, iterator __i2, const _CharT* __s)
      {
                               ;
 return this->replace(__i1, __i2, __s, traits_type::length(__s));
      }
      basic_string&
      replace(iterator __i1, iterator __i2, size_type __n, _CharT __c)
      {

                          ;
 return _M_replace_aux(__i1 - _M_ibegin(), __i2 - __i1, __n, __c);
      }
      template<class _InputIterator>
        basic_string&
        replace(iterator __i1, iterator __i2,
  _InputIterator __k1, _InputIterator __k2)
        {

                            ;
                                             ;
   typedef typename std::__is_integer<_InputIterator>::__type _Integral;
   return _M_replace_dispatch(__i1, __i2, __k1, __k2, _Integral());
 }



      basic_string&
      replace(iterator __i1, iterator __i2, _CharT* __k1, _CharT* __k2)
      {

                          ;
                                           ;
 return this->replace(__i1 - _M_ibegin(), __i2 - __i1,
        __k1, __k2 - __k1);
      }

      basic_string&
      replace(iterator __i1, iterator __i2,
       const _CharT* __k1, const _CharT* __k2)
      {

                          ;
                                           ;
 return this->replace(__i1 - _M_ibegin(), __i2 - __i1,
        __k1, __k2 - __k1);
      }

      basic_string&
      replace(iterator __i1, iterator __i2, iterator __k1, iterator __k2)
      {

                          ;
                                           ;
 return this->replace(__i1 - _M_ibegin(), __i2 - __i1,
        __k1.base(), __k2 - __k1);
      }

      basic_string&
      replace(iterator __i1, iterator __i2,
       const_iterator __k1, const_iterator __k2)
      {

                          ;
                                           ;
 return this->replace(__i1 - _M_ibegin(), __i2 - __i1,
        __k1.base(), __k2 - __k1);
      }

    private:
      template<class _Integer>
 basic_string&
 _M_replace_dispatch(iterator __i1, iterator __i2, _Integer __n,
       _Integer __val, __true_type)
        { return _M_replace_aux(__i1 - _M_ibegin(), __i2 - __i1, __n, __val); }

      template<class _InputIterator>
 basic_string&
 _M_replace_dispatch(iterator __i1, iterator __i2, _InputIterator __k1,
       _InputIterator __k2, __false_type);

      basic_string&
      _M_replace_aux(size_type __pos1, size_type __n1, size_type __n2,
       _CharT __c);

      basic_string&
      _M_replace_safe(size_type __pos1, size_type __n1, const _CharT* __s,
        size_type __n2);



      template<class _InIterator>
        static _CharT*
        _S_construct_aux(_InIterator __beg, _InIterator __end,
    const _Alloc& __a, __false_type)
 {
          typedef typename iterator_traits<_InIterator>::iterator_category _Tag;
          return _S_construct(__beg, __end, __a, _Tag());
 }

      template<class _InIterator>
        static _CharT*
        _S_construct_aux(_InIterator __beg, _InIterator __end,
    const _Alloc& __a, __true_type)
 { return _S_construct(static_cast<size_type>(__beg),
         static_cast<value_type>(__end), __a); }

      template<class _InIterator>
        static _CharT*
        _S_construct(_InIterator __beg, _InIterator __end, const _Alloc& __a)
 {
   typedef typename std::__is_integer<_InIterator>::__type _Integral;
   return _S_construct_aux(__beg, __end, __a, _Integral());
        }


      template<class _InIterator>
        static _CharT*
         _S_construct(_InIterator __beg, _InIterator __end, const _Alloc& __a,
        input_iterator_tag);



      template<class _FwdIterator>
        static _CharT*
        _S_construct(_FwdIterator __beg, _FwdIterator __end, const _Alloc& __a,
       forward_iterator_tag);

      static _CharT*
      _S_construct(size_type __req, _CharT __c, const _Alloc& __a);

    public:
      size_type
      copy(_CharT* __s, size_type __n, size_type __pos = 0) const;
      void
      swap(basic_string& __s);
      const _CharT*
      c_str() const
      { return _M_data(); }







      const _CharT*
      data() const
      { return _M_data(); }




      allocator_type
      get_allocator() const
      { return _M_dataplus; }
      size_type
      find(const _CharT* __s, size_type __pos, size_type __n) const;
      size_type
      find(const basic_string& __str, size_type __pos = 0) const
      { return this->find(__str.data(), __pos, __str.size()); }
      size_type
      find(const _CharT* __s, size_type __pos = 0) const
      {
                               ;
 return this->find(__s, __pos, traits_type::length(__s));
      }
      size_type
      find(_CharT __c, size_type __pos = 0) const;
      size_type
      rfind(const basic_string& __str, size_type __pos = npos) const
      { return this->rfind(__str.data(), __pos, __str.size()); }
      size_type
      rfind(const _CharT* __s, size_type __pos, size_type __n) const;
      size_type
      rfind(const _CharT* __s, size_type __pos = npos) const
      {
                               ;
 return this->rfind(__s, __pos, traits_type::length(__s));
      }
      size_type
      rfind(_CharT __c, size_type __pos = npos) const;
      size_type
      find_first_of(const basic_string& __str, size_type __pos = 0) const
      { return this->find_first_of(__str.data(), __pos, __str.size()); }
      size_type
      find_first_of(const _CharT* __s, size_type __pos, size_type __n) const;
      size_type
      find_first_of(const _CharT* __s, size_type __pos = 0) const
      {
                               ;
 return this->find_first_of(__s, __pos, traits_type::length(__s));
      }
      size_type
      find_first_of(_CharT __c, size_type __pos = 0) const
      { return this->find(__c, __pos); }
      size_type
      find_last_of(const basic_string& __str, size_type __pos = npos) const
      { return this->find_last_of(__str.data(), __pos, __str.size()); }
      size_type
      find_last_of(const _CharT* __s, size_type __pos, size_type __n) const;
      size_type
      find_last_of(const _CharT* __s, size_type __pos = npos) const
      {
                               ;
 return this->find_last_of(__s, __pos, traits_type::length(__s));
      }
      size_type
      find_last_of(_CharT __c, size_type __pos = npos) const
      { return this->rfind(__c, __pos); }
      size_type
      find_first_not_of(const basic_string& __str, size_type __pos = 0) const
      { return this->find_first_not_of(__str.data(), __pos, __str.size()); }
      size_type
      find_first_not_of(const _CharT* __s, size_type __pos,
   size_type __n) const;
      size_type
      find_first_not_of(const _CharT* __s, size_type __pos = 0) const
      {
                               ;
 return this->find_first_not_of(__s, __pos, traits_type::length(__s));
      }
      size_type
      find_first_not_of(_CharT __c, size_type __pos = 0) const;
      size_type
      find_last_not_of(const basic_string& __str, size_type __pos = npos) const
      { return this->find_last_not_of(__str.data(), __pos, __str.size()); }
      size_type
      find_last_not_of(const _CharT* __s, size_type __pos,
         size_type __n) const;
      size_type
      find_last_not_of(const _CharT* __s, size_type __pos = npos) const
      {
                               ;
 return this->find_last_not_of(__s, __pos, traits_type::length(__s));
      }
      size_type
      find_last_not_of(_CharT __c, size_type __pos = npos) const;
      basic_string
      substr(size_type __pos = 0, size_type __n = npos) const
      { return basic_string(*this,
       _M_check(__pos, "basic_string::substr"), __n); }
      int
      compare(const basic_string& __str) const
      {
 const size_type __size = this->size();
 const size_type __osize = __str.size();
 const size_type __len = std::min(__size, __osize);

 int __r = traits_type::compare(_M_data(), __str.data(), __len);
 if (!__r)
   __r = __size - __osize;
 return __r;
      }
      int
      compare(size_type __pos, size_type __n, const basic_string& __str) const;
      int
      compare(size_type __pos1, size_type __n1, const basic_string& __str,
       size_type __pos2, size_type __n2) const;
      int
      compare(const _CharT* __s) const;
      int
      compare(size_type __pos, size_type __n1, const _CharT* __s) const;
      int
      compare(size_type __pos, size_type __n1, const _CharT* __s,
       size_type __n2) const;
  };

  template<typename _CharT, typename _Traits, typename _Alloc>
    inline basic_string<_CharT, _Traits, _Alloc>::
    basic_string()

    : _M_dataplus(_S_empty_rep()._M_refdata(), _Alloc()) { }
  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>
    operator+(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
       const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    {
      basic_string<_CharT, _Traits, _Alloc> __str(__lhs);
      __str.append(__rhs);
      return __str;
    }







  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT,_Traits,_Alloc>
    operator+(const _CharT* __lhs,
       const basic_string<_CharT,_Traits,_Alloc>& __rhs);







  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT,_Traits,_Alloc>
    operator+(_CharT __lhs, const basic_string<_CharT,_Traits,_Alloc>& __rhs);







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline basic_string<_CharT, _Traits, _Alloc>
    operator+(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
      const _CharT* __rhs)
    {
      basic_string<_CharT, _Traits, _Alloc> __str(__lhs);
      __str.append(__rhs);
      return __str;
    }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline basic_string<_CharT, _Traits, _Alloc>
    operator+(const basic_string<_CharT, _Traits, _Alloc>& __lhs, _CharT __rhs)
    {
      typedef basic_string<_CharT, _Traits, _Alloc> __string_type;
      typedef typename __string_type::size_type __size_type;
      __string_type __str(__lhs);
      __str.append(__size_type(1), __rhs);
      return __str;
    }
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator==(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __lhs.compare(__rhs) == 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator==(const _CharT* __lhs,
        const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __rhs.compare(__lhs) == 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator==(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const _CharT* __rhs)
    { return __lhs.compare(__rhs) == 0; }
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator!=(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __rhs.compare(__lhs) != 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator!=(const _CharT* __lhs,
        const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __rhs.compare(__lhs) != 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator!=(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const _CharT* __rhs)
    { return __lhs.compare(__rhs) != 0; }
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator<(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
       const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __lhs.compare(__rhs) < 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator<(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
       const _CharT* __rhs)
    { return __lhs.compare(__rhs) < 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator<(const _CharT* __lhs,
       const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __rhs.compare(__lhs) > 0; }
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator>(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
       const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __lhs.compare(__rhs) > 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator>(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
       const _CharT* __rhs)
    { return __lhs.compare(__rhs) > 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator>(const _CharT* __lhs,
       const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __rhs.compare(__lhs) < 0; }
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator<=(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __lhs.compare(__rhs) <= 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator<=(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const _CharT* __rhs)
    { return __lhs.compare(__rhs) <= 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator<=(const _CharT* __lhs,
        const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __rhs.compare(__lhs) >= 0; }
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator>=(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __lhs.compare(__rhs) >= 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator>=(const basic_string<_CharT, _Traits, _Alloc>& __lhs,
        const _CharT* __rhs)
    { return __lhs.compare(__rhs) >= 0; }







  template<typename _CharT, typename _Traits, typename _Alloc>
    inline bool
    operator>=(const _CharT* __lhs,
      const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { return __rhs.compare(__lhs) <= 0; }
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline void
    swap(basic_string<_CharT, _Traits, _Alloc>& __lhs,
  basic_string<_CharT, _Traits, _Alloc>& __rhs)
    { __lhs.swap(__rhs); }
  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_istream<_CharT, _Traits>&
    operator>>(basic_istream<_CharT, _Traits>& __is,
        basic_string<_CharT, _Traits, _Alloc>& __str);

  template<>
    basic_istream<char>&
    operator>>(basic_istream<char>& __is, basic_string<char>& __str);
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline basic_ostream<_CharT, _Traits>&
    operator<<(basic_ostream<_CharT, _Traits>& __os,
        const basic_string<_CharT, _Traits, _Alloc>& __str)
    {


      return __ostream_insert(__os, __str.data(), __str.size());
    }
  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_istream<_CharT, _Traits>&
    getline(basic_istream<_CharT, _Traits>& __is,
     basic_string<_CharT, _Traits, _Alloc>& __str, _CharT __delim);
  template<typename _CharT, typename _Traits, typename _Alloc>
    inline basic_istream<_CharT, _Traits>&
    getline(basic_istream<_CharT, _Traits>& __is,
     basic_string<_CharT, _Traits, _Alloc>& __str)
    { return getline(__is, __str, __is.widen('\n')); }

  template<>
    basic_istream<char>&
    getline(basic_istream<char>& __in, basic_string<char>& __str,
     char __delim);


  template<>
    basic_istream<wchar_t>&
    getline(basic_istream<wchar_t>& __in, basic_string<wchar_t>& __str,
     wchar_t __delim);


}






namespace std __attribute__ ((__visibility__ ("default"))) {




  template<typename _RandomAccessIterator, typename _Distance>
    bool
    __is_heap(_RandomAccessIterator __first, _Distance __n)
    {
      _Distance __parent = 0;
      for (_Distance __child = 1; __child < __n; ++__child)
 {
   if (__first[__parent] < __first[__child])
     return false;
   if ((__child & 1) == 0)
     ++__parent;
 }
      return true;
    }

  template<typename _RandomAccessIterator, typename _Distance,
           typename _StrictWeakOrdering>
    bool
    __is_heap(_RandomAccessIterator __first, _StrictWeakOrdering __comp,
       _Distance __n)
    {
      _Distance __parent = 0;
      for (_Distance __child = 1; __child < __n; ++__child)
 {
   if (__comp(__first[__parent], __first[__child]))
     return false;
   if ((__child & 1) == 0)
     ++__parent;
 }
      return true;
    }

  template<typename _RandomAccessIterator>
    bool
    __is_heap(_RandomAccessIterator __first, _RandomAccessIterator __last)
    { return std::__is_heap(__first, std::distance(__first, __last)); }

  template<typename _RandomAccessIterator, typename _StrictWeakOrdering>
    bool
    __is_heap(_RandomAccessIterator __first, _RandomAccessIterator __last,
     _StrictWeakOrdering __comp)
    { return std::__is_heap(__first, __comp, std::distance(__first, __last)); }



  template<typename _RandomAccessIterator, typename _Distance, typename _Tp>
    void
    __push_heap(_RandomAccessIterator __first,
  _Distance __holeIndex, _Distance __topIndex, _Tp __value)
    {
      _Distance __parent = (__holeIndex - 1) / 2;
      while (__holeIndex > __topIndex && *(__first + __parent) < __value)
 {
   *(__first + __holeIndex) = *(__first + __parent);
   __holeIndex = __parent;
   __parent = (__holeIndex - 1) / 2;
 }
      *(__first + __holeIndex) = __value;
    }
  template<typename _RandomAccessIterator>
    inline void
    push_heap(_RandomAccessIterator __first, _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
   _ValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
   _DistanceType;





                                                     ;


      std::__push_heap(__first, _DistanceType((__last - __first) - 1),
         _DistanceType(0), _ValueType(*(__last - 1)));
    }

  template<typename _RandomAccessIterator, typename _Distance, typename _Tp,
     typename _Compare>
    void
    __push_heap(_RandomAccessIterator __first, _Distance __holeIndex,
  _Distance __topIndex, _Tp __value, _Compare __comp)
    {
      _Distance __parent = (__holeIndex - 1) / 2;
      while (__holeIndex > __topIndex
      && __comp(*(__first + __parent), __value))
 {
   *(__first + __holeIndex) = *(__first + __parent);
   __holeIndex = __parent;
   __parent = (__holeIndex - 1) / 2;
 }
      *(__first + __holeIndex) = __value;
    }
  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    push_heap(_RandomAccessIterator __first, _RandomAccessIterator __last,
       _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
   _ValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
   _DistanceType;




                                                     ;
                                                               ;

      std::__push_heap(__first, _DistanceType((__last - __first) - 1),
         _DistanceType(0), _ValueType(*(__last - 1)), __comp);
    }

  template<typename _RandomAccessIterator, typename _Distance, typename _Tp>
    void
    __adjust_heap(_RandomAccessIterator __first, _Distance __holeIndex,
    _Distance __len, _Tp __value)
    {
      const _Distance __topIndex = __holeIndex;
      _Distance __secondChild = 2 * __holeIndex + 2;
      while (__secondChild < __len)
 {
   if (*(__first + __secondChild) < *(__first + (__secondChild - 1)))
     __secondChild--;
   *(__first + __holeIndex) = *(__first + __secondChild);
   __holeIndex = __secondChild;
   __secondChild = 2 * (__secondChild + 1);
 }
      if (__secondChild == __len)
 {
   *(__first + __holeIndex) = *(__first + (__secondChild - 1));
   __holeIndex = __secondChild - 1;
 }
      std::__push_heap(__first, __holeIndex, __topIndex, __value);
    }

  template<typename _RandomAccessIterator, typename _Tp>
    inline void
    __pop_heap(_RandomAccessIterator __first, _RandomAccessIterator __last,
        _RandomAccessIterator __result, _Tp __value)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _Distance;
      *__result = *__first;
      std::__adjust_heap(__first, _Distance(0), _Distance(__last - __first),
    __value);
    }
  template<typename _RandomAccessIterator>
    inline void
    pop_heap(_RandomAccessIterator __first, _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;





                                                     ;
                                              ;

      std::__pop_heap(__first, __last - 1, __last - 1,
        _ValueType(*(__last - 1)));
    }

  template<typename _RandomAccessIterator, typename _Distance,
    typename _Tp, typename _Compare>
    void
    __adjust_heap(_RandomAccessIterator __first, _Distance __holeIndex,
    _Distance __len, _Tp __value, _Compare __comp)
    {
      const _Distance __topIndex = __holeIndex;
      _Distance __secondChild = 2 * __holeIndex + 2;
      while (__secondChild < __len)
 {
   if (__comp(*(__first + __secondChild),
       *(__first + (__secondChild - 1))))
     __secondChild--;
   *(__first + __holeIndex) = *(__first + __secondChild);
   __holeIndex = __secondChild;
   __secondChild = 2 * (__secondChild + 1);
 }
      if (__secondChild == __len)
 {
   *(__first + __holeIndex) = *(__first + (__secondChild - 1));
   __holeIndex = __secondChild - 1;
 }
      std::__push_heap(__first, __holeIndex, __topIndex, __value, __comp);
    }

  template<typename _RandomAccessIterator, typename _Tp, typename _Compare>
    inline void
    __pop_heap(_RandomAccessIterator __first, _RandomAccessIterator __last,
        _RandomAccessIterator __result, _Tp __value, _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _Distance;
      *__result = *__first;
      std::__adjust_heap(__first, _Distance(0), _Distance(__last - __first),
    __value, __comp);
    }
  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    pop_heap(_RandomAccessIterator __first,
      _RandomAccessIterator __last, _Compare __comp)
    {



                                                     ;
                                                           ;

      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;
      std::__pop_heap(__first, __last - 1, __last - 1,
        _ValueType(*(__last - 1)), __comp);
    }
  template<typename _RandomAccessIterator>
    void
    make_heap(_RandomAccessIterator __first, _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
   _ValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
   _DistanceType;





                                                     ;

      if (__last - __first < 2)
 return;

      const _DistanceType __len = __last - __first;
      _DistanceType __parent = (__len - 2) / 2;
      while (true)
 {
   std::__adjust_heap(__first, __parent, __len,
        _ValueType(*(__first + __parent)));
   if (__parent == 0)
     return;
   __parent--;
 }
    }
  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    make_heap(_RandomAccessIterator __first, _RandomAccessIterator __last,
       _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
   _ValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
   _DistanceType;




                                                     ;

      if (__last - __first < 2)
 return;

      const _DistanceType __len = __last - __first;
      _DistanceType __parent = (__len - 2) / 2;
      while (true)
 {
   std::__adjust_heap(__first, __parent, __len,
        _ValueType(*(__first + __parent)), __comp);
   if (__parent == 0)
     return;
   __parent--;
 }
    }
  template<typename _RandomAccessIterator>
    void
    sort_heap(_RandomAccessIterator __first, _RandomAccessIterator __last)
    {





                                                     ;


      while (__last - __first > 1)
 std::pop_heap(__first, _RandomAccessIterator(__last--));
    }
  template<typename _RandomAccessIterator, typename _Compare>
    void
    sort_heap(_RandomAccessIterator __first, _RandomAccessIterator __last,
       _Compare __comp)
    {



                                                     ;
                                                           ;

      while (__last - __first > 1)
 std::pop_heap(__first, _RandomAccessIterator(__last--), __comp);
    }

}
namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _ForwardIterator, typename _Tp>
    class _Temporary_buffer
    {



    public:
      typedef _Tp value_type;
      typedef value_type* pointer;
      typedef pointer iterator;
      typedef ptrdiff_t size_type;

    protected:
      size_type _M_original_len;
      size_type _M_len;
      pointer _M_buffer;

      void
      _M_initialize_buffer(const _Tp&, __true_type) { }

      void
      _M_initialize_buffer(const _Tp& __val, __false_type)
      { std::uninitialized_fill_n(_M_buffer, _M_len, __val); }

    public:

      size_type
      size() const
      { return _M_len; }


      size_type
      requested_size() const
      { return _M_original_len; }


      iterator
      begin()
      { return _M_buffer; }


      iterator
      end()
      { return _M_buffer + _M_len; }





      _Temporary_buffer(_ForwardIterator __first, _ForwardIterator __last);

      ~_Temporary_buffer()
      {
 std::_Destroy(_M_buffer, _M_buffer + _M_len);
 std::return_temporary_buffer(_M_buffer);
      }

    private:

      _Temporary_buffer(const _Temporary_buffer&);

      void
      operator=(const _Temporary_buffer&);
    };


  template<typename _ForwardIterator, typename _Tp>
    _Temporary_buffer<_ForwardIterator, _Tp>::
    _Temporary_buffer(_ForwardIterator __first, _ForwardIterator __last)
    : _M_original_len(std::distance(__first, __last)),
      _M_len(0), _M_buffer(0)
    {

      typedef typename std::__is_scalar<_Tp>::__type _Trivial;

      if (true)
 {
   pair<pointer, size_type> __p(get_temporary_buffer<
           value_type>(_M_original_len));
   _M_buffer = __p.first;
   _M_len = __p.second;
   if (_M_len > 0)
     _M_initialize_buffer(*__first, _Trivial());
 }
      if (false)
 {
   std::return_temporary_buffer(_M_buffer);
   _M_buffer = 0;
   _M_len = 0;
                          ;
 }
    }

}




namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _Tp>
    inline const _Tp&
    __median(const _Tp& __a, const _Tp& __b, const _Tp& __c)
    {


      if (__a < __b)
 if (__b < __c)
   return __b;
 else if (__a < __c)
   return __c;
 else
   return __a;
      else if (__a < __c)
 return __a;
      else if (__b < __c)
 return __c;
      else
 return __b;
    }
  template<typename _Tp, typename _Compare>
    inline const _Tp&
    __median(const _Tp& __a, const _Tp& __b, const _Tp& __c, _Compare __comp)
    {


      if (__comp(__a, __b))
 if (__comp(__b, __c))
   return __b;
 else if (__comp(__a, __c))
   return __c;
 else
   return __a;
      else if (__comp(__a, __c))
 return __a;
      else if (__comp(__b, __c))
 return __c;
      else
 return __b;
    }
  template<typename _InputIterator, typename _Function>
    _Function
    for_each(_InputIterator __first, _InputIterator __last, _Function __f)
    {


                                                     ;
      for ( ; __first != __last; ++__first)
 __f(*__first);
      return __f;
    }






  template<typename _InputIterator, typename _Tp>
    inline _InputIterator
    __find(_InputIterator __first, _InputIterator __last,
    const _Tp& __val, input_iterator_tag)
    {
      while (__first != __last && !(*__first == __val))
 ++__first;
      return __first;
    }






  template<typename _InputIterator, typename _Predicate>
    inline _InputIterator
    __find_if(_InputIterator __first, _InputIterator __last,
       _Predicate __pred, input_iterator_tag)
    {
      while (__first != __last && !__pred(*__first))
 ++__first;
      return __first;
    }






  template<typename _RandomAccessIterator, typename _Tp>
    _RandomAccessIterator
    __find(_RandomAccessIterator __first, _RandomAccessIterator __last,
    const _Tp& __val, random_access_iterator_tag)
    {
      typename iterator_traits<_RandomAccessIterator>::difference_type
 __trip_count = (__last - __first) >> 2;

      for ( ; __trip_count > 0 ; --__trip_count)
 {
   if (*__first == __val)
     return __first;
   ++__first;

   if (*__first == __val)
     return __first;
   ++__first;

   if (*__first == __val)
     return __first;
   ++__first;

   if (*__first == __val)
     return __first;
   ++__first;
 }

      switch (__last - __first)
 {
 case 3:
   if (*__first == __val)
     return __first;
   ++__first;
 case 2:
   if (*__first == __val)
     return __first;
   ++__first;
 case 1:
   if (*__first == __val)
     return __first;
   ++__first;
 case 0:
 default:
   return __last;
 }
    }






  template<typename _RandomAccessIterator, typename _Predicate>
    _RandomAccessIterator
    __find_if(_RandomAccessIterator __first, _RandomAccessIterator __last,
       _Predicate __pred, random_access_iterator_tag)
    {
      typename iterator_traits<_RandomAccessIterator>::difference_type
 __trip_count = (__last - __first) >> 2;

      for ( ; __trip_count > 0 ; --__trip_count)
 {
   if (__pred(*__first))
     return __first;
   ++__first;

   if (__pred(*__first))
     return __first;
   ++__first;

   if (__pred(*__first))
     return __first;
   ++__first;

   if (__pred(*__first))
     return __first;
   ++__first;
 }

      switch (__last - __first)
 {
 case 3:
   if (__pred(*__first))
     return __first;
   ++__first;
 case 2:
   if (__pred(*__first))
     return __first;
   ++__first;
 case 1:
   if (__pred(*__first))
     return __first;
   ++__first;
 case 0:
 default:
   return __last;
 }
    }






  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
        istreambuf_iterator<_CharT> >::__type
    find(istreambuf_iterator<_CharT>, istreambuf_iterator<_CharT>,
  const _CharT&);
  template<typename _InputIterator, typename _Tp>
    inline _InputIterator
    find(_InputIterator __first, _InputIterator __last,
  const _Tp& __val)
    {




                                                     ;
      return std::__find(__first, __last, __val,
           std::__iterator_category(__first));
    }
  template<typename _InputIterator, typename _Predicate>
    inline _InputIterator
    find_if(_InputIterator __first, _InputIterator __last,
     _Predicate __pred)
    {




                                                     ;
      return std::__find_if(__first, __last, __pred,
       std::__iterator_category(__first));
    }
  template<typename _ForwardIterator>
    _ForwardIterator
    adjacent_find(_ForwardIterator __first, _ForwardIterator __last)
    {




                                                     ;
      if (__first == __last)
 return __last;
      _ForwardIterator __next = __first;
      while(++__next != __last)
 {
   if (*__first == *__next)
     return __first;
   __first = __next;
 }
      return __last;
    }
  template<typename _ForwardIterator, typename _BinaryPredicate>
    _ForwardIterator
    adjacent_find(_ForwardIterator __first, _ForwardIterator __last,
    _BinaryPredicate __binary_pred)
    {





                                                     ;
      if (__first == __last)
 return __last;
      _ForwardIterator __next = __first;
      while(++__next != __last)
 {
   if (__binary_pred(*__first, *__next))
     return __first;
   __first = __next;
 }
      return __last;
    }
  template<typename _InputIterator, typename _Tp>
    typename iterator_traits<_InputIterator>::difference_type
    count(_InputIterator __first, _InputIterator __last, const _Tp& __value)
    {




                                                     ;
      typename iterator_traits<_InputIterator>::difference_type __n = 0;
      for ( ; __first != __last; ++__first)
 if (*__first == __value)
   ++__n;
      return __n;
    }
  template<typename _InputIterator, typename _Predicate>
    typename iterator_traits<_InputIterator>::difference_type
    count_if(_InputIterator __first, _InputIterator __last, _Predicate __pred)
    {




                                                     ;
      typename iterator_traits<_InputIterator>::difference_type __n = 0;
      for ( ; __first != __last; ++__first)
 if (__pred(*__first))
   ++__n;
      return __n;
    }
  template<typename _ForwardIterator1, typename _ForwardIterator2>
    _ForwardIterator1
    search(_ForwardIterator1 __first1, _ForwardIterator1 __last1,
    _ForwardIterator2 __first2, _ForwardIterator2 __last2)
    {






                                                       ;
                                                       ;

      if (__first1 == __last1 || __first2 == __last2)
 return __first1;


      _ForwardIterator2 __tmp(__first2);
      ++__tmp;
      if (__tmp == __last2)
 return std::find(__first1, __last1, *__first2);


      _ForwardIterator2 __p1, __p;
      __p1 = __first2; ++__p1;
      _ForwardIterator1 __current = __first1;

      while (__first1 != __last1)
 {
   __first1 = std::find(__first1, __last1, *__first2);
   if (__first1 == __last1)
     return __last1;

   __p = __p1;
   __current = __first1;
   if (++__current == __last1)
     return __last1;

   while (*__current == *__p)
     {
       if (++__p == __last2)
  return __first1;
       if (++__current == __last1)
  return __last1;
     }
   ++__first1;
 }
      return __first1;
    }
  template<typename _ForwardIterator1, typename _ForwardIterator2,
    typename _BinaryPredicate>
    _ForwardIterator1
    search(_ForwardIterator1 __first1, _ForwardIterator1 __last1,
    _ForwardIterator2 __first2, _ForwardIterator2 __last2,
    _BinaryPredicate __predicate)
    {






                                                       ;
                                                       ;


      if (__first1 == __last1 || __first2 == __last2)
 return __first1;


      _ForwardIterator2 __tmp(__first2);
      ++__tmp;
      if (__tmp == __last2)
 {
   while (__first1 != __last1 && !__predicate(*__first1, *__first2))
     ++__first1;
   return __first1;
 }


      _ForwardIterator2 __p1, __p;
      __p1 = __first2; ++__p1;
      _ForwardIterator1 __current = __first1;

      while (__first1 != __last1)
 {
   while (__first1 != __last1)
     {
       if (__predicate(*__first1, *__first2))
  break;
       ++__first1;
     }
   while (__first1 != __last1 && !__predicate(*__first1, *__first2))
     ++__first1;
   if (__first1 == __last1)
     return __last1;

   __p = __p1;
   __current = __first1;
   if (++__current == __last1)
     return __last1;

   while (__predicate(*__current, *__p))
     {
       if (++__p == __last2)
  return __first1;
       if (++__current == __last1)
  return __last1;
     }
   ++__first1;
 }
      return __first1;
    }
  template<typename _ForwardIterator, typename _Integer, typename _Tp>
    _ForwardIterator
    __search_n(_ForwardIterator __first, _ForwardIterator __last,
        _Integer __count, const _Tp& __val,
        std::forward_iterator_tag)
    {
      __first = std::find(__first, __last, __val);
      while (__first != __last)
 {
   typename iterator_traits<_ForwardIterator>::difference_type
     __n = __count;
   _ForwardIterator __i = __first;
   ++__i;
   while (__i != __last && __n != 1 && *__i == __val)
     {
       ++__i;
       --__n;
     }
   if (__n == 1)
     return __first;
   if (__i == __last)
     return __last;
   __first = std::find(++__i, __last, __val);
 }
      return __last;
    }
  template<typename _RandomAccessIter, typename _Integer, typename _Tp>
    _RandomAccessIter
    __search_n(_RandomAccessIter __first, _RandomAccessIter __last,
        _Integer __count, const _Tp& __val,
        std::random_access_iterator_tag)
    {

      typedef typename std::iterator_traits<_RandomAccessIter>::difference_type
 _DistanceType;

      _DistanceType __tailSize = __last - __first;
      const _DistanceType __pattSize = __count;

      if (__tailSize < __pattSize)
        return __last;

      const _DistanceType __skipOffset = __pattSize - 1;
      _RandomAccessIter __lookAhead = __first + __skipOffset;
      __tailSize -= __pattSize;

      while (1)
 {


   while (!(*__lookAhead == __val))
     {
       if (__tailSize < __pattSize)
  return __last;
       __lookAhead += __pattSize;
       __tailSize -= __pattSize;
     }
   _DistanceType __remainder = __skipOffset;
   for (_RandomAccessIter __backTrack = __lookAhead - 1;
        *__backTrack == __val; --__backTrack)
     {
       if (--__remainder == 0)
  return (__lookAhead - __skipOffset);
     }
   if (__remainder > __tailSize)
     return __last;
   __lookAhead += __remainder;
   __tailSize -= __remainder;
 }
    }
  template<typename _ForwardIterator, typename _Integer, typename _Tp>
    _ForwardIterator
    search_n(_ForwardIterator __first, _ForwardIterator __last,
      _Integer __count, const _Tp& __val)
    {




                                                     ;

      if (__count <= 0)
 return __first;
      if (__count == 1)
 return std::find(__first, __last, __val);
      return std::__search_n(__first, __last, __count, __val,
        std::__iterator_category(__first));
    }
  template<typename _ForwardIterator, typename _Integer, typename _Tp,
           typename _BinaryPredicate>
    _ForwardIterator
    __search_n(_ForwardIterator __first, _ForwardIterator __last,
        _Integer __count, const _Tp& __val,
        _BinaryPredicate __binary_pred, std::forward_iterator_tag)
    {
      while (__first != __last && !__binary_pred(*__first, __val))
        ++__first;

      while (__first != __last)
 {
   typename iterator_traits<_ForwardIterator>::difference_type
     __n = __count;
   _ForwardIterator __i = __first;
   ++__i;
   while (__i != __last && __n != 1 && __binary_pred(*__i, __val))
     {
       ++__i;
       --__n;
     }
   if (__n == 1)
     return __first;
   if (__i == __last)
     return __last;
   __first = ++__i;
   while (__first != __last && !__binary_pred(*__first, __val))
     ++__first;
 }
      return __last;
    }
  template<typename _RandomAccessIter, typename _Integer, typename _Tp,
    typename _BinaryPredicate>
    _RandomAccessIter
    __search_n(_RandomAccessIter __first, _RandomAccessIter __last,
        _Integer __count, const _Tp& __val,
        _BinaryPredicate __binary_pred, std::random_access_iterator_tag)
    {

      typedef typename std::iterator_traits<_RandomAccessIter>::difference_type
 _DistanceType;

      _DistanceType __tailSize = __last - __first;
      const _DistanceType __pattSize = __count;

      if (__tailSize < __pattSize)
        return __last;

      const _DistanceType __skipOffset = __pattSize - 1;
      _RandomAccessIter __lookAhead = __first + __skipOffset;
      __tailSize -= __pattSize;

      while (1)
 {


   while (!__binary_pred(*__lookAhead, __val))
     {
       if (__tailSize < __pattSize)
  return __last;
       __lookAhead += __pattSize;
       __tailSize -= __pattSize;
     }
   _DistanceType __remainder = __skipOffset;
   for (_RandomAccessIter __backTrack = __lookAhead - 1;
        __binary_pred(*__backTrack, __val); --__backTrack)
     {
       if (--__remainder == 0)
  return (__lookAhead - __skipOffset);
     }
   if (__remainder > __tailSize)
     return __last;
   __lookAhead += __remainder;
   __tailSize -= __remainder;
 }
    }
  template<typename _ForwardIterator, typename _Integer, typename _Tp,
           typename _BinaryPredicate>
    _ForwardIterator
    search_n(_ForwardIterator __first, _ForwardIterator __last,
      _Integer __count, const _Tp& __val,
      _BinaryPredicate __binary_pred)
    {




                                                     ;

      if (__count <= 0)
 return __first;
      if (__count == 1)
 {
   while (__first != __last && !__binary_pred(*__first, __val))
     ++__first;
   return __first;
 }
      return std::__search_n(__first, __last, __count, __val, __binary_pred,
        std::__iterator_category(__first));
    }
  template<typename _ForwardIterator1, typename _ForwardIterator2>
    _ForwardIterator2
    swap_ranges(_ForwardIterator1 __first1, _ForwardIterator1 __last1,
  _ForwardIterator2 __first2)
    {
                                                       ;

      for ( ; __first1 != __last1; ++__first1, ++__first2)
 std::iter_swap(__first1, __first2);
      return __first2;
    }
  template<typename _InputIterator, typename _OutputIterator,
    typename _UnaryOperation>
    _OutputIterator
    transform(_InputIterator __first, _InputIterator __last,
       _OutputIterator __result, _UnaryOperation __unary_op)
    {





                                                     ;

      for ( ; __first != __last; ++__first, ++__result)
 *__result = __unary_op(*__first);
      return __result;
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator, typename _BinaryOperation>
    _OutputIterator
    transform(_InputIterator1 __first1, _InputIterator1 __last1,
       _InputIterator2 __first2, _OutputIterator __result,
       _BinaryOperation __binary_op)
    {






                                                       ;

      for ( ; __first1 != __last1; ++__first1, ++__first2, ++__result)
 *__result = __binary_op(*__first1, *__first2);
      return __result;
    }
  template<typename _ForwardIterator, typename _Tp>
    void
    replace(_ForwardIterator __first, _ForwardIterator __last,
     const _Tp& __old_value, const _Tp& __new_value)
    {







                                                     ;

      for ( ; __first != __last; ++__first)
 if (*__first == __old_value)
   *__first = __new_value;
    }
  template<typename _ForwardIterator, typename _Predicate, typename _Tp>
    void
    replace_if(_ForwardIterator __first, _ForwardIterator __last,
        _Predicate __pred, const _Tp& __new_value)
    {







                                                     ;

      for ( ; __first != __last; ++__first)
 if (__pred(*__first))
   *__first = __new_value;
    }
  template<typename _InputIterator, typename _OutputIterator, typename _Tp>
    _OutputIterator
    replace_copy(_InputIterator __first, _InputIterator __last,
   _OutputIterator __result,
   const _Tp& __old_value, const _Tp& __new_value)
    {






                                                     ;

      for ( ; __first != __last; ++__first, ++__result)
 if (*__first == __old_value)
   *__result = __new_value;
 else
   *__result = *__first;
      return __result;
    }
  template<typename _InputIterator, typename _OutputIterator,
    typename _Predicate, typename _Tp>
    _OutputIterator
    replace_copy_if(_InputIterator __first, _InputIterator __last,
      _OutputIterator __result,
      _Predicate __pred, const _Tp& __new_value)
    {






                                                     ;

      for ( ; __first != __last; ++__first, ++__result)
 if (__pred(*__first))
   *__result = __new_value;
 else
   *__result = *__first;
      return __result;
    }
  template<typename _ForwardIterator, typename _Generator>
    void
    generate(_ForwardIterator __first, _ForwardIterator __last,
      _Generator __gen)
    {




                                                     ;

      for ( ; __first != __last; ++__first)
 *__first = __gen();
    }
  template<typename _OutputIterator, typename _Size, typename _Generator>
    _OutputIterator
    generate_n(_OutputIterator __first, _Size __n, _Generator __gen)
    {





      for ( ; __n > 0; --__n, ++__first)
 *__first = __gen();
      return __first;
    }
  template<typename _InputIterator, typename _OutputIterator, typename _Tp>
    _OutputIterator
    remove_copy(_InputIterator __first, _InputIterator __last,
  _OutputIterator __result, const _Tp& __value)
    {






                                                     ;

      for ( ; __first != __last; ++__first)
 if (!(*__first == __value))
   {
     *__result = *__first;
     ++__result;
   }
      return __result;
    }
  template<typename _InputIterator, typename _OutputIterator,
    typename _Predicate>
    _OutputIterator
    remove_copy_if(_InputIterator __first, _InputIterator __last,
     _OutputIterator __result, _Predicate __pred)
    {






                                                     ;

      for ( ; __first != __last; ++__first)
 if (!__pred(*__first))
   {
     *__result = *__first;
     ++__result;
   }
      return __result;
    }
  template<typename _ForwardIterator, typename _Tp>
    _ForwardIterator
    remove(_ForwardIterator __first, _ForwardIterator __last,
    const _Tp& __value)
    {





                                                     ;

      __first = std::find(__first, __last, __value);
      _ForwardIterator __i = __first;
      return __first == __last ? __first
          : std::remove_copy(++__i, __last,
        __first, __value);
    }
  template<typename _ForwardIterator, typename _Predicate>
    _ForwardIterator
    remove_if(_ForwardIterator __first, _ForwardIterator __last,
       _Predicate __pred)
    {





                                                     ;

      __first = std::find_if(__first, __last, __pred);
      _ForwardIterator __i = __first;
      return __first == __last ? __first
          : std::remove_copy_if(++__i, __last,
           __first, __pred);
    }
  template<typename _ForwardIterator, typename _OutputIterator>
    _OutputIterator
    __unique_copy(_ForwardIterator __first, _ForwardIterator __last,
    _OutputIterator __result,
    forward_iterator_tag, output_iterator_tag)
    {

      _ForwardIterator __next = __first;
      *__result = *__first;
      while (++__next != __last)
 if (!(*__first == *__next))
   {
     __first = __next;
     *++__result = *__first;
   }
      return ++__result;
    }
  template<typename _InputIterator, typename _OutputIterator>
    _OutputIterator
    __unique_copy(_InputIterator __first, _InputIterator __last,
    _OutputIterator __result,
    input_iterator_tag, output_iterator_tag)
    {

      typename iterator_traits<_InputIterator>::value_type __value = *__first;
      *__result = __value;
      while (++__first != __last)
 if (!(__value == *__first))
   {
     __value = *__first;
     *++__result = __value;
   }
      return ++__result;
    }
  template<typename _InputIterator, typename _ForwardIterator>
    _ForwardIterator
    __unique_copy(_InputIterator __first, _InputIterator __last,
    _ForwardIterator __result,
    input_iterator_tag, forward_iterator_tag)
    {

      *__result = *__first;
      while (++__first != __last)
 if (!(*__result == *__first))
   *++__result = *__first;
      return ++__result;
    }
  template<typename _ForwardIterator, typename _OutputIterator,
    typename _BinaryPredicate>
    _OutputIterator
    __unique_copy(_ForwardIterator __first, _ForwardIterator __last,
    _OutputIterator __result, _BinaryPredicate __binary_pred,
    forward_iterator_tag, output_iterator_tag)
    {





      _ForwardIterator __next = __first;
      *__result = *__first;
      while (++__next != __last)
 if (!__binary_pred(*__first, *__next))
   {
     __first = __next;
     *++__result = *__first;
   }
      return ++__result;
    }
  template<typename _InputIterator, typename _OutputIterator,
    typename _BinaryPredicate>
    _OutputIterator
    __unique_copy(_InputIterator __first, _InputIterator __last,
    _OutputIterator __result, _BinaryPredicate __binary_pred,
    input_iterator_tag, output_iterator_tag)
    {





      typename iterator_traits<_InputIterator>::value_type __value = *__first;
      *__result = __value;
      while (++__first != __last)
 if (!__binary_pred(__value, *__first))
   {
     __value = *__first;
     *++__result = __value;
   }
      return ++__result;
    }
  template<typename _InputIterator, typename _ForwardIterator,
    typename _BinaryPredicate>
    _ForwardIterator
    __unique_copy(_InputIterator __first, _InputIterator __last,
    _ForwardIterator __result, _BinaryPredicate __binary_pred,
    input_iterator_tag, forward_iterator_tag)
    {





      *__result = *__first;
      while (++__first != __last)
 if (!__binary_pred(*__result, *__first))
   *++__result = *__first;
      return ++__result;
    }
  template<typename _InputIterator, typename _OutputIterator>
    inline _OutputIterator
    unique_copy(_InputIterator __first, _InputIterator __last,
  _OutputIterator __result)
    {






                                                     ;

      if (__first == __last)
 return __result;
      return std::__unique_copy(__first, __last, __result,
    std::__iterator_category(__first),
    std::__iterator_category(__result));
    }
  template<typename _InputIterator, typename _OutputIterator,
    typename _BinaryPredicate>
    inline _OutputIterator
    unique_copy(_InputIterator __first, _InputIterator __last,
  _OutputIterator __result,
  _BinaryPredicate __binary_pred)
    {




                                                     ;

      if (__first == __last)
 return __result;
      return std::__unique_copy(__first, __last, __result, __binary_pred,
    std::__iterator_category(__first),
    std::__iterator_category(__result));
    }
  template<typename _ForwardIterator>
    _ForwardIterator
    unique(_ForwardIterator __first, _ForwardIterator __last)
    {





                                                     ;


      __first = std::adjacent_find(__first, __last);
      if (__first == __last)
 return __last;


      _ForwardIterator __dest = __first;
      ++__first;
      while (++__first != __last)
 if (!(*__dest == *__first))
   *++__dest = *__first;
      return ++__dest;
    }
  template<typename _ForwardIterator, typename _BinaryPredicate>
    _ForwardIterator
    unique(_ForwardIterator __first, _ForwardIterator __last,
           _BinaryPredicate __binary_pred)
    {






                                                     ;


      __first = std::adjacent_find(__first, __last, __binary_pred);
      if (__first == __last)
 return __last;


      _ForwardIterator __dest = __first;
      ++__first;
      while (++__first != __last)
 if (!__binary_pred(*__dest, *__first))
   *++__dest = *__first;
      return ++__dest;
    }
  template<typename _BidirectionalIterator>
    void
    __reverse(_BidirectionalIterator __first, _BidirectionalIterator __last,
       bidirectional_iterator_tag)
    {
      while (true)
 if (__first == __last || __first == --__last)
   return;
 else
   {
     std::iter_swap(__first, __last);
     ++__first;
   }
    }
  template<typename _RandomAccessIterator>
    void
    __reverse(_RandomAccessIterator __first, _RandomAccessIterator __last,
       random_access_iterator_tag)
    {
      if (__first == __last)
 return;
      --__last;
      while (__first < __last)
 {
   std::iter_swap(__first, __last);
   ++__first;
   --__last;
 }
    }
  template<typename _BidirectionalIterator>
    inline void
    reverse(_BidirectionalIterator __first, _BidirectionalIterator __last)
    {



                                                     ;
      std::__reverse(__first, __last, std::__iterator_category(__first));
    }
  template<typename _BidirectionalIterator, typename _OutputIterator>
    _OutputIterator
    reverse_copy(_BidirectionalIterator __first, _BidirectionalIterator __last,
        _OutputIterator __result)
    {





                                                     ;

      while (__first != __last)
 {
   --__last;
   *__result = *__last;
   ++__result;
 }
      return __result;
    }
  template<typename _EuclideanRingElement>
    _EuclideanRingElement
    __gcd(_EuclideanRingElement __m, _EuclideanRingElement __n)
    {
      while (__n != 0)
 {
   _EuclideanRingElement __t = __m % __n;
   __m = __n;
   __n = __t;
 }
      return __m;
    }






  template<typename _ForwardIterator>
    void
    __rotate(_ForwardIterator __first,
      _ForwardIterator __middle,
      _ForwardIterator __last,
      forward_iterator_tag)
    {
      if (__first == __middle || __last == __middle)
 return;

      _ForwardIterator __first2 = __middle;
      do
 {
   swap(*__first, *__first2);
   ++__first;
   ++__first2;
   if (__first == __middle)
     __middle = __first2;
 }
      while (__first2 != __last);

      __first2 = __middle;

      while (__first2 != __last)
 {
   swap(*__first, *__first2);
   ++__first;
   ++__first2;
   if (__first == __middle)
     __middle = __first2;
   else if (__first2 == __last)
     __first2 = __middle;
 }
    }






  template<typename _BidirectionalIterator>
    void
    __rotate(_BidirectionalIterator __first,
      _BidirectionalIterator __middle,
      _BidirectionalIterator __last,
       bidirectional_iterator_tag)
    {




      if (__first == __middle || __last == __middle)
 return;

      std::__reverse(__first, __middle, bidirectional_iterator_tag());
      std::__reverse(__middle, __last, bidirectional_iterator_tag());

      while (__first != __middle && __middle != __last)
 {
   swap(*__first, *--__last);
   ++__first;
 }

      if (__first == __middle)
 std::__reverse(__middle, __last, bidirectional_iterator_tag());
      else
 std::__reverse(__first, __middle, bidirectional_iterator_tag());
    }






  template<typename _RandomAccessIterator>
    void
    __rotate(_RandomAccessIterator __first,
      _RandomAccessIterator __middle,
      _RandomAccessIterator __last,
      random_access_iterator_tag)
    {




      if (__first == __middle || __last == __middle)
 return;

      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _Distance;
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      const _Distance __n = __last - __first;
      const _Distance __k = __middle - __first;
      const _Distance __l = __n - __k;

      if (__k == __l)
 {
   std::swap_ranges(__first, __middle, __middle);
   return;
 }

      const _Distance __d = __gcd(__n, __k);

      for (_Distance __i = 0; __i < __d; __i++)
 {
   _ValueType __tmp = *__first;
   _RandomAccessIterator __p = __first;

   if (__k < __l)
     {
       for (_Distance __j = 0; __j < __l / __d; __j++)
  {
    if (__p > __first + __l)
      {
        *__p = *(__p - __l);
        __p -= __l;
      }

    *__p = *(__p + __k);
    __p += __k;
  }
     }
   else
     {
       for (_Distance __j = 0; __j < __k / __d - 1; __j ++)
  {
    if (__p < __last - __k)
      {
        *__p = *(__p + __k);
        __p += __k;
      }
    *__p = * (__p - __l);
    __p -= __l;
  }
     }

   *__p = __tmp;
   ++__first;
 }
    }
  template<typename _ForwardIterator>
    inline void
    rotate(_ForwardIterator __first, _ForwardIterator __middle,
    _ForwardIterator __last)
    {



                                                       ;
                                                      ;

      typedef typename iterator_traits<_ForwardIterator>::iterator_category
 _IterType;
      std::__rotate(__first, __middle, __last, _IterType());
    }
  template<typename _ForwardIterator, typename _OutputIterator>
    _OutputIterator
    rotate_copy(_ForwardIterator __first, _ForwardIterator __middle,
                _ForwardIterator __last, _OutputIterator __result)
    {




                                                       ;
                                                      ;

      return std::copy(__first, __middle,
                       std::copy(__middle, __last, __result));
    }
  template<typename _RandomAccessIterator>
    inline void
    random_shuffle(_RandomAccessIterator __first, _RandomAccessIterator __last)
    {



                                                     ;

      if (__first != __last)
 for (_RandomAccessIterator __i = __first + 1; __i != __last; ++__i)
   std::iter_swap(__i, __first + (std::rand() % ((__i - __first) + 1)));
    }
  template<typename _RandomAccessIterator, typename _RandomNumberGenerator>
    void
    random_shuffle(_RandomAccessIterator __first, _RandomAccessIterator __last,
     _RandomNumberGenerator& __rand)
    {



                                                     ;

      if (__first == __last)
 return;
      for (_RandomAccessIterator __i = __first + 1; __i != __last; ++__i)
 std::iter_swap(__i, __first + __rand((__i - __first) + 1));
    }







  template<typename _ForwardIterator, typename _Predicate>
    _ForwardIterator
    __partition(_ForwardIterator __first, _ForwardIterator __last,
  _Predicate __pred,
  forward_iterator_tag)
    {
      if (__first == __last)
 return __first;

      while (__pred(*__first))
 if (++__first == __last)
   return __first;

      _ForwardIterator __next = __first;

      while (++__next != __last)
 if (__pred(*__next))
   {
     swap(*__first, *__next);
     ++__first;
   }

      return __first;
    }






  template<typename _BidirectionalIterator, typename _Predicate>
    _BidirectionalIterator
    __partition(_BidirectionalIterator __first, _BidirectionalIterator __last,
  _Predicate __pred,
  bidirectional_iterator_tag)
    {
      while (true)
 {
   while (true)
     if (__first == __last)
       return __first;
     else if (__pred(*__first))
       ++__first;
     else
       break;
   --__last;
   while (true)
     if (__first == __last)
       return __first;
     else if (!__pred(*__last))
       --__last;
     else
       break;
   std::iter_swap(__first, __last);
   ++__first;
 }
    }
  template<typename _ForwardIterator, typename _Predicate>
    inline _ForwardIterator
    partition(_ForwardIterator __first, _ForwardIterator __last,
       _Predicate __pred)
    {





                                                     ;

      return std::__partition(__first, __last, __pred,
         std::__iterator_category(__first));
    }







  template<typename _ForwardIterator, typename _Predicate, typename _Distance>
    _ForwardIterator
    __inplace_stable_partition(_ForwardIterator __first,
          _ForwardIterator __last,
          _Predicate __pred, _Distance __len)
    {
      if (__len == 1)
 return __pred(*__first) ? __last : __first;
      _ForwardIterator __middle = __first;
      std::advance(__middle, __len / 2);
      _ForwardIterator __begin = std::__inplace_stable_partition(__first,
         __middle,
         __pred,
         __len / 2);
      _ForwardIterator __end = std::__inplace_stable_partition(__middle, __last,
              __pred,
              __len
              - __len / 2);
      std::rotate(__begin, __middle, __end);
      std::advance(__begin, std::distance(__middle, __end));
      return __begin;
    }






  template<typename _ForwardIterator, typename _Pointer, typename _Predicate,
    typename _Distance>
    _ForwardIterator
    __stable_partition_adaptive(_ForwardIterator __first,
    _ForwardIterator __last,
    _Predicate __pred, _Distance __len,
    _Pointer __buffer,
    _Distance __buffer_size)
    {
      if (__len <= __buffer_size)
 {
   _ForwardIterator __result1 = __first;
   _Pointer __result2 = __buffer;
   for ( ; __first != __last ; ++__first)
     if (__pred(*__first))
       {
  *__result1 = *__first;
  ++__result1;
       }
     else
       {
  *__result2 = *__first;
  ++__result2;
       }
   std::copy(__buffer, __result2, __result1);
   return __result1;
 }
      else
 {
   _ForwardIterator __middle = __first;
   std::advance(__middle, __len / 2);
   _ForwardIterator __begin =
     std::__stable_partition_adaptive(__first, __middle, __pred,
          __len / 2, __buffer,
          __buffer_size);
   _ForwardIterator __end =
     std::__stable_partition_adaptive(__middle, __last, __pred,
          __len - __len / 2,
          __buffer, __buffer_size);
   std::rotate(__begin, __middle, __end);
   std::advance(__begin, std::distance(__middle, __end));
   return __begin;
 }
    }
  template<typename _ForwardIterator, typename _Predicate>
    _ForwardIterator
    stable_partition(_ForwardIterator __first, _ForwardIterator __last,
       _Predicate __pred)
    {





                                                     ;

      if (__first == __last)
 return __first;
      else
 {
   typedef typename iterator_traits<_ForwardIterator>::value_type
     _ValueType;
   typedef typename iterator_traits<_ForwardIterator>::difference_type
     _DistanceType;

   _Temporary_buffer<_ForwardIterator, _ValueType> __buf(__first,
        __last);
 if (__buf.size() > 0)
   return
     std::__stable_partition_adaptive(__first, __last, __pred,
       _DistanceType(__buf.requested_size()),
       __buf.begin(), __buf.size());
 else
   return
     std::__inplace_stable_partition(__first, __last, __pred,
      _DistanceType(__buf.requested_size()));
 }
    }






  template<typename _RandomAccessIterator, typename _Tp>
    _RandomAccessIterator
    __unguarded_partition(_RandomAccessIterator __first,
     _RandomAccessIterator __last, _Tp __pivot)
    {
      while (true)
 {
   while (*__first < __pivot)
     ++__first;
   --__last;
   while (__pivot < *__last)
     --__last;
   if (!(__first < __last))
     return __first;
   std::iter_swap(__first, __last);
   ++__first;
 }
    }






  template<typename _RandomAccessIterator, typename _Tp, typename _Compare>
    _RandomAccessIterator
    __unguarded_partition(_RandomAccessIterator __first,
     _RandomAccessIterator __last,
     _Tp __pivot, _Compare __comp)
    {
      while (true)
 {
   while (__comp(*__first, __pivot))
     ++__first;
   --__last;
   while (__comp(__pivot, *__last))
     --__last;
   if (!(__first < __last))
     return __first;
   std::iter_swap(__first, __last);
   ++__first;
 }
    }







  enum { _S_threshold = 16 };






  template<typename _RandomAccessIterator, typename _Tp>
    void
    __unguarded_linear_insert(_RandomAccessIterator __last, _Tp __val)
    {
      _RandomAccessIterator __next = __last;
      --__next;
      while (__val < *__next)
 {
   *__last = *__next;
   __last = __next;
   --__next;
 }
      *__last = __val;
    }






  template<typename _RandomAccessIterator, typename _Tp, typename _Compare>
    void
    __unguarded_linear_insert(_RandomAccessIterator __last, _Tp __val,
         _Compare __comp)
    {
      _RandomAccessIterator __next = __last;
      --__next;
      while (__comp(__val, *__next))
 {
   *__last = *__next;
   __last = __next;
   --__next;
 }
      *__last = __val;
    }






  template<typename _RandomAccessIterator>
    void
    __insertion_sort(_RandomAccessIterator __first,
       _RandomAccessIterator __last)
    {
      if (__first == __last)
 return;

      for (_RandomAccessIterator __i = __first + 1; __i != __last; ++__i)
 {
   typename iterator_traits<_RandomAccessIterator>::value_type
     __val = *__i;
   if (__val < *__first)
     {
       std::copy_backward(__first, __i, __i + 1);
       *__first = __val;
     }
   else
     std::__unguarded_linear_insert(__i, __val);
 }
    }






  template<typename _RandomAccessIterator, typename _Compare>
    void
    __insertion_sort(_RandomAccessIterator __first,
       _RandomAccessIterator __last, _Compare __comp)
    {
      if (__first == __last) return;

      for (_RandomAccessIterator __i = __first + 1; __i != __last; ++__i)
 {
   typename iterator_traits<_RandomAccessIterator>::value_type
     __val = *__i;
   if (__comp(__val, *__first))
     {
       std::copy_backward(__first, __i, __i + 1);
       *__first = __val;
     }
   else
     std::__unguarded_linear_insert(__i, __val, __comp);
 }
    }






  template<typename _RandomAccessIterator>
    inline void
    __unguarded_insertion_sort(_RandomAccessIterator __first,
          _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      for (_RandomAccessIterator __i = __first; __i != __last; ++__i)
 std::__unguarded_linear_insert(__i, _ValueType(*__i));
    }






  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    __unguarded_insertion_sort(_RandomAccessIterator __first,
          _RandomAccessIterator __last, _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      for (_RandomAccessIterator __i = __first; __i != __last; ++__i)
 std::__unguarded_linear_insert(__i, _ValueType(*__i), __comp);
    }






  template<typename _RandomAccessIterator>
    void
    __final_insertion_sort(_RandomAccessIterator __first,
      _RandomAccessIterator __last)
    {
      if (__last - __first > int(_S_threshold))
 {
   std::__insertion_sort(__first, __first + int(_S_threshold));
   std::__unguarded_insertion_sort(__first + int(_S_threshold), __last);
 }
      else
 std::__insertion_sort(__first, __last);
    }






  template<typename _RandomAccessIterator, typename _Compare>
    void
    __final_insertion_sort(_RandomAccessIterator __first,
      _RandomAccessIterator __last, _Compare __comp)
    {
      if (__last - __first > int(_S_threshold))
 {
   std::__insertion_sort(__first, __first + int(_S_threshold), __comp);
   std::__unguarded_insertion_sort(__first + int(_S_threshold), __last,
       __comp);
 }
      else
 std::__insertion_sort(__first, __last, __comp);
    }






  template<typename _RandomAccessIterator>
    void
    __heap_select(_RandomAccessIterator __first,
    _RandomAccessIterator __middle,
    _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      std::make_heap(__first, __middle);
      for (_RandomAccessIterator __i = __middle; __i < __last; ++__i)
 if (*__i < *__first)
   std::__pop_heap(__first, __middle, __i, _ValueType(*__i));
    }






  template<typename _RandomAccessIterator, typename _Compare>
    void
    __heap_select(_RandomAccessIterator __first,
    _RandomAccessIterator __middle,
    _RandomAccessIterator __last, _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      std::make_heap(__first, __middle, __comp);
      for (_RandomAccessIterator __i = __middle; __i < __last; ++__i)
 if (__comp(*__i, *__first))
   std::__pop_heap(__first, __middle, __i, _ValueType(*__i), __comp);
    }






  template<typename _Size>
    inline _Size
    __lg(_Size __n)
    {
      _Size __k;
      for (__k = 0; __n != 1; __n >>= 1)
 ++__k;
      return __k;
    }
  template<typename _RandomAccessIterator>
    inline void
    partial_sort(_RandomAccessIterator __first,
   _RandomAccessIterator __middle,
   _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;





                                                       ;
                                                      ;

      std::__heap_select(__first, __middle, __last);
      std::sort_heap(__first, __middle);
    }
  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    partial_sort(_RandomAccessIterator __first,
   _RandomAccessIterator __middle,
   _RandomAccessIterator __last,
   _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;






                                                       ;
                                                      ;

      std::__heap_select(__first, __middle, __last, __comp);
      std::sort_heap(__first, __middle, __comp);
    }
  template<typename _InputIterator, typename _RandomAccessIterator>
    _RandomAccessIterator
    partial_sort_copy(_InputIterator __first, _InputIterator __last,
        _RandomAccessIterator __result_first,
        _RandomAccessIterator __result_last)
    {
      typedef typename iterator_traits<_InputIterator>::value_type
 _InputValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _OutputValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _DistanceType;
                                                     ;
                                                                   ;

      if (__result_first == __result_last)
 return __result_last;
      _RandomAccessIterator __result_real_last = __result_first;
      while(__first != __last && __result_real_last != __result_last)
 {
   *__result_real_last = *__first;
   ++__result_real_last;
   ++__first;
 }
      std::make_heap(__result_first, __result_real_last);
      while (__first != __last)
 {
   if (*__first < *__result_first)
     std::__adjust_heap(__result_first, _DistanceType(0),
          _DistanceType(__result_real_last
          - __result_first),
          _InputValueType(*__first));
   ++__first;
 }
      std::sort_heap(__result_first, __result_real_last);
      return __result_real_last;
    }
  template<typename _InputIterator, typename _RandomAccessIterator, typename _Compare>
    _RandomAccessIterator
    partial_sort_copy(_InputIterator __first, _InputIterator __last,
        _RandomAccessIterator __result_first,
        _RandomAccessIterator __result_last,
        _Compare __comp)
    {
      typedef typename iterator_traits<_InputIterator>::value_type
 _InputValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _OutputValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _DistanceType;
                                                     ;
                                                                   ;

      if (__result_first == __result_last)
 return __result_last;
      _RandomAccessIterator __result_real_last = __result_first;
      while(__first != __last && __result_real_last != __result_last)
 {
   *__result_real_last = *__first;
   ++__result_real_last;
   ++__first;
 }
      std::make_heap(__result_first, __result_real_last, __comp);
      while (__first != __last)
 {
   if (__comp(*__first, *__result_first))
     std::__adjust_heap(__result_first, _DistanceType(0),
          _DistanceType(__result_real_last
          - __result_first),
          _InputValueType(*__first),
          __comp);
   ++__first;
 }
      std::sort_heap(__result_first, __result_real_last, __comp);
      return __result_real_last;
    }






  template<typename _RandomAccessIterator, typename _Size>
    void
    __introsort_loop(_RandomAccessIterator __first,
       _RandomAccessIterator __last,
       _Size __depth_limit)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      while (__last - __first > int(_S_threshold))
 {
   if (__depth_limit == 0)
     {
       std::partial_sort(__first, __last, __last);
       return;
     }
   --__depth_limit;
   _RandomAccessIterator __cut =
     std::__unguarded_partition(__first, __last,
           _ValueType(std::__median(*__first,
        *(__first
          + (__last
             - __first)
          / 2),
        *(__last
          - 1))));
   std::__introsort_loop(__cut, __last, __depth_limit);
   __last = __cut;
 }
    }






  template<typename _RandomAccessIterator, typename _Size, typename _Compare>
    void
    __introsort_loop(_RandomAccessIterator __first,
       _RandomAccessIterator __last,
       _Size __depth_limit, _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      while (__last - __first > int(_S_threshold))
 {
   if (__depth_limit == 0)
     {
       std::partial_sort(__first, __last, __last, __comp);
       return;
     }
   --__depth_limit;
   _RandomAccessIterator __cut =
     std::__unguarded_partition(__first, __last,
           _ValueType(std::__median(*__first,
        *(__first
          + (__last
             - __first)
          / 2),
        *(__last - 1),
        __comp)),
           __comp);
   std::__introsort_loop(__cut, __last, __depth_limit, __comp);
   __last = __cut;
 }
    }
  template<typename _RandomAccessIterator>
    inline void
    sort(_RandomAccessIterator __first, _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;





                                                     ;

      if (__first != __last)
 {
   std::__introsort_loop(__first, __last,
    std::__lg(__last - __first) * 2);
   std::__final_insertion_sort(__first, __last);
 }
    }
  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    sort(_RandomAccessIterator __first, _RandomAccessIterator __last,
  _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;






                                                     ;

      if (__first != __last)
 {
   std::__introsort_loop(__first, __last,
    std::__lg(__last - __first) * 2, __comp);
   std::__final_insertion_sort(__first, __last, __comp);
 }
    }
  template<typename _ForwardIterator, typename _Tp>
    _ForwardIterator
    lower_bound(_ForwardIterator __first, _ForwardIterator __last,
  const _Tp& __val)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_ForwardIterator>::difference_type
 _DistanceType;




                                                            ;

      _DistanceType __len = std::distance(__first, __last);
      _DistanceType __half;
      _ForwardIterator __middle;

      while (__len > 0)
 {
   __half = __len >> 1;
   __middle = __first;
   std::advance(__middle, __half);
   if (*__middle < __val)
     {
       __first = __middle;
       ++__first;
       __len = __len - __half - 1;
     }
   else
     __len = __half;
 }
      return __first;
    }
  template<typename _ForwardIterator, typename _Tp, typename _Compare>
    _ForwardIterator
    lower_bound(_ForwardIterator __first, _ForwardIterator __last,
  const _Tp& __val, _Compare __comp)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_ForwardIterator>::difference_type
 _DistanceType;





                                                                         ;

      _DistanceType __len = std::distance(__first, __last);
      _DistanceType __half;
      _ForwardIterator __middle;

      while (__len > 0)
 {
   __half = __len >> 1;
   __middle = __first;
   std::advance(__middle, __half);
   if (__comp(*__middle, __val))
     {
       __first = __middle;
       ++__first;
       __len = __len - __half - 1;
     }
   else
     __len = __half;
 }
      return __first;
    }
  template<typename _ForwardIterator, typename _Tp>
    _ForwardIterator
    upper_bound(_ForwardIterator __first, _ForwardIterator __last,
  const _Tp& __val)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_ForwardIterator>::difference_type
 _DistanceType;




                                                            ;

      _DistanceType __len = std::distance(__first, __last);
      _DistanceType __half;
      _ForwardIterator __middle;

      while (__len > 0)
 {
   __half = __len >> 1;
   __middle = __first;
   std::advance(__middle, __half);
   if (__val < *__middle)
     __len = __half;
   else
     {
       __first = __middle;
       ++__first;
       __len = __len - __half - 1;
     }
 }
      return __first;
    }
  template<typename _ForwardIterator, typename _Tp, typename _Compare>
    _ForwardIterator
    upper_bound(_ForwardIterator __first, _ForwardIterator __last,
  const _Tp& __val, _Compare __comp)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_ForwardIterator>::difference_type
 _DistanceType;





                                                                         ;

      _DistanceType __len = std::distance(__first, __last);
      _DistanceType __half;
      _ForwardIterator __middle;

      while (__len > 0)
 {
   __half = __len >> 1;
   __middle = __first;
   std::advance(__middle, __half);
   if (__comp(__val, *__middle))
     __len = __half;
   else
     {
       __first = __middle;
       ++__first;
       __len = __len - __half - 1;
     }
 }
      return __first;
    }






  template<typename _BidirectionalIterator, typename _Distance>
    void
    __merge_without_buffer(_BidirectionalIterator __first,
      _BidirectionalIterator __middle,
      _BidirectionalIterator __last,
      _Distance __len1, _Distance __len2)
    {
      if (__len1 == 0 || __len2 == 0)
 return;
      if (__len1 + __len2 == 2)
 {
   if (*__middle < *__first)
     std::iter_swap(__first, __middle);
   return;
 }
      _BidirectionalIterator __first_cut = __first;
      _BidirectionalIterator __second_cut = __middle;
      _Distance __len11 = 0;
      _Distance __len22 = 0;
      if (__len1 > __len2)
 {
   __len11 = __len1 / 2;
   std::advance(__first_cut, __len11);
   __second_cut = std::lower_bound(__middle, __last, *__first_cut);
   __len22 = std::distance(__middle, __second_cut);
 }
      else
 {
   __len22 = __len2 / 2;
   std::advance(__second_cut, __len22);
   __first_cut = std::upper_bound(__first, __middle, *__second_cut);
   __len11 = std::distance(__first, __first_cut);
 }
      std::rotate(__first_cut, __middle, __second_cut);
      _BidirectionalIterator __new_middle = __first_cut;
      std::advance(__new_middle, std::distance(__middle, __second_cut));
      std::__merge_without_buffer(__first, __first_cut, __new_middle,
      __len11, __len22);
      std::__merge_without_buffer(__new_middle, __second_cut, __last,
      __len1 - __len11, __len2 - __len22);
    }






  template<typename _BidirectionalIterator, typename _Distance,
    typename _Compare>
    void
    __merge_without_buffer(_BidirectionalIterator __first,
                           _BidirectionalIterator __middle,
      _BidirectionalIterator __last,
      _Distance __len1, _Distance __len2,
      _Compare __comp)
    {
      if (__len1 == 0 || __len2 == 0)
 return;
      if (__len1 + __len2 == 2)
 {
   if (__comp(*__middle, *__first))
     std::iter_swap(__first, __middle);
   return;
 }
      _BidirectionalIterator __first_cut = __first;
      _BidirectionalIterator __second_cut = __middle;
      _Distance __len11 = 0;
      _Distance __len22 = 0;
      if (__len1 > __len2)
 {
   __len11 = __len1 / 2;
   std::advance(__first_cut, __len11);
   __second_cut = std::lower_bound(__middle, __last, *__first_cut,
       __comp);
   __len22 = std::distance(__middle, __second_cut);
 }
      else
 {
   __len22 = __len2 / 2;
   std::advance(__second_cut, __len22);
   __first_cut = std::upper_bound(__first, __middle, *__second_cut,
      __comp);
   __len11 = std::distance(__first, __first_cut);
 }
      std::rotate(__first_cut, __middle, __second_cut);
      _BidirectionalIterator __new_middle = __first_cut;
      std::advance(__new_middle, std::distance(__middle, __second_cut));
      std::__merge_without_buffer(__first, __first_cut, __new_middle,
      __len11, __len22, __comp);
      std::__merge_without_buffer(__new_middle, __second_cut, __last,
      __len1 - __len11, __len2 - __len22, __comp);
    }






  template<typename _RandomAccessIterator>
    void
    __inplace_stable_sort(_RandomAccessIterator __first,
     _RandomAccessIterator __last)
    {
      if (__last - __first < 15)
 {
   std::__insertion_sort(__first, __last);
   return;
 }
      _RandomAccessIterator __middle = __first + (__last - __first) / 2;
      std::__inplace_stable_sort(__first, __middle);
      std::__inplace_stable_sort(__middle, __last);
      std::__merge_without_buffer(__first, __middle, __last,
      __middle - __first,
      __last - __middle);
    }






  template<typename _RandomAccessIterator, typename _Compare>
    void
    __inplace_stable_sort(_RandomAccessIterator __first,
     _RandomAccessIterator __last, _Compare __comp)
    {
      if (__last - __first < 15)
 {
   std::__insertion_sort(__first, __last, __comp);
   return;
 }
      _RandomAccessIterator __middle = __first + (__last - __first) / 2;
      std::__inplace_stable_sort(__first, __middle, __comp);
      std::__inplace_stable_sort(__middle, __last, __comp);
      std::__merge_without_buffer(__first, __middle, __last,
      __middle - __first,
      __last - __middle,
      __comp);
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator>
    _OutputIterator
    merge(_InputIterator1 __first1, _InputIterator1 __last1,
   _InputIterator2 __first2, _InputIterator2 __last2,
   _OutputIterator __result)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                  ;
                                                  ;

      while (__first1 != __last1 && __first2 != __last2)
 {
   if (*__first2 < *__first1)
     {
       *__result = *__first2;
       ++__first2;
     }
   else
     {
       *__result = *__first1;
       ++__first1;
     }
   ++__result;
 }
      return std::copy(__first2, __last2, std::copy(__first1, __last1,
          __result));
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator, typename _Compare>
    _OutputIterator
    merge(_InputIterator1 __first1, _InputIterator1 __last1,
   _InputIterator2 __first2, _InputIterator2 __last2,
   _OutputIterator __result, _Compare __comp)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                               ;
                                                               ;

      while (__first1 != __last1 && __first2 != __last2)
 {
   if (__comp(*__first2, *__first1))
     {
       *__result = *__first2;
       ++__first2;
     }
   else
     {
       *__result = *__first1;
       ++__first1;
     }
   ++__result;
 }
      return std::copy(__first2, __last2, std::copy(__first1, __last1,
          __result));
    }

  template<typename _RandomAccessIterator1, typename _RandomAccessIterator2,
    typename _Distance>
    void
    __merge_sort_loop(_RandomAccessIterator1 __first,
        _RandomAccessIterator1 __last,
        _RandomAccessIterator2 __result,
        _Distance __step_size)
    {
      const _Distance __two_step = 2 * __step_size;

      while (__last - __first >= __two_step)
 {
   __result = std::merge(__first, __first + __step_size,
    __first + __step_size, __first + __two_step,
    __result);
   __first += __two_step;
 }

      __step_size = std::min(_Distance(__last - __first), __step_size);
      std::merge(__first, __first + __step_size, __first + __step_size, __last,
   __result);
    }

  template<typename _RandomAccessIterator1, typename _RandomAccessIterator2,
    typename _Distance, typename _Compare>
    void
    __merge_sort_loop(_RandomAccessIterator1 __first,
        _RandomAccessIterator1 __last,
        _RandomAccessIterator2 __result, _Distance __step_size,
        _Compare __comp)
    {
      const _Distance __two_step = 2 * __step_size;

      while (__last - __first >= __two_step)
 {
   __result = std::merge(__first, __first + __step_size,
    __first + __step_size, __first + __two_step,
    __result,
    __comp);
   __first += __two_step;
 }
      __step_size = std::min(_Distance(__last - __first), __step_size);

      std::merge(__first, __first + __step_size,
   __first + __step_size, __last,
   __result,
   __comp);
    }

  enum { _S_chunk_size = 7 };

  template<typename _RandomAccessIterator, typename _Distance>
    void
    __chunk_insertion_sort(_RandomAccessIterator __first,
      _RandomAccessIterator __last,
      _Distance __chunk_size)
    {
      while (__last - __first >= __chunk_size)
 {
   std::__insertion_sort(__first, __first + __chunk_size);
   __first += __chunk_size;
 }
      std::__insertion_sort(__first, __last);
    }

  template<typename _RandomAccessIterator, typename _Distance, typename _Compare>
    void
    __chunk_insertion_sort(_RandomAccessIterator __first,
      _RandomAccessIterator __last,
      _Distance __chunk_size, _Compare __comp)
    {
      while (__last - __first >= __chunk_size)
 {
   std::__insertion_sort(__first, __first + __chunk_size, __comp);
   __first += __chunk_size;
 }
      std::__insertion_sort(__first, __last, __comp);
    }

  template<typename _RandomAccessIterator, typename _Pointer>
    void
    __merge_sort_with_buffer(_RandomAccessIterator __first,
        _RandomAccessIterator __last,
                             _Pointer __buffer)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _Distance;

      const _Distance __len = __last - __first;
      const _Pointer __buffer_last = __buffer + __len;

      _Distance __step_size = _S_chunk_size;
      std::__chunk_insertion_sort(__first, __last, __step_size);

      while (__step_size < __len)
 {
   std::__merge_sort_loop(__first, __last, __buffer, __step_size);
   __step_size *= 2;
   std::__merge_sort_loop(__buffer, __buffer_last, __first, __step_size);
   __step_size *= 2;
 }
    }

  template<typename _RandomAccessIterator, typename _Pointer, typename _Compare>
    void
    __merge_sort_with_buffer(_RandomAccessIterator __first,
        _RandomAccessIterator __last,
                             _Pointer __buffer, _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _Distance;

      const _Distance __len = __last - __first;
      const _Pointer __buffer_last = __buffer + __len;

      _Distance __step_size = _S_chunk_size;
      std::__chunk_insertion_sort(__first, __last, __step_size, __comp);

      while (__step_size < __len)
 {
   std::__merge_sort_loop(__first, __last, __buffer,
     __step_size, __comp);
   __step_size *= 2;
   std::__merge_sort_loop(__buffer, __buffer_last, __first,
     __step_size, __comp);
   __step_size *= 2;
 }
    }






  template<typename _BidirectionalIterator1, typename _BidirectionalIterator2,
    typename _BidirectionalIterator3>
    _BidirectionalIterator3
    __merge_backward(_BidirectionalIterator1 __first1,
       _BidirectionalIterator1 __last1,
       _BidirectionalIterator2 __first2,
       _BidirectionalIterator2 __last2,
       _BidirectionalIterator3 __result)
    {
      if (__first1 == __last1)
 return std::copy_backward(__first2, __last2, __result);
      if (__first2 == __last2)
 return std::copy_backward(__first1, __last1, __result);
      --__last1;
      --__last2;
      while (true)
 {
   if (*__last2 < *__last1)
     {
       *--__result = *__last1;
       if (__first1 == __last1)
  return std::copy_backward(__first2, ++__last2, __result);
       --__last1;
     }
   else
     {
       *--__result = *__last2;
       if (__first2 == __last2)
  return std::copy_backward(__first1, ++__last1, __result);
       --__last2;
     }
 }
    }






  template<typename _BidirectionalIterator1, typename _BidirectionalIterator2,
    typename _BidirectionalIterator3, typename _Compare>
    _BidirectionalIterator3
    __merge_backward(_BidirectionalIterator1 __first1,
       _BidirectionalIterator1 __last1,
       _BidirectionalIterator2 __first2,
       _BidirectionalIterator2 __last2,
       _BidirectionalIterator3 __result,
       _Compare __comp)
    {
      if (__first1 == __last1)
 return std::copy_backward(__first2, __last2, __result);
      if (__first2 == __last2)
 return std::copy_backward(__first1, __last1, __result);
      --__last1;
      --__last2;
      while (true)
 {
   if (__comp(*__last2, *__last1))
     {
       *--__result = *__last1;
       if (__first1 == __last1)
  return std::copy_backward(__first2, ++__last2, __result);
       --__last1;
     }
   else
     {
       *--__result = *__last2;
       if (__first2 == __last2)
  return std::copy_backward(__first1, ++__last1, __result);
       --__last2;
     }
 }
    }






  template<typename _BidirectionalIterator1, typename _BidirectionalIterator2,
    typename _Distance>
    _BidirectionalIterator1
    __rotate_adaptive(_BidirectionalIterator1 __first,
        _BidirectionalIterator1 __middle,
        _BidirectionalIterator1 __last,
        _Distance __len1, _Distance __len2,
        _BidirectionalIterator2 __buffer,
        _Distance __buffer_size)
    {
      _BidirectionalIterator2 __buffer_end;
      if (__len1 > __len2 && __len2 <= __buffer_size)
 {
   __buffer_end = std::copy(__middle, __last, __buffer);
   std::copy_backward(__first, __middle, __last);
   return std::copy(__buffer, __buffer_end, __first);
 }
      else if (__len1 <= __buffer_size)
 {
   __buffer_end = std::copy(__first, __middle, __buffer);
   std::copy(__middle, __last, __first);
   return std::copy_backward(__buffer, __buffer_end, __last);
 }
      else
 {
   std::rotate(__first, __middle, __last);
   std::advance(__first, std::distance(__middle, __last));
   return __first;
 }
    }






  template<typename _BidirectionalIterator, typename _Distance,
    typename _Pointer>
    void
    __merge_adaptive(_BidirectionalIterator __first,
                     _BidirectionalIterator __middle,
       _BidirectionalIterator __last,
       _Distance __len1, _Distance __len2,
       _Pointer __buffer, _Distance __buffer_size)
    {
      if (__len1 <= __len2 && __len1 <= __buffer_size)
 {
   _Pointer __buffer_end = std::copy(__first, __middle, __buffer);
   std::merge(__buffer, __buffer_end, __middle, __last, __first);
 }
      else if (__len2 <= __buffer_size)
 {
   _Pointer __buffer_end = std::copy(__middle, __last, __buffer);
   std::__merge_backward(__first, __middle, __buffer,
    __buffer_end, __last);
 }
      else
 {
   _BidirectionalIterator __first_cut = __first;
   _BidirectionalIterator __second_cut = __middle;
   _Distance __len11 = 0;
   _Distance __len22 = 0;
   if (__len1 > __len2)
     {
       __len11 = __len1 / 2;
       std::advance(__first_cut, __len11);
       __second_cut = std::lower_bound(__middle, __last,
           *__first_cut);
       __len22 = std::distance(__middle, __second_cut);
     }
   else
     {
       __len22 = __len2 / 2;
       std::advance(__second_cut, __len22);
       __first_cut = std::upper_bound(__first, __middle,
          *__second_cut);
       __len11 = std::distance(__first, __first_cut);
     }
   _BidirectionalIterator __new_middle =
     std::__rotate_adaptive(__first_cut, __middle, __second_cut,
       __len1 - __len11, __len22, __buffer,
       __buffer_size);
   std::__merge_adaptive(__first, __first_cut, __new_middle, __len11,
    __len22, __buffer, __buffer_size);
   std::__merge_adaptive(__new_middle, __second_cut, __last,
    __len1 - __len11,
    __len2 - __len22, __buffer, __buffer_size);
 }
    }






  template<typename _BidirectionalIterator, typename _Distance, typename _Pointer,
    typename _Compare>
    void
    __merge_adaptive(_BidirectionalIterator __first,
                     _BidirectionalIterator __middle,
       _BidirectionalIterator __last,
       _Distance __len1, _Distance __len2,
       _Pointer __buffer, _Distance __buffer_size,
       _Compare __comp)
    {
      if (__len1 <= __len2 && __len1 <= __buffer_size)
 {
   _Pointer __buffer_end = std::copy(__first, __middle, __buffer);
   std::merge(__buffer, __buffer_end, __middle, __last, __first, __comp);
 }
      else if (__len2 <= __buffer_size)
 {
   _Pointer __buffer_end = std::copy(__middle, __last, __buffer);
   std::__merge_backward(__first, __middle, __buffer, __buffer_end,
    __last, __comp);
 }
      else
 {
   _BidirectionalIterator __first_cut = __first;
   _BidirectionalIterator __second_cut = __middle;
   _Distance __len11 = 0;
   _Distance __len22 = 0;
   if (__len1 > __len2)
     {
       __len11 = __len1 / 2;
       std::advance(__first_cut, __len11);
       __second_cut = std::lower_bound(__middle, __last, *__first_cut,
           __comp);
       __len22 = std::distance(__middle, __second_cut);
     }
   else
     {
       __len22 = __len2 / 2;
       std::advance(__second_cut, __len22);
       __first_cut = std::upper_bound(__first, __middle, *__second_cut,
          __comp);
       __len11 = std::distance(__first, __first_cut);
     }
   _BidirectionalIterator __new_middle =
     std::__rotate_adaptive(__first_cut, __middle, __second_cut,
       __len1 - __len11, __len22, __buffer,
       __buffer_size);
   std::__merge_adaptive(__first, __first_cut, __new_middle, __len11,
    __len22, __buffer, __buffer_size, __comp);
   std::__merge_adaptive(__new_middle, __second_cut, __last,
    __len1 - __len11,
    __len2 - __len22, __buffer,
    __buffer_size, __comp);
 }
    }
  template<typename _BidirectionalIterator>
    void
    inplace_merge(_BidirectionalIterator __first,
    _BidirectionalIterator __middle,
    _BidirectionalIterator __last)
    {
      typedef typename iterator_traits<_BidirectionalIterator>::value_type
          _ValueType;
      typedef typename iterator_traits<_BidirectionalIterator>::difference_type
          _DistanceType;





                                                  ;
                                                 ;

      if (__first == __middle || __middle == __last)
 return;

      _DistanceType __len1 = std::distance(__first, __middle);
      _DistanceType __len2 = std::distance(__middle, __last);

      _Temporary_buffer<_BidirectionalIterator, _ValueType> __buf(__first,
          __last);
      if (__buf.begin() == 0)
 std::__merge_without_buffer(__first, __middle, __last, __len1, __len2);
      else
 std::__merge_adaptive(__first, __middle, __last, __len1, __len2,
         __buf.begin(), _DistanceType(__buf.size()));
    }
  template<typename _BidirectionalIterator, typename _Compare>
    void
    inplace_merge(_BidirectionalIterator __first,
    _BidirectionalIterator __middle,
    _BidirectionalIterator __last,
    _Compare __comp)
    {
      typedef typename iterator_traits<_BidirectionalIterator>::value_type
          _ValueType;
      typedef typename iterator_traits<_BidirectionalIterator>::difference_type
          _DistanceType;






                                                               ;
                                                              ;

      if (__first == __middle || __middle == __last)
 return;

      const _DistanceType __len1 = std::distance(__first, __middle);
      const _DistanceType __len2 = std::distance(__middle, __last);

      _Temporary_buffer<_BidirectionalIterator, _ValueType> __buf(__first,
          __last);
      if (__buf.begin() == 0)
 std::__merge_without_buffer(__first, __middle, __last, __len1,
        __len2, __comp);
      else
 std::__merge_adaptive(__first, __middle, __last, __len1, __len2,
         __buf.begin(), _DistanceType(__buf.size()),
         __comp);
    }

  template<typename _RandomAccessIterator, typename _Pointer,
    typename _Distance>
    void
    __stable_sort_adaptive(_RandomAccessIterator __first,
      _RandomAccessIterator __last,
                           _Pointer __buffer, _Distance __buffer_size)
    {
      const _Distance __len = (__last - __first + 1) / 2;
      const _RandomAccessIterator __middle = __first + __len;
      if (__len > __buffer_size)
 {
   std::__stable_sort_adaptive(__first, __middle,
          __buffer, __buffer_size);
   std::__stable_sort_adaptive(__middle, __last,
          __buffer, __buffer_size);
 }
      else
 {
   std::__merge_sort_with_buffer(__first, __middle, __buffer);
   std::__merge_sort_with_buffer(__middle, __last, __buffer);
 }
      std::__merge_adaptive(__first, __middle, __last,
       _Distance(__middle - __first),
       _Distance(__last - __middle),
       __buffer, __buffer_size);
    }

  template<typename _RandomAccessIterator, typename _Pointer,
    typename _Distance, typename _Compare>
    void
    __stable_sort_adaptive(_RandomAccessIterator __first,
      _RandomAccessIterator __last,
                           _Pointer __buffer, _Distance __buffer_size,
                           _Compare __comp)
    {
      const _Distance __len = (__last - __first + 1) / 2;
      const _RandomAccessIterator __middle = __first + __len;
      if (__len > __buffer_size)
 {
   std::__stable_sort_adaptive(__first, __middle, __buffer,
          __buffer_size, __comp);
   std::__stable_sort_adaptive(__middle, __last, __buffer,
          __buffer_size, __comp);
 }
      else
 {
   std::__merge_sort_with_buffer(__first, __middle, __buffer, __comp);
   std::__merge_sort_with_buffer(__middle, __last, __buffer, __comp);
 }
      std::__merge_adaptive(__first, __middle, __last,
       _Distance(__middle - __first),
       _Distance(__last - __middle),
       __buffer, __buffer_size,
       __comp);
    }
  template<typename _RandomAccessIterator>
    inline void
    stable_sort(_RandomAccessIterator __first, _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _DistanceType;





                                                     ;

      _Temporary_buffer<_RandomAccessIterator, _ValueType> __buf(__first,
         __last);
      if (__buf.begin() == 0)
 std::__inplace_stable_sort(__first, __last);
      else
 std::__stable_sort_adaptive(__first, __last, __buf.begin(),
        _DistanceType(__buf.size()));
    }
  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    stable_sort(_RandomAccessIterator __first, _RandomAccessIterator __last,
  _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_RandomAccessIterator>::difference_type
 _DistanceType;







                                                     ;

      _Temporary_buffer<_RandomAccessIterator, _ValueType> __buf(__first,
         __last);
      if (__buf.begin() == 0)
 std::__inplace_stable_sort(__first, __last, __comp);
      else
 std::__stable_sort_adaptive(__first, __last, __buf.begin(),
        _DistanceType(__buf.size()), __comp);
    }


  template<typename _RandomAccessIterator, typename _Size>
    void
    __introselect(_RandomAccessIterator __first, _RandomAccessIterator __nth,
    _RandomAccessIterator __last, _Size __depth_limit)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      while (__last - __first > 3)
 {
   if (__depth_limit == 0)
     {
       std::__heap_select(__first, __nth + 1, __last);

       std::iter_swap(__first, __nth);
       return;
     }
   --__depth_limit;
   _RandomAccessIterator __cut =
     std::__unguarded_partition(__first, __last,
           _ValueType(std::__median(*__first,
        *(__first
          + (__last
             - __first)
          / 2),
        *(__last
          - 1))));
   if (__cut <= __nth)
     __first = __cut;
   else
     __last = __cut;
 }
      std::__insertion_sort(__first, __last);
    }

  template<typename _RandomAccessIterator, typename _Size, typename _Compare>
    void
    __introselect(_RandomAccessIterator __first, _RandomAccessIterator __nth,
    _RandomAccessIterator __last, _Size __depth_limit,
    _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;

      while (__last - __first > 3)
 {
   if (__depth_limit == 0)
     {
       std::__heap_select(__first, __nth + 1, __last, __comp);

       std::iter_swap(__first, __nth);
       return;
     }
   --__depth_limit;
   _RandomAccessIterator __cut =
     std::__unguarded_partition(__first, __last,
           _ValueType(std::__median(*__first,
        *(__first
          + (__last
             - __first)
          / 2),
        *(__last - 1),
        __comp)),
           __comp);
   if (__cut <= __nth)
     __first = __cut;
   else
     __last = __cut;
 }
      std::__insertion_sort(__first, __last, __comp);
    }
  template<typename _RandomAccessIterator>
    inline void
    nth_element(_RandomAccessIterator __first, _RandomAccessIterator __nth,
  _RandomAccessIterator __last)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;





                                                    ;
                                                   ;

      if (__first == __last || __nth == __last)
 return;

      std::__introselect(__first, __nth, __last,
    std::__lg(__last - __first) * 2);
    }
  template<typename _RandomAccessIterator, typename _Compare>
    inline void
    nth_element(_RandomAccessIterator __first, _RandomAccessIterator __nth,
  _RandomAccessIterator __last, _Compare __comp)
    {
      typedef typename iterator_traits<_RandomAccessIterator>::value_type
 _ValueType;






                                                    ;
                                                   ;

      if (__first == __last || __nth == __last)
 return;

      std::__introselect(__first, __nth, __last,
    std::__lg(__last - __first) * 2, __comp);
    }
  template<typename _ForwardIterator, typename _Tp>
    pair<_ForwardIterator, _ForwardIterator>
    equal_range(_ForwardIterator __first, _ForwardIterator __last,
  const _Tp& __val)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_ForwardIterator>::difference_type
 _DistanceType;





                                                            ;

      _DistanceType __len = std::distance(__first, __last);
      _DistanceType __half;
      _ForwardIterator __middle, __left, __right;

      while (__len > 0)
 {
   __half = __len >> 1;
   __middle = __first;
   std::advance(__middle, __half);
   if (*__middle < __val)
     {
       __first = __middle;
       ++__first;
       __len = __len - __half - 1;
     }
   else if (__val < *__middle)
     __len = __half;
   else
     {
       __left = std::lower_bound(__first, __middle, __val);
       std::advance(__first, __len);
       __right = std::upper_bound(++__middle, __first, __val);
       return pair<_ForwardIterator, _ForwardIterator>(__left, __right);
     }
 }
      return pair<_ForwardIterator, _ForwardIterator>(__first, __first);
    }
  template<typename _ForwardIterator, typename _Tp, typename _Compare>
    pair<_ForwardIterator, _ForwardIterator>
    equal_range(_ForwardIterator __first, _ForwardIterator __last,
  const _Tp& __val,
  _Compare __comp)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;
      typedef typename iterator_traits<_ForwardIterator>::difference_type
 _DistanceType;







                                                                         ;

      _DistanceType __len = std::distance(__first, __last);
      _DistanceType __half;
      _ForwardIterator __middle, __left, __right;

      while (__len > 0)
 {
   __half = __len >> 1;
   __middle = __first;
   std::advance(__middle, __half);
   if (__comp(*__middle, __val))
     {
       __first = __middle;
       ++__first;
       __len = __len - __half - 1;
     }
   else if (__comp(__val, *__middle))
     __len = __half;
   else
     {
       __left = std::lower_bound(__first, __middle, __val, __comp);
       std::advance(__first, __len);
       __right = std::upper_bound(++__middle, __first, __val, __comp);
       return pair<_ForwardIterator, _ForwardIterator>(__left, __right);
     }
 }
      return pair<_ForwardIterator, _ForwardIterator>(__first, __first);
    }
  template<typename _ForwardIterator, typename _Tp>
    bool
    binary_search(_ForwardIterator __first, _ForwardIterator __last,
                  const _Tp& __val)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;




                                                            ;

      _ForwardIterator __i = std::lower_bound(__first, __last, __val);
      return __i != __last && !(__val < *__i);
    }
  template<typename _ForwardIterator, typename _Tp, typename _Compare>
    bool
    binary_search(_ForwardIterator __first, _ForwardIterator __last,
                  const _Tp& __val, _Compare __comp)
    {
      typedef typename iterator_traits<_ForwardIterator>::value_type
 _ValueType;





                                                                         ;

      _ForwardIterator __i = std::lower_bound(__first, __last, __val, __comp);
      return __i != __last && !__comp(__val, *__i);
    }
  template<typename _InputIterator1, typename _InputIterator2>
    bool
    includes(_InputIterator1 __first1, _InputIterator1 __last1,
      _InputIterator2 __first2, _InputIterator2 __last2)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;






                                                  ;
                                                  ;

      while (__first1 != __last1 && __first2 != __last2)
 if (*__first2 < *__first1)
   return false;
 else if(*__first1 < *__first2)
   ++__first1;
 else
   ++__first1, ++__first2;

      return __first2 == __last2;
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _Compare>
    bool
    includes(_InputIterator1 __first1, _InputIterator1 __last1,
      _InputIterator2 __first2, _InputIterator2 __last2, _Compare __comp)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                               ;
                                                               ;

      while (__first1 != __last1 && __first2 != __last2)
 if (__comp(*__first2, *__first1))
   return false;
 else if(__comp(*__first1, *__first2))
   ++__first1;
 else
   ++__first1, ++__first2;

      return __first2 == __last2;
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator>
    _OutputIterator
    set_union(_InputIterator1 __first1, _InputIterator1 __last1,
       _InputIterator2 __first2, _InputIterator2 __last2,
       _OutputIterator __result)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                  ;
                                                  ;

      while (__first1 != __last1 && __first2 != __last2)
 {
   if (*__first1 < *__first2)
     {
       *__result = *__first1;
       ++__first1;
     }
   else if (*__first2 < *__first1)
     {
       *__result = *__first2;
       ++__first2;
     }
   else
     {
       *__result = *__first1;
       ++__first1;
       ++__first2;
     }
   ++__result;
 }
      return std::copy(__first2, __last2, std::copy(__first1, __last1,
          __result));
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator, typename _Compare>
    _OutputIterator
    set_union(_InputIterator1 __first1, _InputIterator1 __last1,
       _InputIterator2 __first2, _InputIterator2 __last2,
       _OutputIterator __result, _Compare __comp)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                               ;
                                                               ;

      while (__first1 != __last1 && __first2 != __last2)
 {
   if (__comp(*__first1, *__first2))
     {
       *__result = *__first1;
       ++__first1;
     }
   else if (__comp(*__first2, *__first1))
     {
       *__result = *__first2;
       ++__first2;
     }
   else
     {
       *__result = *__first1;
       ++__first1;
       ++__first2;
     }
   ++__result;
 }
      return std::copy(__first2, __last2, std::copy(__first1, __last1,
          __result));
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator>
    _OutputIterator
    set_intersection(_InputIterator1 __first1, _InputIterator1 __last1,
       _InputIterator2 __first2, _InputIterator2 __last2,
       _OutputIterator __result)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                  ;
                                                  ;

      while (__first1 != __last1 && __first2 != __last2)
 if (*__first1 < *__first2)
   ++__first1;
 else if (*__first2 < *__first1)
   ++__first2;
 else
   {
     *__result = *__first1;
     ++__first1;
     ++__first2;
     ++__result;
   }
      return __result;
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator, typename _Compare>
    _OutputIterator
    set_intersection(_InputIterator1 __first1, _InputIterator1 __last1,
       _InputIterator2 __first2, _InputIterator2 __last2,
       _OutputIterator __result, _Compare __comp)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                               ;
                                                               ;

      while (__first1 != __last1 && __first2 != __last2)
 if (__comp(*__first1, *__first2))
   ++__first1;
 else if (__comp(*__first2, *__first1))
   ++__first2;
 else
   {
     *__result = *__first1;
     ++__first1;
     ++__first2;
     ++__result;
   }
      return __result;
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator>
    _OutputIterator
    set_difference(_InputIterator1 __first1, _InputIterator1 __last1,
     _InputIterator2 __first2, _InputIterator2 __last2,
     _OutputIterator __result)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                  ;
                                                  ;

      while (__first1 != __last1 && __first2 != __last2)
 if (*__first1 < *__first2)
   {
     *__result = *__first1;
     ++__first1;
     ++__result;
   }
 else if (*__first2 < *__first1)
   ++__first2;
 else
   {
     ++__first1;
     ++__first2;
   }
      return std::copy(__first1, __last1, __result);
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator, typename _Compare>
    _OutputIterator
    set_difference(_InputIterator1 __first1, _InputIterator1 __last1,
     _InputIterator2 __first2, _InputIterator2 __last2,
     _OutputIterator __result, _Compare __comp)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                               ;
                                                               ;

      while (__first1 != __last1 && __first2 != __last2)
 if (__comp(*__first1, *__first2))
   {
     *__result = *__first1;
     ++__first1;
     ++__result;
   }
 else if (__comp(*__first2, *__first1))
   ++__first2;
 else
   {
     ++__first1;
     ++__first2;
   }
      return std::copy(__first1, __last1, __result);
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator>
    _OutputIterator
    set_symmetric_difference(_InputIterator1 __first1, _InputIterator1 __last1,
        _InputIterator2 __first2, _InputIterator2 __last2,
        _OutputIterator __result)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                  ;
                                                  ;

      while (__first1 != __last1 && __first2 != __last2)
 if (*__first1 < *__first2)
   {
     *__result = *__first1;
     ++__first1;
     ++__result;
   }
 else if (*__first2 < *__first1)
   {
     *__result = *__first2;
     ++__first2;
     ++__result;
   }
 else
   {
     ++__first1;
     ++__first2;
   }
      return std::copy(__first2, __last2, std::copy(__first1,
          __last1, __result));
    }
  template<typename _InputIterator1, typename _InputIterator2,
    typename _OutputIterator, typename _Compare>
    _OutputIterator
    set_symmetric_difference(_InputIterator1 __first1, _InputIterator1 __last1,
        _InputIterator2 __first2, _InputIterator2 __last2,
        _OutputIterator __result,
        _Compare __comp)
    {
      typedef typename iterator_traits<_InputIterator1>::value_type
 _ValueType1;
      typedef typename iterator_traits<_InputIterator2>::value_type
 _ValueType2;
                                                               ;
                                                               ;

      while (__first1 != __last1 && __first2 != __last2)
 if (__comp(*__first1, *__first2))
   {
     *__result = *__first1;
     ++__first1;
     ++__result;
   }
 else if (__comp(*__first2, *__first1))
   {
     *__result = *__first2;
     ++__first2;
     ++__result;
   }
 else
   {
     ++__first1;
     ++__first2;
   }
      return std::copy(__first2, __last2, std::copy(__first1,
          __last1, __result));
    }
  template<typename _ForwardIterator>
    _ForwardIterator
    max_element(_ForwardIterator __first, _ForwardIterator __last)
    {




                                                     ;

      if (__first == __last)
 return __first;
      _ForwardIterator __result = __first;
      while (++__first != __last)
 if (*__result < *__first)
   __result = __first;
      return __result;
    }
  template<typename _ForwardIterator, typename _Compare>
    _ForwardIterator
    max_element(_ForwardIterator __first, _ForwardIterator __last,
  _Compare __comp)
    {





                                                     ;

      if (__first == __last) return __first;
      _ForwardIterator __result = __first;
      while (++__first != __last)
 if (__comp(*__result, *__first)) __result = __first;
      return __result;
    }







  template<typename _ForwardIterator>
    _ForwardIterator
    min_element(_ForwardIterator __first, _ForwardIterator __last)
    {




                                                     ;

      if (__first == __last)
 return __first;
      _ForwardIterator __result = __first;
      while (++__first != __last)
 if (*__first < *__result)
   __result = __first;
      return __result;
    }
  template<typename _ForwardIterator, typename _Compare>
    _ForwardIterator
    min_element(_ForwardIterator __first, _ForwardIterator __last,
  _Compare __comp)
    {





                                                     ;

      if (__first == __last)
 return __first;
      _ForwardIterator __result = __first;
      while (++__first != __last)
 if (__comp(*__first, *__result))
   __result = __first;
      return __result;
    }
  template<typename _BidirectionalIterator>
    bool
    next_permutation(_BidirectionalIterator __first,
       _BidirectionalIterator __last)
    {





                                                     ;

      if (__first == __last)
 return false;
      _BidirectionalIterator __i = __first;
      ++__i;
      if (__i == __last)
 return false;
      __i = __last;
      --__i;

      for(;;)
 {
   _BidirectionalIterator __ii = __i;
   --__i;
   if (*__i < *__ii)
     {
       _BidirectionalIterator __j = __last;
       while (!(*__i < *--__j))
  {}
       std::iter_swap(__i, __j);
       std::reverse(__ii, __last);
       return true;
     }
   if (__i == __first)
     {
       std::reverse(__first, __last);
       return false;
     }
 }
    }
  template<typename _BidirectionalIterator, typename _Compare>
    bool
    next_permutation(_BidirectionalIterator __first,
       _BidirectionalIterator __last, _Compare __comp)
    {






                                                     ;

      if (__first == __last)
 return false;
      _BidirectionalIterator __i = __first;
      ++__i;
      if (__i == __last)
 return false;
      __i = __last;
      --__i;

      for(;;)
 {
   _BidirectionalIterator __ii = __i;
   --__i;
   if (__comp(*__i, *__ii))
     {
       _BidirectionalIterator __j = __last;
       while (!__comp(*__i, *--__j))
  {}
       std::iter_swap(__i, __j);
       std::reverse(__ii, __last);
       return true;
     }
   if (__i == __first)
     {
       std::reverse(__first, __last);
       return false;
     }
 }
    }
  template<typename _BidirectionalIterator>
    bool
    prev_permutation(_BidirectionalIterator __first,
       _BidirectionalIterator __last)
    {





                                                     ;

      if (__first == __last)
 return false;
      _BidirectionalIterator __i = __first;
      ++__i;
      if (__i == __last)
 return false;
      __i = __last;
      --__i;

      for(;;)
 {
   _BidirectionalIterator __ii = __i;
   --__i;
   if (*__ii < *__i)
     {
       _BidirectionalIterator __j = __last;
       while (!(*--__j < *__i))
  {}
       std::iter_swap(__i, __j);
       std::reverse(__ii, __last);
       return true;
     }
   if (__i == __first)
     {
       std::reverse(__first, __last);
       return false;
     }
 }
    }
  template<typename _BidirectionalIterator, typename _Compare>
    bool
    prev_permutation(_BidirectionalIterator __first,
       _BidirectionalIterator __last, _Compare __comp)
    {






                                                     ;

      if (__first == __last)
 return false;
      _BidirectionalIterator __i = __first;
      ++__i;
      if (__i == __last)
 return false;
      __i = __last;
      --__i;

      for(;;)
 {
   _BidirectionalIterator __ii = __i;
   --__i;
   if (__comp(*__ii, *__i))
     {
       _BidirectionalIterator __j = __last;
       while (!__comp(*--__j, *__i))
  {}
       std::iter_swap(__i, __j);
       std::reverse(__ii, __last);
       return true;
     }
   if (__i == __first)
     {
       std::reverse(__first, __last);
       return false;
     }
 }
    }
  template<typename _InputIterator, typename _ForwardIterator>
    _InputIterator
    find_first_of(_InputIterator __first1, _InputIterator __last1,
    _ForwardIterator __first2, _ForwardIterator __last2)
    {






                                                       ;
                                                       ;

      for ( ; __first1 != __last1; ++__first1)
 for (_ForwardIterator __iter = __first2; __iter != __last2; ++__iter)
   if (*__first1 == *__iter)
     return __first1;
      return __last1;
    }
  template<typename _InputIterator, typename _ForwardIterator,
    typename _BinaryPredicate>
    _InputIterator
    find_first_of(_InputIterator __first1, _InputIterator __last1,
    _ForwardIterator __first2, _ForwardIterator __last2,
    _BinaryPredicate __comp)
    {






                                                       ;
                                                       ;

      for ( ; __first1 != __last1; ++__first1)
 for (_ForwardIterator __iter = __first2; __iter != __last2; ++__iter)
   if (__comp(*__first1, *__iter))
     return __first1;
      return __last1;
    }
  template<typename _ForwardIterator1, typename _ForwardIterator2>
    _ForwardIterator1
    __find_end(_ForwardIterator1 __first1, _ForwardIterator1 __last1,
        _ForwardIterator2 __first2, _ForwardIterator2 __last2,
        forward_iterator_tag, forward_iterator_tag)
    {
      if (__first2 == __last2)
 return __last1;
      else
 {
   _ForwardIterator1 __result = __last1;
   while (1)
     {
       _ForwardIterator1 __new_result
  = std::search(__first1, __last1, __first2, __last2);
       if (__new_result == __last1)
  return __result;
       else
  {
    __result = __new_result;
    __first1 = __new_result;
    ++__first1;
  }
     }
 }
    }

  template<typename _ForwardIterator1, typename _ForwardIterator2,
    typename _BinaryPredicate>
    _ForwardIterator1
    __find_end(_ForwardIterator1 __first1, _ForwardIterator1 __last1,
        _ForwardIterator2 __first2, _ForwardIterator2 __last2,
        forward_iterator_tag, forward_iterator_tag,
        _BinaryPredicate __comp)
    {
      if (__first2 == __last2)
 return __last1;
      else
 {
   _ForwardIterator1 __result = __last1;
   while (1)
     {
       _ForwardIterator1 __new_result
  = std::search(__first1, __last1, __first2, __last2, __comp);
       if (__new_result == __last1)
  return __result;
       else
  {
    __result = __new_result;
    __first1 = __new_result;
    ++__first1;
  }
     }
 }
    }


  template<typename _BidirectionalIterator1, typename _BidirectionalIterator2>
    _BidirectionalIterator1
    __find_end(_BidirectionalIterator1 __first1,
        _BidirectionalIterator1 __last1,
        _BidirectionalIterator2 __first2,
        _BidirectionalIterator2 __last2,
        bidirectional_iterator_tag, bidirectional_iterator_tag)
    {






      typedef reverse_iterator<_BidirectionalIterator1> _RevIterator1;
      typedef reverse_iterator<_BidirectionalIterator2> _RevIterator2;

      _RevIterator1 __rlast1(__first1);
      _RevIterator2 __rlast2(__first2);
      _RevIterator1 __rresult = std::search(_RevIterator1(__last1), __rlast1,
         _RevIterator2(__last2), __rlast2);

      if (__rresult == __rlast1)
 return __last1;
      else
 {
   _BidirectionalIterator1 __result = __rresult.base();
   std::advance(__result, -std::distance(__first2, __last2));
   return __result;
 }
    }

  template<typename _BidirectionalIterator1, typename _BidirectionalIterator2,
    typename _BinaryPredicate>
    _BidirectionalIterator1
    __find_end(_BidirectionalIterator1 __first1,
        _BidirectionalIterator1 __last1,
        _BidirectionalIterator2 __first2,
        _BidirectionalIterator2 __last2,
        bidirectional_iterator_tag, bidirectional_iterator_tag,
        _BinaryPredicate __comp)
    {






      typedef reverse_iterator<_BidirectionalIterator1> _RevIterator1;
      typedef reverse_iterator<_BidirectionalIterator2> _RevIterator2;

      _RevIterator1 __rlast1(__first1);
      _RevIterator2 __rlast2(__first2);
      _RevIterator1 __rresult = std::search(_RevIterator1(__last1), __rlast1,
         _RevIterator2(__last2), __rlast2,
         __comp);

      if (__rresult == __rlast1)
 return __last1;
      else
 {
   _BidirectionalIterator1 __result = __rresult.base();
   std::advance(__result, -std::distance(__first2, __last2));
   return __result;
 }
    }
  template<typename _ForwardIterator1, typename _ForwardIterator2>
    inline _ForwardIterator1
    find_end(_ForwardIterator1 __first1, _ForwardIterator1 __last1,
      _ForwardIterator2 __first2, _ForwardIterator2 __last2)
    {






                                                       ;
                                                       ;

      return std::__find_end(__first1, __last1, __first2, __last2,
        std::__iterator_category(__first1),
        std::__iterator_category(__first2));
    }
  template<typename _ForwardIterator1, typename _ForwardIterator2,
    typename _BinaryPredicate>
    inline _ForwardIterator1
    find_end(_ForwardIterator1 __first1, _ForwardIterator1 __last1,
      _ForwardIterator2 __first2, _ForwardIterator2 __last2,
      _BinaryPredicate __comp)
    {






                                                       ;
                                                       ;

      return std::__find_end(__first1, __last1, __first2, __last2,
        std::__iterator_category(__first1),
        std::__iterator_category(__first2),
        __comp);
    }

}

namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _Type>
    inline bool
    __is_null_pointer(_Type* __ptr)
    { return __ptr == 0; }

  template<typename _Type>
    inline bool
    __is_null_pointer(_Type)
    { return false; }

  template<typename _CharT, typename _Traits, typename _Alloc>
    const typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    _Rep::_S_max_size = (((npos - sizeof(_Rep_base))/sizeof(_CharT)) - 1) / 4;

  template<typename _CharT, typename _Traits, typename _Alloc>
    const _CharT
    basic_string<_CharT, _Traits, _Alloc>::
    _Rep::_S_terminal = _CharT();

  template<typename _CharT, typename _Traits, typename _Alloc>
    const typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::npos;



  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::_Rep::_S_empty_rep_storage[
    (sizeof(_Rep_base) + sizeof(_CharT) + sizeof(size_type) - 1) /
      sizeof(size_type)];





  template<typename _CharT, typename _Traits, typename _Alloc>
    template<typename _InIterator>
      _CharT*
      basic_string<_CharT, _Traits, _Alloc>::
      _S_construct(_InIterator __beg, _InIterator __end, const _Alloc& __a,
     input_iterator_tag)
      {

 if (__beg == __end && __a == _Alloc())
   return _S_empty_rep()._M_refdata();


 _CharT __buf[128];
 size_type __len = 0;
 while (__beg != __end && __len < sizeof(__buf) / sizeof(_CharT))
   {
     __buf[__len++] = *__beg;
     ++__beg;
   }
 _Rep* __r = _Rep::_S_create(__len, size_type(0), __a);
 _M_copy(__r->_M_refdata(), __buf, __len);
 if (true)
   {
     while (__beg != __end)
       {
  if (__len == __r->_M_capacity)
    {

      _Rep* __another = _Rep::_S_create(__len + 1, __len, __a);
      _M_copy(__another->_M_refdata(), __r->_M_refdata(), __len);
      __r->_M_destroy(__a);
      __r = __another;
    }
  __r->_M_refdata()[__len++] = *__beg;
  ++__beg;
       }
   }
 if (false)
   {
     __r->_M_destroy(__a);
                            ;
   }
 __r->_M_set_length_and_sharable(__len);
 return __r->_M_refdata();
      }

  template<typename _CharT, typename _Traits, typename _Alloc>
    template <typename _InIterator>
      _CharT*
      basic_string<_CharT, _Traits, _Alloc>::
      _S_construct(_InIterator __beg, _InIterator __end, const _Alloc& __a,
     forward_iterator_tag)
      {

 if (__beg == __end && __a == _Alloc())
   return _S_empty_rep()._M_refdata();


 if (__builtin_expect(__is_null_pointer(__beg) && __beg != __end, 0))
   __throw_logic_error(("basic_string::_S_construct NULL not valid"));

 const size_type __dnew = static_cast<size_type>(std::distance(__beg,
              __end));

 _Rep* __r = _Rep::_S_create(__dnew, size_type(0), __a);
 if (true)
   { _S_copy_chars(__r->_M_refdata(), __beg, __end); }
 if (false)
   {
     __r->_M_destroy(__a);
                            ;
   }
 __r->_M_set_length_and_sharable(__dnew);
 return __r->_M_refdata();
      }

  template<typename _CharT, typename _Traits, typename _Alloc>
    _CharT*
    basic_string<_CharT, _Traits, _Alloc>::
    _S_construct(size_type __n, _CharT __c, const _Alloc& __a)
    {

      if (__n == 0 && __a == _Alloc())
 return _S_empty_rep()._M_refdata();


      _Rep* __r = _Rep::_S_create(__n, size_type(0), __a);
      if (__n)
 _M_assign(__r->_M_refdata(), __n, __c);

      __r->_M_set_length_and_sharable(__n);
      return __r->_M_refdata();
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(const basic_string& __str)
    : _M_dataplus(__str._M_rep()->_M_grab(_Alloc(__str.get_allocator()),
       __str.get_allocator()),
    __str.get_allocator())
    { }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(const _Alloc& __a)
    : _M_dataplus(_S_construct(size_type(), _CharT(), __a), __a)
    { }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(const basic_string& __str, size_type __pos, size_type __n)
    : _M_dataplus(_S_construct(__str._M_data()
          + __str._M_check(__pos,
      "basic_string::basic_string"),
          __str._M_data() + __str._M_limit(__pos, __n)
          + __pos, _Alloc()), _Alloc())
    { }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(const basic_string& __str, size_type __pos,
   size_type __n, const _Alloc& __a)
    : _M_dataplus(_S_construct(__str._M_data()
          + __str._M_check(__pos,
      "basic_string::basic_string"),
          __str._M_data() + __str._M_limit(__pos, __n)
          + __pos, __a), __a)
    { }


  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(const _CharT* __s, size_type __n, const _Alloc& __a)
    : _M_dataplus(_S_construct(__s, __s + __n, __a), __a)
    { }


  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(const _CharT* __s, const _Alloc& __a)
    : _M_dataplus(_S_construct(__s, __s ? __s + traits_type::length(__s) :
          __s + npos, __a), __a)
    { }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(size_type __n, _CharT __c, const _Alloc& __a)
    : _M_dataplus(_S_construct(__n, __c, __a), __a)
    { }


  template<typename _CharT, typename _Traits, typename _Alloc>
    template<typename _InputIterator>
    basic_string<_CharT, _Traits, _Alloc>::
    basic_string(_InputIterator __beg, _InputIterator __end, const _Alloc& __a)
    : _M_dataplus(_S_construct(__beg, __end, __a), __a)
    { }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    assign(const basic_string& __str)
    {
      if (_M_rep() != __str._M_rep())
 {

   const allocator_type __a = this->get_allocator();
   _CharT* __tmp = __str._M_rep()->_M_grab(__a, __str.get_allocator());
   _M_rep()->_M_dispose(__a);
   _M_data(__tmp);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    assign(const _CharT* __s, size_type __n)
    {
                                             ;
      _M_check_length(this->size(), __n, "basic_string::assign");
      if (_M_disjunct(__s) || _M_rep()->_M_is_shared())
 return _M_replace_safe(size_type(0), this->size(), __s, __n);
      else
 {

   const size_type __pos = __s - _M_data();
   if (__pos >= __n)
     _M_copy(_M_data(), __s, __n);
   else if (__pos)
     _M_move(_M_data(), __s, __n);
   _M_rep()->_M_set_length_and_sharable(__n);
   return *this;
 }
     }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    append(size_type __n, _CharT __c)
    {
      if (__n)
 {
   _M_check_length(size_type(0), __n, "basic_string::append");
   const size_type __len = __n + this->size();
   if (__len > this->capacity() || _M_rep()->_M_is_shared())
     this->reserve(__len);
   _M_assign(_M_data() + this->size(), __n, __c);
   _M_rep()->_M_set_length_and_sharable(__len);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    append(const _CharT* __s, size_type __n)
    {
                                             ;
      if (__n)
 {
   _M_check_length(size_type(0), __n, "basic_string::append");
   const size_type __len = __n + this->size();
   if (__len > this->capacity() || _M_rep()->_M_is_shared())
     {
       if (_M_disjunct(__s))
  this->reserve(__len);
       else
  {
    const size_type __off = __s - _M_data();
    this->reserve(__len);
    __s = _M_data() + __off;
  }
     }
   _M_copy(_M_data() + this->size(), __s, __n);
   _M_rep()->_M_set_length_and_sharable(__len);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    append(const basic_string& __str)
    {
      const size_type __size = __str.size();
      if (__size)
 {
   const size_type __len = __size + this->size();
   if (__len > this->capacity() || _M_rep()->_M_is_shared())
     this->reserve(__len);
   _M_copy(_M_data() + this->size(), __str._M_data(), __size);
   _M_rep()->_M_set_length_and_sharable(__len);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    append(const basic_string& __str, size_type __pos, size_type __n)
    {
      __str._M_check(__pos, "basic_string::append");
      __n = __str._M_limit(__pos, __n);
      if (__n)
 {
   const size_type __len = __n + this->size();
   if (__len > this->capacity() || _M_rep()->_M_is_shared())
     this->reserve(__len);
   _M_copy(_M_data() + this->size(), __str._M_data() + __pos, __n);
   _M_rep()->_M_set_length_and_sharable(__len);
 }
      return *this;
    }

   template<typename _CharT, typename _Traits, typename _Alloc>
     basic_string<_CharT, _Traits, _Alloc>&
     basic_string<_CharT, _Traits, _Alloc>::
     insert(size_type __pos, const _CharT* __s, size_type __n)
     {
                                              ;
       _M_check(__pos, "basic_string::insert");
       _M_check_length(size_type(0), __n, "basic_string::insert");
       if (_M_disjunct(__s) || _M_rep()->_M_is_shared())
         return _M_replace_safe(__pos, size_type(0), __s, __n);
       else
         {

           const size_type __off = __s - _M_data();
           _M_mutate(__pos, 0, __n);
           __s = _M_data() + __off;
           _CharT* __p = _M_data() + __pos;
           if (__s + __n <= __p)
             _M_copy(__p, __s, __n);
           else if (__s >= __p)
             _M_copy(__p, __s + __n, __n);
           else
             {
        const size_type __nleft = __p - __s;
               _M_copy(__p, __s, __nleft);
               _M_copy(__p + __nleft, __p + __n, __n - __nleft);
             }
           return *this;
         }
     }

   template<typename _CharT, typename _Traits, typename _Alloc>
     basic_string<_CharT, _Traits, _Alloc>&
     basic_string<_CharT, _Traits, _Alloc>::
     replace(size_type __pos, size_type __n1, const _CharT* __s,
      size_type __n2)
     {
                                               ;
       _M_check(__pos, "basic_string::replace");
       __n1 = _M_limit(__pos, __n1);
       _M_check_length(__n1, __n2, "basic_string::replace");
       bool __left;
       if (_M_disjunct(__s) || _M_rep()->_M_is_shared())
         return _M_replace_safe(__pos, __n1, __s, __n2);
       else if ((__left = __s + __n2 <= _M_data() + __pos)
  || _M_data() + __pos + __n1 <= __s)
  {

    size_type __off = __s - _M_data();
    __left ? __off : (__off += __n2 - __n1);
    _M_mutate(__pos, __n1, __n2);
    _M_copy(_M_data() + __pos, _M_data() + __off, __n2);
    return *this;
  }
       else
  {

    const basic_string __tmp(__s, __n2);
    return _M_replace_safe(__pos, __n1, __tmp._M_data(), __n2);
  }
     }

  template<typename _CharT, typename _Traits, typename _Alloc>
    void
    basic_string<_CharT, _Traits, _Alloc>::_Rep::
    _M_destroy(const _Alloc& __a) throw ()
    {
      const size_type __size = sizeof(_Rep_base) +
                        (this->_M_capacity + 1) * sizeof(_CharT);
      _Raw_bytes_alloc(__a).deallocate(reinterpret_cast<char*>(this), __size);
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    void
    basic_string<_CharT, _Traits, _Alloc>::
    _M_leak_hard()
    {

      if (_M_rep() == &_S_empty_rep())
 return;

      if (_M_rep()->_M_is_shared())
 _M_mutate(0, 0, 0);
      _M_rep()->_M_set_leaked();
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    void
    basic_string<_CharT, _Traits, _Alloc>::
    _M_mutate(size_type __pos, size_type __len1, size_type __len2)
    {
      const size_type __old_size = this->size();
      const size_type __new_size = __old_size + __len2 - __len1;
      const size_type __how_much = __old_size - __pos - __len1;

      if (__new_size > this->capacity() || _M_rep()->_M_is_shared())
 {

   const allocator_type __a = get_allocator();
   _Rep* __r = _Rep::_S_create(__new_size, this->capacity(), __a);

   if (__pos)
     _M_copy(__r->_M_refdata(), _M_data(), __pos);
   if (__how_much)
     _M_copy(__r->_M_refdata() + __pos + __len2,
      _M_data() + __pos + __len1, __how_much);

   _M_rep()->_M_dispose(__a);
   _M_data(__r->_M_refdata());
 }
      else if (__how_much && __len1 != __len2)
 {

   _M_move(_M_data() + __pos + __len2,
    _M_data() + __pos + __len1, __how_much);
 }
      _M_rep()->_M_set_length_and_sharable(__new_size);
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    void
    basic_string<_CharT, _Traits, _Alloc>::
    reserve(size_type __res)
    {
      if (__res != this->capacity() || _M_rep()->_M_is_shared())
        {

   if (__res < this->size())
     __res = this->size();
   const allocator_type __a = get_allocator();
   _CharT* __tmp = _M_rep()->_M_clone(__a, __res - this->size());
   _M_rep()->_M_dispose(__a);
   _M_data(__tmp);
        }
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    void
    basic_string<_CharT, _Traits, _Alloc>::
    swap(basic_string& __s)
    {
      if (_M_rep()->_M_is_leaked())
 _M_rep()->_M_set_sharable();
      if (__s._M_rep()->_M_is_leaked())
 __s._M_rep()->_M_set_sharable();
      if (this->get_allocator() == __s.get_allocator())
 {
   _CharT* __tmp = _M_data();
   _M_data(__s._M_data());
   __s._M_data(__tmp);
 }

      else
 {
   const basic_string __tmp1(_M_ibegin(), _M_iend(),
        __s.get_allocator());
   const basic_string __tmp2(__s._M_ibegin(), __s._M_iend(),
        this->get_allocator());
   *this = __tmp2;
   __s = __tmp1;
 }
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::_Rep*
    basic_string<_CharT, _Traits, _Alloc>::_Rep::
    _S_create(size_type __capacity, size_type __old_capacity,
       const _Alloc& __alloc)
    {


      if (__capacity > _S_max_size)
 __throw_length_error(("basic_string::_S_create"));
      const size_type __pagesize = 4096;
      const size_type __malloc_header_size = 4 * sizeof(void*);







      if (__capacity > __old_capacity && __capacity < 2 * __old_capacity)
 __capacity = 2 * __old_capacity;




      size_type __size = (__capacity + 1) * sizeof(_CharT) + sizeof(_Rep);

      const size_type __adj_size = __size + __malloc_header_size;
      if (__adj_size > __pagesize && __capacity > __old_capacity)
 {
   const size_type __extra = __pagesize - __adj_size % __pagesize;
   __capacity += __extra / sizeof(_CharT);

   if (__capacity > _S_max_size)
     __capacity = _S_max_size;
   __size = (__capacity + 1) * sizeof(_CharT) + sizeof(_Rep);
 }



      void* __place = _Raw_bytes_alloc(__alloc).allocate(__size);
      _Rep *__p = new (__place) _Rep;
      __p->_M_capacity = __capacity;







      __p->_M_set_sharable();
      return __p;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    _CharT*
    basic_string<_CharT, _Traits, _Alloc>::_Rep::
    _M_clone(const _Alloc& __alloc, size_type __res)
    {

      const size_type __requested_cap = this->_M_length + __res;
      _Rep* __r = _Rep::_S_create(__requested_cap, this->_M_capacity,
      __alloc);
      if (this->_M_length)
 _M_copy(__r->_M_refdata(), _M_refdata(), this->_M_length);

      __r->_M_set_length_and_sharable(this->_M_length);
      return __r->_M_refdata();
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    void
    basic_string<_CharT, _Traits, _Alloc>::
    resize(size_type __n, _CharT __c)
    {
      const size_type __size = this->size();
      _M_check_length(__size, __n, "basic_string::resize");
      if (__size < __n)
 this->append(__n - __size, __c);
      else if (__n < __size)
 this->erase(__n);

    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    template<typename _InputIterator>
      basic_string<_CharT, _Traits, _Alloc>&
      basic_string<_CharT, _Traits, _Alloc>::
      _M_replace_dispatch(iterator __i1, iterator __i2, _InputIterator __k1,
     _InputIterator __k2, __false_type)
      {
 const basic_string __s(__k1, __k2);
 const size_type __n1 = __i2 - __i1;
 _M_check_length(__n1, __s.size(), "basic_string::_M_replace_dispatch");
 return _M_replace_safe(__i1 - _M_ibegin(), __n1, __s._M_data(),
          __s.size());
      }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    _M_replace_aux(size_type __pos1, size_type __n1, size_type __n2,
     _CharT __c)
    {
      _M_check_length(__n1, __n2, "basic_string::_M_replace_aux");
      _M_mutate(__pos1, __n1, __n2);
      if (__n2)
 _M_assign(_M_data() + __pos1, __n2, __c);
      return *this;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>&
    basic_string<_CharT, _Traits, _Alloc>::
    _M_replace_safe(size_type __pos1, size_type __n1, const _CharT* __s,
      size_type __n2)
    {
      _M_mutate(__pos1, __n1, __n2);
      if (__n2)
 _M_copy(_M_data() + __pos1, __s, __n2);
      return *this;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>
    operator+(const _CharT* __lhs,
       const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    {
                                      ;
      typedef basic_string<_CharT, _Traits, _Alloc> __string_type;
      typedef typename __string_type::size_type __size_type;
      const __size_type __len = _Traits::length(__lhs);
      __string_type __str;
      __str.reserve(__len + __rhs.size());
      __str.append(__lhs, __len);
      __str.append(__rhs);
      return __str;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_string<_CharT, _Traits, _Alloc>
    operator+(_CharT __lhs, const basic_string<_CharT, _Traits, _Alloc>& __rhs)
    {
      typedef basic_string<_CharT, _Traits, _Alloc> __string_type;
      typedef typename __string_type::size_type __size_type;
      __string_type __str;
      const __size_type __len = __rhs.size();
      __str.reserve(__len + 1);
      __str.append(__size_type(1), __lhs);
      __str.append(__rhs);
      return __str;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    copy(_CharT* __s, size_type __n, size_type __pos) const
    {
      _M_check(__pos, "basic_string::copy");
      __n = _M_limit(__pos, __n);
                                             ;
      if (__n)
 _M_copy(__s, _M_data() + __pos, __n);

      return __n;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find(const _CharT* __s, size_type __pos, size_type __n) const
    {
                                             ;
      const size_type __size = this->size();
      const _CharT* __data = _M_data();

      if (__n == 0)
 return __pos <= __size ? __pos : npos;

      if (__n <= __size)
 {
   for (; __pos <= __size - __n; ++__pos)
     if (traits_type::eq(__data[__pos], __s[0])
  && traits_type::compare(__data + __pos + 1,
     __s + 1, __n - 1) == 0)
       return __pos;
 }
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find(_CharT __c, size_type __pos) const
    {
      size_type __ret = npos;
      const size_type __size = this->size();
      if (__pos < __size)
 {
   const _CharT* __data = _M_data();
   const size_type __n = __size - __pos;
   const _CharT* __p = traits_type::find(__data + __pos, __n, __c);
   if (__p)
     __ret = __p - __data;
 }
      return __ret;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    rfind(const _CharT* __s, size_type __pos, size_type __n) const
    {
                                             ;
      const size_type __size = this->size();
      if (__n <= __size)
 {
   __pos = std::min(size_type(__size - __n), __pos);
   const _CharT* __data = _M_data();
   do
     {
       if (traits_type::compare(__data + __pos, __s, __n) == 0)
  return __pos;
     }
   while (__pos-- > 0);
 }
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    rfind(_CharT __c, size_type __pos) const
    {
      size_type __size = this->size();
      if (__size)
 {
   if (--__size > __pos)
     __size = __pos;
   for (++__size; __size-- > 0; )
     if (traits_type::eq(_M_data()[__size], __c))
       return __size;
 }
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find_first_of(const _CharT* __s, size_type __pos, size_type __n) const
    {
                                             ;
      for (; __n && __pos < this->size(); ++__pos)
 {
   const _CharT* __p = traits_type::find(__s, __n, _M_data()[__pos]);
   if (__p)
     return __pos;
 }
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find_last_of(const _CharT* __s, size_type __pos, size_type __n) const
    {
                                             ;
      size_type __size = this->size();
      if (__size && __n)
 {
   if (--__size > __pos)
     __size = __pos;
   do
     {
       if (traits_type::find(__s, __n, _M_data()[__size]))
  return __size;
     }
   while (__size-- != 0);
 }
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find_first_not_of(const _CharT* __s, size_type __pos, size_type __n) const
    {
                                             ;
      for (; __pos < this->size(); ++__pos)
 if (!traits_type::find(__s, __n, _M_data()[__pos]))
   return __pos;
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find_first_not_of(_CharT __c, size_type __pos) const
    {
      for (; __pos < this->size(); ++__pos)
 if (!traits_type::eq(_M_data()[__pos], __c))
   return __pos;
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find_last_not_of(const _CharT* __s, size_type __pos, size_type __n) const
    {
                                             ;
      size_type __size = this->size();
      if (__size)
 {
   if (--__size > __pos)
     __size = __pos;
   do
     {
       if (!traits_type::find(__s, __n, _M_data()[__size]))
  return __size;
     }
   while (__size--);
 }
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    typename basic_string<_CharT, _Traits, _Alloc>::size_type
    basic_string<_CharT, _Traits, _Alloc>::
    find_last_not_of(_CharT __c, size_type __pos) const
    {
      size_type __size = this->size();
      if (__size)
 {
   if (--__size > __pos)
     __size = __pos;
   do
     {
       if (!traits_type::eq(_M_data()[__size], __c))
  return __size;
     }
   while (__size--);
 }
      return npos;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    int
    basic_string<_CharT, _Traits, _Alloc>::
    compare(size_type __pos, size_type __n, const basic_string& __str) const
    {
      _M_check(__pos, "basic_string::compare");
      __n = _M_limit(__pos, __n);
      const size_type __osize = __str.size();
      const size_type __len = std::min(__n, __osize);
      int __r = traits_type::compare(_M_data() + __pos, __str.data(), __len);
      if (!__r)
 __r = __n - __osize;
      return __r;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    int
    basic_string<_CharT, _Traits, _Alloc>::
    compare(size_type __pos1, size_type __n1, const basic_string& __str,
     size_type __pos2, size_type __n2) const
    {
      _M_check(__pos1, "basic_string::compare");
      __str._M_check(__pos2, "basic_string::compare");
      __n1 = _M_limit(__pos1, __n1);
      __n2 = __str._M_limit(__pos2, __n2);
      const size_type __len = std::min(__n1, __n2);
      int __r = traits_type::compare(_M_data() + __pos1,
         __str.data() + __pos2, __len);
      if (!__r)
 __r = __n1 - __n2;
      return __r;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    int
    basic_string<_CharT, _Traits, _Alloc>::
    compare(const _CharT* __s) const
    {
                                    ;
      const size_type __size = this->size();
      const size_type __osize = traits_type::length(__s);
      const size_type __len = std::min(__size, __osize);
      int __r = traits_type::compare(_M_data(), __s, __len);
      if (!__r)
 __r = __size - __osize;
      return __r;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    int
    basic_string <_CharT, _Traits, _Alloc>::
    compare(size_type __pos, size_type __n1, const _CharT* __s) const
    {
                                    ;
      _M_check(__pos, "basic_string::compare");
      __n1 = _M_limit(__pos, __n1);
      const size_type __osize = traits_type::length(__s);
      const size_type __len = std::min(__n1, __osize);
      int __r = traits_type::compare(_M_data() + __pos, __s, __len);
      if (!__r)
 __r = __n1 - __osize;
      return __r;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    int
    basic_string <_CharT, _Traits, _Alloc>::
    compare(size_type __pos, size_type __n1, const _CharT* __s,
     size_type __n2) const
    {
                                              ;
      _M_check(__pos, "basic_string::compare");
      __n1 = _M_limit(__pos, __n1);
      const size_type __len = std::min(__n1, __n2);
      int __r = traits_type::compare(_M_data() + __pos, __s, __len);
      if (!__r)
 __r = __n1 - __n2;
      return __r;
    }





  extern template class basic_string<char>;
  extern template
    basic_istream<char>&
    operator>>(basic_istream<char>&, string&);
  extern template
    basic_ostream<char>&
    operator<<(basic_ostream<char>&, const string&);
  extern template
    basic_istream<char>&
    getline(basic_istream<char>&, string&, char);
  extern template
    basic_istream<char>&
    getline(basic_istream<char>&, string&);


  extern template class basic_string<wchar_t>;
  extern template
    basic_istream<wchar_t>&
    operator>>(basic_istream<wchar_t>&, wstring&);
  extern template
    basic_ostream<wchar_t>&
    operator<<(basic_ostream<wchar_t>&, const wstring&);
  extern template
    basic_istream<wchar_t>&
    getline(basic_istream<wchar_t>&, wstring&, wchar_t);
  extern template
    basic_istream<wchar_t>&
    getline(basic_istream<wchar_t>&, wstring&);



}

namespace llvm {
class MCAsmBackend;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectWriter;
class MCSubtargetInfo;
class StringRef;
class Target;
class raw_ostream;

extern Target TheARMTarget, TheThumbTarget;

namespace ARM_MC {
  std::string ParseARMTriple(StringRef TT);




  MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
                                            StringRef FS);
}

MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
                                      const MCSubtargetInfo &STI,
                                      MCContext &Ctx);

MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT);


MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
                                          bool Is64Bit,
                                          uint32_t CPUType,
                                          uint32_t CPUSubtype);

}







namespace llvm {

class MCRegisterClass;
extern MCRegisterClass ARMMCRegisterClasses[];

namespace ARM {
enum {
  NoRegister,
  APSR = 1,
  CPSR = 2,
  D0 = 3,
  D1 = 4,
  D2 = 5,
  D3 = 6,
  D4 = 7,
  D5 = 8,
  D6 = 9,
  D7 = 10,
  D8 = 11,
  D9 = 12,
  D10 = 13,
  D11 = 14,
  D12 = 15,
  D13 = 16,
  D14 = 17,
  D15 = 18,
  D16 = 19,
  D17 = 20,
  D18 = 21,
  D19 = 22,
  D20 = 23,
  D21 = 24,
  D22 = 25,
  D23 = 26,
  D24 = 27,
  D25 = 28,
  D26 = 29,
  D27 = 30,
  D28 = 31,
  D29 = 32,
  D30 = 33,
  D31 = 34,
  FPEXC = 35,
  FPSCR = 36,
  FPSID = 37,
  ITSTATE = 38,
  LR = 39,
  PC = 40,
  Q0 = 41,
  Q1 = 42,
  Q2 = 43,
  Q3 = 44,
  Q4 = 45,
  Q5 = 46,
  Q6 = 47,
  Q7 = 48,
  Q8 = 49,
  Q9 = 50,
  Q10 = 51,
  Q11 = 52,
  Q12 = 53,
  Q13 = 54,
  Q14 = 55,
  Q15 = 56,
  QQ0 = 57,
  QQ1 = 58,
  QQ2 = 59,
  QQ3 = 60,
  QQ4 = 61,
  QQ5 = 62,
  QQ6 = 63,
  QQ7 = 64,
  QQQQ0 = 65,
  QQQQ1 = 66,
  QQQQ2 = 67,
  QQQQ3 = 68,
  R0 = 69,
  R1 = 70,
  R2 = 71,
  R3 = 72,
  R4 = 73,
  R5 = 74,
  R6 = 75,
  R7 = 76,
  R8 = 77,
  R9 = 78,
  R10 = 79,
  R11 = 80,
  R12 = 81,
  S0 = 82,
  S1 = 83,
  S2 = 84,
  S3 = 85,
  S4 = 86,
  S5 = 87,
  S6 = 88,
  S7 = 89,
  S8 = 90,
  S9 = 91,
  S10 = 92,
  S11 = 93,
  S12 = 94,
  S13 = 95,
  S14 = 96,
  S15 = 97,
  S16 = 98,
  S17 = 99,
  S18 = 100,
  S19 = 101,
  S20 = 102,
  S21 = 103,
  S22 = 104,
  S23 = 105,
  S24 = 106,
  S25 = 107,
  S26 = 108,
  S27 = 109,
  S28 = 110,
  S29 = 111,
  S30 = 112,
  S31 = 113,
  SP = 114,
  SPSR = 115,
  NUM_TARGET_REGS
};
}


namespace ARM {
enum {
  SPRRegClassID = 0,
  DPRRegClassID = 1,
  GPRRegClassID = 2,
  SPR_8RegClassID = 3,
  DPR_VFP2RegClassID = 4,
  QPRRegClassID = 5,
  GPRnopcRegClassID = 6,
  rGPRRegClassID = 7,
  tGPRRegClassID = 8,
  hGPRRegClassID = 9,
  DPR_8RegClassID = 10,
  QPR_VFP2RegClassID = 11,
  QQPRRegClassID = 12,
  tcGPRRegClassID = 13,
  QPR_8RegClassID = 14,
  QQPR_VFP2RegClassID = 15,
  QQQQPRRegClassID = 16,
  QQQQPR_with_ssub_0RegClassID = 17,
  GPRspRegClassID = 18,
  CCRRegClassID = 19
  };
}
}





namespace llvm {

namespace ARM {
  enum {
    PHI = 0,
    INLINEASM = 1,
    PROLOG_LABEL = 2,
    EH_LABEL = 3,
    GC_LABEL = 4,
    KILL = 5,
    EXTRACT_SUBREG = 6,
    INSERT_SUBREG = 7,
    IMPLICIT_DEF = 8,
    SUBREG_TO_REG = 9,
    COPY_TO_REGCLASS = 10,
    DBG_VALUE = 11,
    REG_SEQUENCE = 12,
    COPY = 13,
    ABS = 14,
    ADCri = 15,
    ADCrr = 16,
    ADCrsi = 17,
    ADCrsr = 18,
    ADDSri = 19,
    ADDSrr = 20,
    ADDSrsi = 21,
    ADDSrsr = 22,
    ADDri = 23,
    ADDrr = 24,
    ADDrsi = 25,
    ADDrsr = 26,
    ADJCALLSTACKDOWN = 27,
    ADJCALLSTACKUP = 28,
    ADR = 29,
    ANDri = 30,
    ANDrr = 31,
    ANDrsi = 32,
    ANDrsr = 33,
    ATOMADD6432 = 34,
    ATOMAND6432 = 35,
    ATOMCMPXCHG6432 = 36,
    ATOMIC_CMP_SWAP_I16 = 37,
    ATOMIC_CMP_SWAP_I32 = 38,
    ATOMIC_CMP_SWAP_I8 = 39,
    ATOMIC_LOAD_ADD_I16 = 40,
    ATOMIC_LOAD_ADD_I32 = 41,
    ATOMIC_LOAD_ADD_I8 = 42,
    ATOMIC_LOAD_AND_I16 = 43,
    ATOMIC_LOAD_AND_I32 = 44,
    ATOMIC_LOAD_AND_I8 = 45,
    ATOMIC_LOAD_MAX_I16 = 46,
    ATOMIC_LOAD_MAX_I32 = 47,
    ATOMIC_LOAD_MAX_I8 = 48,
    ATOMIC_LOAD_MIN_I16 = 49,
    ATOMIC_LOAD_MIN_I32 = 50,
    ATOMIC_LOAD_MIN_I8 = 51,
    ATOMIC_LOAD_NAND_I16 = 52,
    ATOMIC_LOAD_NAND_I32 = 53,
    ATOMIC_LOAD_NAND_I8 = 54,
    ATOMIC_LOAD_OR_I16 = 55,
    ATOMIC_LOAD_OR_I32 = 56,
    ATOMIC_LOAD_OR_I8 = 57,
    ATOMIC_LOAD_SUB_I16 = 58,
    ATOMIC_LOAD_SUB_I32 = 59,
    ATOMIC_LOAD_SUB_I8 = 60,
    ATOMIC_LOAD_UMAX_I16 = 61,
    ATOMIC_LOAD_UMAX_I32 = 62,
    ATOMIC_LOAD_UMAX_I8 = 63,
    ATOMIC_LOAD_UMIN_I16 = 64,
    ATOMIC_LOAD_UMIN_I32 = 65,
    ATOMIC_LOAD_UMIN_I8 = 66,
    ATOMIC_LOAD_XOR_I16 = 67,
    ATOMIC_LOAD_XOR_I32 = 68,
    ATOMIC_LOAD_XOR_I8 = 69,
    ATOMIC_SWAP_I16 = 70,
    ATOMIC_SWAP_I32 = 71,
    ATOMIC_SWAP_I8 = 72,
    ATOMNAND6432 = 73,
    ATOMOR6432 = 74,
    ATOMSUB6432 = 75,
    ATOMSWAP6432 = 76,
    ATOMXOR6432 = 77,
    B = 78,
    BCCZi64 = 79,
    BCCi64 = 80,
    BFC = 81,
    BFI = 82,
    BICri = 83,
    BICrr = 84,
    BICrsi = 85,
    BICrsr = 86,
    BKPT = 87,
    BL = 88,
    BLX = 89,
    BLX_pred = 90,
    BLXi = 91,
    BLXr9 = 92,
    BLXr9_pred = 93,
    BL_pred = 94,
    BLr9 = 95,
    BLr9_pred = 96,
    BMOVPCRX_CALL = 97,
    BMOVPCRXr9_CALL = 98,
    BR_JTadd = 99,
    BR_JTm = 100,
    BR_JTr = 101,
    BX = 102,
    BXJ = 103,
    BX_CALL = 104,
    BX_RET = 105,
    BX_pred = 106,
    BXr9_CALL = 107,
    Bcc = 108,
    CDP = 109,
    CDP2 = 110,
    CLREX = 111,
    CLZ = 112,
    CMNzri = 113,
    CMNzrr = 114,
    CMNzrsi = 115,
    CMNzrsr = 116,
    CMPri = 117,
    CMPrr = 118,
    CMPrsi = 119,
    CMPrsr = 120,
    CONSTPOOL_ENTRY = 121,
    CPS1p = 122,
    CPS2p = 123,
    CPS3p = 124,
    DBG = 125,
    DMB = 126,
    DSB = 127,
    EORri = 128,
    EORrr = 129,
    EORrsi = 130,
    EORrsr = 131,
    FCONSTD = 132,
    FCONSTS = 133,
    FMSTAT = 134,
    ISB = 135,
    Int_eh_sjlj_dispatchsetup = 136,
    Int_eh_sjlj_longjmp = 137,
    Int_eh_sjlj_setjmp = 138,
    Int_eh_sjlj_setjmp_nofp = 139,
    LDC2L_OFFSET = 140,
    LDC2L_OPTION = 141,
    LDC2L_POST = 142,
    LDC2L_PRE = 143,
    LDC2_OFFSET = 144,
    LDC2_OPTION = 145,
    LDC2_POST = 146,
    LDC2_PRE = 147,
    LDCL_OFFSET = 148,
    LDCL_OPTION = 149,
    LDCL_POST = 150,
    LDCL_PRE = 151,
    LDC_OFFSET = 152,
    LDC_OPTION = 153,
    LDC_POST = 154,
    LDC_PRE = 155,
    LDMDA = 156,
    LDMDA_UPD = 157,
    LDMDB = 158,
    LDMDB_UPD = 159,
    LDMIA = 160,
    LDMIA_RET = 161,
    LDMIA_UPD = 162,
    LDMIB = 163,
    LDMIB_UPD = 164,
    LDRBT_POST_IMM = 165,
    LDRBT_POST_REG = 166,
    LDRB_POST_IMM = 167,
    LDRB_POST_REG = 168,
    LDRB_PRE_IMM = 169,
    LDRB_PRE_REG = 170,
    LDRBi12 = 171,
    LDRBrs = 172,
    LDRD = 173,
    LDRD_POST = 174,
    LDRD_PRE = 175,
    LDREX = 176,
    LDREXB = 177,
    LDREXD = 178,
    LDREXH = 179,
    LDRH = 180,
    LDRHTi = 181,
    LDRHTr = 182,
    LDRH_POST = 183,
    LDRH_PRE = 184,
    LDRSB = 185,
    LDRSBTi = 186,
    LDRSBTr = 187,
    LDRSB_POST = 188,
    LDRSB_PRE = 189,
    LDRSH = 190,
    LDRSHTi = 191,
    LDRSHTr = 192,
    LDRSH_POST = 193,
    LDRSH_PRE = 194,
    LDRT_POST_IMM = 195,
    LDRT_POST_REG = 196,
    LDR_POST_IMM = 197,
    LDR_POST_REG = 198,
    LDR_PRE_IMM = 199,
    LDR_PRE_REG = 200,
    LDRcp = 201,
    LDRi12 = 202,
    LDRrs = 203,
    LEApcrel = 204,
    LEApcrelJT = 205,
    MCR = 206,
    MCR2 = 207,
    MCRR = 208,
    MCRR2 = 209,
    MLA = 210,
    MLAv5 = 211,
    MLS = 212,
    MOVCCi = 213,
    MOVCCi16 = 214,
    MOVCCi32imm = 215,
    MOVCCr = 216,
    MOVCCsi = 217,
    MOVCCsr = 218,
    MOVPCLR = 219,
    MOVPCRX = 220,
    MOVTi16 = 221,
    MOVTi16_ga_pcrel = 222,
    MOV_ga_dyn = 223,
    MOV_ga_pcrel = 224,
    MOV_ga_pcrel_ldr = 225,
    MOVi = 226,
    MOVi16 = 227,
    MOVi16_ga_pcrel = 228,
    MOVi32imm = 229,
    MOVr = 230,
    MOVr_TC = 231,
    MOVsi = 232,
    MOVsr = 233,
    MOVsra_flag = 234,
    MOVsrl_flag = 235,
    MRC = 236,
    MRC2 = 237,
    MRRC = 238,
    MRRC2 = 239,
    MRS = 240,
    MRSsys = 241,
    MSR = 242,
    MSRi = 243,
    MUL = 244,
    MULv5 = 245,
    MVNCCi = 246,
    MVNi = 247,
    MVNr = 248,
    MVNsi = 249,
    MVNsr = 250,
    NOP = 251,
    ORRri = 252,
    ORRrr = 253,
    ORRrsi = 254,
    ORRrsr = 255,
    PICADD = 256,
    PICLDR = 257,
    PICLDRB = 258,
    PICLDRH = 259,
    PICLDRSB = 260,
    PICLDRSH = 261,
    PICSTR = 262,
    PICSTRB = 263,
    PICSTRH = 264,
    PKHBT = 265,
    PKHTB = 266,
    PLDWi12 = 267,
    PLDWrs = 268,
    PLDi12 = 269,
    PLDrs = 270,
    PLIi12 = 271,
    PLIrs = 272,
    QADD = 273,
    QADD16 = 274,
    QADD8 = 275,
    QASX = 276,
    QDADD = 277,
    QDSUB = 278,
    QSAX = 279,
    QSUB = 280,
    QSUB16 = 281,
    QSUB8 = 282,
    RBIT = 283,
    REV = 284,
    REV16 = 285,
    REVSH = 286,
    RFEDA = 287,
    RFEDA_UPD = 288,
    RFEDB = 289,
    RFEDB_UPD = 290,
    RFEIA = 291,
    RFEIA_UPD = 292,
    RFEIB = 293,
    RFEIB_UPD = 294,
    RRX = 295,
    RSBSri = 296,
    RSBSrr = 297,
    RSBSrsi = 298,
    RSBSrsr = 299,
    RSBri = 300,
    RSBrr = 301,
    RSBrsi = 302,
    RSBrsr = 303,
    RSCri = 304,
    RSCrr = 305,
    RSCrsi = 306,
    RSCrsr = 307,
    SADD16 = 308,
    SADD8 = 309,
    SASX = 310,
    SBCri = 311,
    SBCrr = 312,
    SBCrsi = 313,
    SBCrsr = 314,
    SBFX = 315,
    SEL = 316,
    SETEND = 317,
    SEV = 318,
    SHADD16 = 319,
    SHADD8 = 320,
    SHASX = 321,
    SHSAX = 322,
    SHSUB16 = 323,
    SHSUB8 = 324,
    SMC = 325,
    SMLABB = 326,
    SMLABT = 327,
    SMLAD = 328,
    SMLADX = 329,
    SMLAL = 330,
    SMLALBB = 331,
    SMLALBT = 332,
    SMLALD = 333,
    SMLALDX = 334,
    SMLALTB = 335,
    SMLALTT = 336,
    SMLALv5 = 337,
    SMLATB = 338,
    SMLATT = 339,
    SMLAWB = 340,
    SMLAWT = 341,
    SMLSD = 342,
    SMLSDX = 343,
    SMLSLD = 344,
    SMLSLDX = 345,
    SMMLA = 346,
    SMMLAR = 347,
    SMMLS = 348,
    SMMLSR = 349,
    SMMUL = 350,
    SMMULR = 351,
    SMUAD = 352,
    SMUADX = 353,
    SMULBB = 354,
    SMULBT = 355,
    SMULL = 356,
    SMULLv5 = 357,
    SMULTB = 358,
    SMULTT = 359,
    SMULWB = 360,
    SMULWT = 361,
    SMUSD = 362,
    SMUSDX = 363,
    SRSDA = 364,
    SRSDA_UPD = 365,
    SRSDB = 366,
    SRSDB_UPD = 367,
    SRSIA = 368,
    SRSIA_UPD = 369,
    SRSIB = 370,
    SRSIB_UPD = 371,
    SSAT = 372,
    SSAT16 = 373,
    SSAX = 374,
    SSUB16 = 375,
    SSUB8 = 376,
    STC2L_OFFSET = 377,
    STC2L_OPTION = 378,
    STC2L_POST = 379,
    STC2L_PRE = 380,
    STC2_OFFSET = 381,
    STC2_OPTION = 382,
    STC2_POST = 383,
    STC2_PRE = 384,
    STCL_OFFSET = 385,
    STCL_OPTION = 386,
    STCL_POST = 387,
    STCL_PRE = 388,
    STC_OFFSET = 389,
    STC_OPTION = 390,
    STC_POST = 391,
    STC_PRE = 392,
    STMDA = 393,
    STMDA_UPD = 394,
    STMDB = 395,
    STMDB_UPD = 396,
    STMIA = 397,
    STMIA_UPD = 398,
    STMIB = 399,
    STMIB_UPD = 400,
    STRBT_POST_IMM = 401,
    STRBT_POST_REG = 402,
    STRB_POST_IMM = 403,
    STRB_POST_REG = 404,
    STRB_PRE_IMM = 405,
    STRB_PRE_REG = 406,
    STRBi12 = 407,
    STRBi_preidx = 408,
    STRBr_preidx = 409,
    STRBrs = 410,
    STRD = 411,
    STRD_POST = 412,
    STRD_PRE = 413,
    STREX = 414,
    STREXB = 415,
    STREXD = 416,
    STREXH = 417,
    STRH = 418,
    STRHTi = 419,
    STRHTr = 420,
    STRH_POST = 421,
    STRH_PRE = 422,
    STRH_preidx = 423,
    STRT_POST_IMM = 424,
    STRT_POST_REG = 425,
    STR_POST_IMM = 426,
    STR_POST_REG = 427,
    STR_PRE_IMM = 428,
    STR_PRE_REG = 429,
    STRi12 = 430,
    STRi_preidx = 431,
    STRr_preidx = 432,
    STRrs = 433,
    SUBSri = 434,
    SUBSrr = 435,
    SUBSrsi = 436,
    SUBSrsr = 437,
    SUBri = 438,
    SUBrr = 439,
    SUBrsi = 440,
    SUBrsr = 441,
    SVC = 442,
    SWP = 443,
    SWPB = 444,
    SXTAB = 445,
    SXTAB16 = 446,
    SXTAH = 447,
    SXTB = 448,
    SXTB16 = 449,
    SXTH = 450,
    TAILJMPd = 451,
    TAILJMPdND = 452,
    TAILJMPr = 453,
    TAILJMPrND = 454,
    TCRETURNdi = 455,
    TCRETURNdiND = 456,
    TCRETURNri = 457,
    TCRETURNriND = 458,
    TEQri = 459,
    TEQrr = 460,
    TEQrsi = 461,
    TEQrsr = 462,
    TPsoft = 463,
    TRAP = 464,
    TSTri = 465,
    TSTrr = 466,
    TSTrsi = 467,
    TSTrsr = 468,
    UADD16 = 469,
    UADD8 = 470,
    UASX = 471,
    UBFX = 472,
    UHADD16 = 473,
    UHADD8 = 474,
    UHASX = 475,
    UHSAX = 476,
    UHSUB16 = 477,
    UHSUB8 = 478,
    UMAAL = 479,
    UMAALv5 = 480,
    UMLAL = 481,
    UMLALv5 = 482,
    UMULL = 483,
    UMULLv5 = 484,
    UQADD16 = 485,
    UQADD8 = 486,
    UQASX = 487,
    UQSAX = 488,
    UQSUB16 = 489,
    UQSUB8 = 490,
    USAD8 = 491,
    USADA8 = 492,
    USAT = 493,
    USAT16 = 494,
    USAX = 495,
    USUB16 = 496,
    USUB8 = 497,
    UXTAB = 498,
    UXTAB16 = 499,
    UXTAH = 500,
    UXTB = 501,
    UXTB16 = 502,
    UXTH = 503,
    VABALsv2i64 = 504,
    VABALsv4i32 = 505,
    VABALsv8i16 = 506,
    VABALuv2i64 = 507,
    VABALuv4i32 = 508,
    VABALuv8i16 = 509,
    VABAsv16i8 = 510,
    VABAsv2i32 = 511,
    VABAsv4i16 = 512,
    VABAsv4i32 = 513,
    VABAsv8i16 = 514,
    VABAsv8i8 = 515,
    VABAuv16i8 = 516,
    VABAuv2i32 = 517,
    VABAuv4i16 = 518,
    VABAuv4i32 = 519,
    VABAuv8i16 = 520,
    VABAuv8i8 = 521,
    VABDLsv2i64 = 522,
    VABDLsv4i32 = 523,
    VABDLsv8i16 = 524,
    VABDLuv2i64 = 525,
    VABDLuv4i32 = 526,
    VABDLuv8i16 = 527,
    VABDfd = 528,
    VABDfq = 529,
    VABDsv16i8 = 530,
    VABDsv2i32 = 531,
    VABDsv4i16 = 532,
    VABDsv4i32 = 533,
    VABDsv8i16 = 534,
    VABDsv8i8 = 535,
    VABDuv16i8 = 536,
    VABDuv2i32 = 537,
    VABDuv4i16 = 538,
    VABDuv4i32 = 539,
    VABDuv8i16 = 540,
    VABDuv8i8 = 541,
    VABSD = 542,
    VABSS = 543,
    VABSfd = 544,
    VABSfq = 545,
    VABSv16i8 = 546,
    VABSv2i32 = 547,
    VABSv4i16 = 548,
    VABSv4i32 = 549,
    VABSv8i16 = 550,
    VABSv8i8 = 551,
    VACGEd = 552,
    VACGEq = 553,
    VACGTd = 554,
    VACGTq = 555,
    VADDD = 556,
    VADDHNv2i32 = 557,
    VADDHNv4i16 = 558,
    VADDHNv8i8 = 559,
    VADDLsv2i64 = 560,
    VADDLsv4i32 = 561,
    VADDLsv8i16 = 562,
    VADDLuv2i64 = 563,
    VADDLuv4i32 = 564,
    VADDLuv8i16 = 565,
    VADDS = 566,
    VADDWsv2i64 = 567,
    VADDWsv4i32 = 568,
    VADDWsv8i16 = 569,
    VADDWuv2i64 = 570,
    VADDWuv4i32 = 571,
    VADDWuv8i16 = 572,
    VADDfd = 573,
    VADDfq = 574,
    VADDv16i8 = 575,
    VADDv1i64 = 576,
    VADDv2i32 = 577,
    VADDv2i64 = 578,
    VADDv4i16 = 579,
    VADDv4i32 = 580,
    VADDv8i16 = 581,
    VADDv8i8 = 582,
    VANDd = 583,
    VANDq = 584,
    VBICd = 585,
    VBICiv2i32 = 586,
    VBICiv4i16 = 587,
    VBICiv4i32 = 588,
    VBICiv8i16 = 589,
    VBICq = 590,
    VBIFd = 591,
    VBIFq = 592,
    VBITd = 593,
    VBITq = 594,
    VBSLd = 595,
    VBSLq = 596,
    VCEQfd = 597,
    VCEQfq = 598,
    VCEQv16i8 = 599,
    VCEQv2i32 = 600,
    VCEQv4i16 = 601,
    VCEQv4i32 = 602,
    VCEQv8i16 = 603,
    VCEQv8i8 = 604,
    VCEQzv16i8 = 605,
    VCEQzv2f32 = 606,
    VCEQzv2i32 = 607,
    VCEQzv4f32 = 608,
    VCEQzv4i16 = 609,
    VCEQzv4i32 = 610,
    VCEQzv8i16 = 611,
    VCEQzv8i8 = 612,
    VCGEfd = 613,
    VCGEfq = 614,
    VCGEsv16i8 = 615,
    VCGEsv2i32 = 616,
    VCGEsv4i16 = 617,
    VCGEsv4i32 = 618,
    VCGEsv8i16 = 619,
    VCGEsv8i8 = 620,
    VCGEuv16i8 = 621,
    VCGEuv2i32 = 622,
    VCGEuv4i16 = 623,
    VCGEuv4i32 = 624,
    VCGEuv8i16 = 625,
    VCGEuv8i8 = 626,
    VCGEzv16i8 = 627,
    VCGEzv2f32 = 628,
    VCGEzv2i32 = 629,
    VCGEzv4f32 = 630,
    VCGEzv4i16 = 631,
    VCGEzv4i32 = 632,
    VCGEzv8i16 = 633,
    VCGEzv8i8 = 634,
    VCGTfd = 635,
    VCGTfq = 636,
    VCGTsv16i8 = 637,
    VCGTsv2i32 = 638,
    VCGTsv4i16 = 639,
    VCGTsv4i32 = 640,
    VCGTsv8i16 = 641,
    VCGTsv8i8 = 642,
    VCGTuv16i8 = 643,
    VCGTuv2i32 = 644,
    VCGTuv4i16 = 645,
    VCGTuv4i32 = 646,
    VCGTuv8i16 = 647,
    VCGTuv8i8 = 648,
    VCGTzv16i8 = 649,
    VCGTzv2f32 = 650,
    VCGTzv2i32 = 651,
    VCGTzv4f32 = 652,
    VCGTzv4i16 = 653,
    VCGTzv4i32 = 654,
    VCGTzv8i16 = 655,
    VCGTzv8i8 = 656,
    VCLEzv16i8 = 657,
    VCLEzv2f32 = 658,
    VCLEzv2i32 = 659,
    VCLEzv4f32 = 660,
    VCLEzv4i16 = 661,
    VCLEzv4i32 = 662,
    VCLEzv8i16 = 663,
    VCLEzv8i8 = 664,
    VCLSv16i8 = 665,
    VCLSv2i32 = 666,
    VCLSv4i16 = 667,
    VCLSv4i32 = 668,
    VCLSv8i16 = 669,
    VCLSv8i8 = 670,
    VCLTzv16i8 = 671,
    VCLTzv2f32 = 672,
    VCLTzv2i32 = 673,
    VCLTzv4f32 = 674,
    VCLTzv4i16 = 675,
    VCLTzv4i32 = 676,
    VCLTzv8i16 = 677,
    VCLTzv8i8 = 678,
    VCLZv16i8 = 679,
    VCLZv2i32 = 680,
    VCLZv4i16 = 681,
    VCLZv4i32 = 682,
    VCLZv8i16 = 683,
    VCLZv8i8 = 684,
    VCMPD = 685,
    VCMPED = 686,
    VCMPES = 687,
    VCMPEZD = 688,
    VCMPEZS = 689,
    VCMPS = 690,
    VCMPZD = 691,
    VCMPZS = 692,
    VCNTd = 693,
    VCNTq = 694,
    VCVTBHS = 695,
    VCVTBSH = 696,
    VCVTDS = 697,
    VCVTSD = 698,
    VCVTTHS = 699,
    VCVTTSH = 700,
    VCVTf2h = 701,
    VCVTf2sd = 702,
    VCVTf2sq = 703,
    VCVTf2ud = 704,
    VCVTf2uq = 705,
    VCVTf2xsd = 706,
    VCVTf2xsq = 707,
    VCVTf2xud = 708,
    VCVTf2xuq = 709,
    VCVTh2f = 710,
    VCVTs2fd = 711,
    VCVTs2fq = 712,
    VCVTu2fd = 713,
    VCVTu2fq = 714,
    VCVTxs2fd = 715,
    VCVTxs2fq = 716,
    VCVTxu2fd = 717,
    VCVTxu2fq = 718,
    VDIVD = 719,
    VDIVS = 720,
    VDUP16d = 721,
    VDUP16q = 722,
    VDUP32d = 723,
    VDUP32q = 724,
    VDUP8d = 725,
    VDUP8q = 726,
    VDUPLN16d = 727,
    VDUPLN16q = 728,
    VDUPLN32d = 729,
    VDUPLN32q = 730,
    VDUPLN8d = 731,
    VDUPLN8q = 732,
    VDUPfdf = 733,
    VDUPfqf = 734,
    VEORd = 735,
    VEORq = 736,
    VEXTd16 = 737,
    VEXTd32 = 738,
    VEXTd8 = 739,
    VEXTq16 = 740,
    VEXTq32 = 741,
    VEXTq8 = 742,
    VGETLNi32 = 743,
    VGETLNs16 = 744,
    VGETLNs8 = 745,
    VGETLNu16 = 746,
    VGETLNu8 = 747,
    VHADDsv16i8 = 748,
    VHADDsv2i32 = 749,
    VHADDsv4i16 = 750,
    VHADDsv4i32 = 751,
    VHADDsv8i16 = 752,
    VHADDsv8i8 = 753,
    VHADDuv16i8 = 754,
    VHADDuv2i32 = 755,
    VHADDuv4i16 = 756,
    VHADDuv4i32 = 757,
    VHADDuv8i16 = 758,
    VHADDuv8i8 = 759,
    VHSUBsv16i8 = 760,
    VHSUBsv2i32 = 761,
    VHSUBsv4i16 = 762,
    VHSUBsv4i32 = 763,
    VHSUBsv8i16 = 764,
    VHSUBsv8i8 = 765,
    VHSUBuv16i8 = 766,
    VHSUBuv2i32 = 767,
    VHSUBuv4i16 = 768,
    VHSUBuv4i32 = 769,
    VHSUBuv8i16 = 770,
    VHSUBuv8i8 = 771,
    VLD1DUPd16 = 772,
    VLD1DUPd16_UPD = 773,
    VLD1DUPd32 = 774,
    VLD1DUPd32_UPD = 775,
    VLD1DUPd8 = 776,
    VLD1DUPd8_UPD = 777,
    VLD1DUPq16 = 778,
    VLD1DUPq16Pseudo = 779,
    VLD1DUPq16Pseudo_UPD = 780,
    VLD1DUPq16_UPD = 781,
    VLD1DUPq32 = 782,
    VLD1DUPq32Pseudo = 783,
    VLD1DUPq32Pseudo_UPD = 784,
    VLD1DUPq32_UPD = 785,
    VLD1DUPq8 = 786,
    VLD1DUPq8Pseudo = 787,
    VLD1DUPq8Pseudo_UPD = 788,
    VLD1DUPq8_UPD = 789,
    VLD1LNd16 = 790,
    VLD1LNd16_UPD = 791,
    VLD1LNd32 = 792,
    VLD1LNd32_UPD = 793,
    VLD1LNd8 = 794,
    VLD1LNd8_UPD = 795,
    VLD1LNq16Pseudo = 796,
    VLD1LNq16Pseudo_UPD = 797,
    VLD1LNq32Pseudo = 798,
    VLD1LNq32Pseudo_UPD = 799,
    VLD1LNq8Pseudo = 800,
    VLD1LNq8Pseudo_UPD = 801,
    VLD1d16 = 802,
    VLD1d16Q = 803,
    VLD1d16Q_UPD = 804,
    VLD1d16T = 805,
    VLD1d16T_UPD = 806,
    VLD1d16_UPD = 807,
    VLD1d32 = 808,
    VLD1d32Q = 809,
    VLD1d32Q_UPD = 810,
    VLD1d32T = 811,
    VLD1d32T_UPD = 812,
    VLD1d32_UPD = 813,
    VLD1d64 = 814,
    VLD1d64Q = 815,
    VLD1d64QPseudo = 816,
    VLD1d64QPseudo_UPD = 817,
    VLD1d64Q_UPD = 818,
    VLD1d64T = 819,
    VLD1d64TPseudo = 820,
    VLD1d64TPseudo_UPD = 821,
    VLD1d64T_UPD = 822,
    VLD1d64_UPD = 823,
    VLD1d8 = 824,
    VLD1d8Q = 825,
    VLD1d8Q_UPD = 826,
    VLD1d8T = 827,
    VLD1d8T_UPD = 828,
    VLD1d8_UPD = 829,
    VLD1q16 = 830,
    VLD1q16Pseudo = 831,
    VLD1q16Pseudo_UPD = 832,
    VLD1q16_UPD = 833,
    VLD1q32 = 834,
    VLD1q32Pseudo = 835,
    VLD1q32Pseudo_UPD = 836,
    VLD1q32_UPD = 837,
    VLD1q64 = 838,
    VLD1q64Pseudo = 839,
    VLD1q64Pseudo_UPD = 840,
    VLD1q64_UPD = 841,
    VLD1q8 = 842,
    VLD1q8Pseudo = 843,
    VLD1q8Pseudo_UPD = 844,
    VLD1q8_UPD = 845,
    VLD2DUPd16 = 846,
    VLD2DUPd16Pseudo = 847,
    VLD2DUPd16Pseudo_UPD = 848,
    VLD2DUPd16_UPD = 849,
    VLD2DUPd16x2 = 850,
    VLD2DUPd16x2_UPD = 851,
    VLD2DUPd32 = 852,
    VLD2DUPd32Pseudo = 853,
    VLD2DUPd32Pseudo_UPD = 854,
    VLD2DUPd32_UPD = 855,
    VLD2DUPd32x2 = 856,
    VLD2DUPd32x2_UPD = 857,
    VLD2DUPd8 = 858,
    VLD2DUPd8Pseudo = 859,
    VLD2DUPd8Pseudo_UPD = 860,
    VLD2DUPd8_UPD = 861,
    VLD2DUPd8x2 = 862,
    VLD2DUPd8x2_UPD = 863,
    VLD2LNd16 = 864,
    VLD2LNd16Pseudo = 865,
    VLD2LNd16Pseudo_UPD = 866,
    VLD2LNd16_UPD = 867,
    VLD2LNd32 = 868,
    VLD2LNd32Pseudo = 869,
    VLD2LNd32Pseudo_UPD = 870,
    VLD2LNd32_UPD = 871,
    VLD2LNd8 = 872,
    VLD2LNd8Pseudo = 873,
    VLD2LNd8Pseudo_UPD = 874,
    VLD2LNd8_UPD = 875,
    VLD2LNq16 = 876,
    VLD2LNq16Pseudo = 877,
    VLD2LNq16Pseudo_UPD = 878,
    VLD2LNq16_UPD = 879,
    VLD2LNq32 = 880,
    VLD2LNq32Pseudo = 881,
    VLD2LNq32Pseudo_UPD = 882,
    VLD2LNq32_UPD = 883,
    VLD2b16 = 884,
    VLD2b16_UPD = 885,
    VLD2b32 = 886,
    VLD2b32_UPD = 887,
    VLD2b8 = 888,
    VLD2b8_UPD = 889,
    VLD2d16 = 890,
    VLD2d16Pseudo = 891,
    VLD2d16Pseudo_UPD = 892,
    VLD2d16_UPD = 893,
    VLD2d32 = 894,
    VLD2d32Pseudo = 895,
    VLD2d32Pseudo_UPD = 896,
    VLD2d32_UPD = 897,
    VLD2d8 = 898,
    VLD2d8Pseudo = 899,
    VLD2d8Pseudo_UPD = 900,
    VLD2d8_UPD = 901,
    VLD2q16 = 902,
    VLD2q16Pseudo = 903,
    VLD2q16Pseudo_UPD = 904,
    VLD2q16_UPD = 905,
    VLD2q32 = 906,
    VLD2q32Pseudo = 907,
    VLD2q32Pseudo_UPD = 908,
    VLD2q32_UPD = 909,
    VLD2q8 = 910,
    VLD2q8Pseudo = 911,
    VLD2q8Pseudo_UPD = 912,
    VLD2q8_UPD = 913,
    VLD3DUPd16 = 914,
    VLD3DUPd16Pseudo = 915,
    VLD3DUPd16Pseudo_UPD = 916,
    VLD3DUPd16_UPD = 917,
    VLD3DUPd16x2 = 918,
    VLD3DUPd16x2_UPD = 919,
    VLD3DUPd32 = 920,
    VLD3DUPd32Pseudo = 921,
    VLD3DUPd32Pseudo_UPD = 922,
    VLD3DUPd32_UPD = 923,
    VLD3DUPd32x2 = 924,
    VLD3DUPd32x2_UPD = 925,
    VLD3DUPd8 = 926,
    VLD3DUPd8Pseudo = 927,
    VLD3DUPd8Pseudo_UPD = 928,
    VLD3DUPd8_UPD = 929,
    VLD3DUPd8x2 = 930,
    VLD3DUPd8x2_UPD = 931,
    VLD3LNd16 = 932,
    VLD3LNd16Pseudo = 933,
    VLD3LNd16Pseudo_UPD = 934,
    VLD3LNd16_UPD = 935,
    VLD3LNd32 = 936,
    VLD3LNd32Pseudo = 937,
    VLD3LNd32Pseudo_UPD = 938,
    VLD3LNd32_UPD = 939,
    VLD3LNd8 = 940,
    VLD3LNd8Pseudo = 941,
    VLD3LNd8Pseudo_UPD = 942,
    VLD3LNd8_UPD = 943,
    VLD3LNq16 = 944,
    VLD3LNq16Pseudo = 945,
    VLD3LNq16Pseudo_UPD = 946,
    VLD3LNq16_UPD = 947,
    VLD3LNq32 = 948,
    VLD3LNq32Pseudo = 949,
    VLD3LNq32Pseudo_UPD = 950,
    VLD3LNq32_UPD = 951,
    VLD3d16 = 952,
    VLD3d16Pseudo = 953,
    VLD3d16Pseudo_UPD = 954,
    VLD3d16_UPD = 955,
    VLD3d32 = 956,
    VLD3d32Pseudo = 957,
    VLD3d32Pseudo_UPD = 958,
    VLD3d32_UPD = 959,
    VLD3d8 = 960,
    VLD3d8Pseudo = 961,
    VLD3d8Pseudo_UPD = 962,
    VLD3d8_UPD = 963,
    VLD3q16 = 964,
    VLD3q16Pseudo_UPD = 965,
    VLD3q16_UPD = 966,
    VLD3q16oddPseudo = 967,
    VLD3q16oddPseudo_UPD = 968,
    VLD3q32 = 969,
    VLD3q32Pseudo_UPD = 970,
    VLD3q32_UPD = 971,
    VLD3q32oddPseudo = 972,
    VLD3q32oddPseudo_UPD = 973,
    VLD3q8 = 974,
    VLD3q8Pseudo_UPD = 975,
    VLD3q8_UPD = 976,
    VLD3q8oddPseudo = 977,
    VLD3q8oddPseudo_UPD = 978,
    VLD4DUPd16 = 979,
    VLD4DUPd16Pseudo = 980,
    VLD4DUPd16Pseudo_UPD = 981,
    VLD4DUPd16_UPD = 982,
    VLD4DUPd16x2 = 983,
    VLD4DUPd16x2_UPD = 984,
    VLD4DUPd32 = 985,
    VLD4DUPd32Pseudo = 986,
    VLD4DUPd32Pseudo_UPD = 987,
    VLD4DUPd32_UPD = 988,
    VLD4DUPd32x2 = 989,
    VLD4DUPd32x2_UPD = 990,
    VLD4DUPd8 = 991,
    VLD4DUPd8Pseudo = 992,
    VLD4DUPd8Pseudo_UPD = 993,
    VLD4DUPd8_UPD = 994,
    VLD4DUPd8x2 = 995,
    VLD4DUPd8x2_UPD = 996,
    VLD4LNd16 = 997,
    VLD4LNd16Pseudo = 998,
    VLD4LNd16Pseudo_UPD = 999,
    VLD4LNd16_UPD = 1000,
    VLD4LNd32 = 1001,
    VLD4LNd32Pseudo = 1002,
    VLD4LNd32Pseudo_UPD = 1003,
    VLD4LNd32_UPD = 1004,
    VLD4LNd8 = 1005,
    VLD4LNd8Pseudo = 1006,
    VLD4LNd8Pseudo_UPD = 1007,
    VLD4LNd8_UPD = 1008,
    VLD4LNq16 = 1009,
    VLD4LNq16Pseudo = 1010,
    VLD4LNq16Pseudo_UPD = 1011,
    VLD4LNq16_UPD = 1012,
    VLD4LNq32 = 1013,
    VLD4LNq32Pseudo = 1014,
    VLD4LNq32Pseudo_UPD = 1015,
    VLD4LNq32_UPD = 1016,
    VLD4d16 = 1017,
    VLD4d16Pseudo = 1018,
    VLD4d16Pseudo_UPD = 1019,
    VLD4d16_UPD = 1020,
    VLD4d32 = 1021,
    VLD4d32Pseudo = 1022,
    VLD4d32Pseudo_UPD = 1023,
    VLD4d32_UPD = 1024,
    VLD4d8 = 1025,
    VLD4d8Pseudo = 1026,
    VLD4d8Pseudo_UPD = 1027,
    VLD4d8_UPD = 1028,
    VLD4q16 = 1029,
    VLD4q16Pseudo_UPD = 1030,
    VLD4q16_UPD = 1031,
    VLD4q16oddPseudo = 1032,
    VLD4q16oddPseudo_UPD = 1033,
    VLD4q32 = 1034,
    VLD4q32Pseudo_UPD = 1035,
    VLD4q32_UPD = 1036,
    VLD4q32oddPseudo = 1037,
    VLD4q32oddPseudo_UPD = 1038,
    VLD4q8 = 1039,
    VLD4q8Pseudo_UPD = 1040,
    VLD4q8_UPD = 1041,
    VLD4q8oddPseudo = 1042,
    VLD4q8oddPseudo_UPD = 1043,
    VLDMDDB_UPD = 1044,
    VLDMDIA = 1045,
    VLDMDIA_UPD = 1046,
    VLDMQIA = 1047,
    VLDMSDB_UPD = 1048,
    VLDMSIA = 1049,
    VLDMSIA_UPD = 1050,
    VLDRD = 1051,
    VLDRS = 1052,
    VMAXfd = 1053,
    VMAXfq = 1054,
    VMAXsv16i8 = 1055,
    VMAXsv2i32 = 1056,
    VMAXsv4i16 = 1057,
    VMAXsv4i32 = 1058,
    VMAXsv8i16 = 1059,
    VMAXsv8i8 = 1060,
    VMAXuv16i8 = 1061,
    VMAXuv2i32 = 1062,
    VMAXuv4i16 = 1063,
    VMAXuv4i32 = 1064,
    VMAXuv8i16 = 1065,
    VMAXuv8i8 = 1066,
    VMINfd = 1067,
    VMINfq = 1068,
    VMINsv16i8 = 1069,
    VMINsv2i32 = 1070,
    VMINsv4i16 = 1071,
    VMINsv4i32 = 1072,
    VMINsv8i16 = 1073,
    VMINsv8i8 = 1074,
    VMINuv16i8 = 1075,
    VMINuv2i32 = 1076,
    VMINuv4i16 = 1077,
    VMINuv4i32 = 1078,
    VMINuv8i16 = 1079,
    VMINuv8i8 = 1080,
    VMLAD = 1081,
    VMLALslsv2i32 = 1082,
    VMLALslsv4i16 = 1083,
    VMLALsluv2i32 = 1084,
    VMLALsluv4i16 = 1085,
    VMLALsv2i64 = 1086,
    VMLALsv4i32 = 1087,
    VMLALsv8i16 = 1088,
    VMLALuv2i64 = 1089,
    VMLALuv4i32 = 1090,
    VMLALuv8i16 = 1091,
    VMLAS = 1092,
    VMLAfd = 1093,
    VMLAfq = 1094,
    VMLAslfd = 1095,
    VMLAslfq = 1096,
    VMLAslv2i32 = 1097,
    VMLAslv4i16 = 1098,
    VMLAslv4i32 = 1099,
    VMLAslv8i16 = 1100,
    VMLAv16i8 = 1101,
    VMLAv2i32 = 1102,
    VMLAv4i16 = 1103,
    VMLAv4i32 = 1104,
    VMLAv8i16 = 1105,
    VMLAv8i8 = 1106,
    VMLSD = 1107,
    VMLSLslsv2i32 = 1108,
    VMLSLslsv4i16 = 1109,
    VMLSLsluv2i32 = 1110,
    VMLSLsluv4i16 = 1111,
    VMLSLsv2i64 = 1112,
    VMLSLsv4i32 = 1113,
    VMLSLsv8i16 = 1114,
    VMLSLuv2i64 = 1115,
    VMLSLuv4i32 = 1116,
    VMLSLuv8i16 = 1117,
    VMLSS = 1118,
    VMLSfd = 1119,
    VMLSfq = 1120,
    VMLSslfd = 1121,
    VMLSslfq = 1122,
    VMLSslv2i32 = 1123,
    VMLSslv4i16 = 1124,
    VMLSslv4i32 = 1125,
    VMLSslv8i16 = 1126,
    VMLSv16i8 = 1127,
    VMLSv2i32 = 1128,
    VMLSv4i16 = 1129,
    VMLSv4i32 = 1130,
    VMLSv8i16 = 1131,
    VMLSv8i8 = 1132,
    VMOVD = 1133,
    VMOVDRR = 1134,
    VMOVDcc = 1135,
    VMOVLsv2i64 = 1136,
    VMOVLsv4i32 = 1137,
    VMOVLsv8i16 = 1138,
    VMOVLuv2i64 = 1139,
    VMOVLuv4i32 = 1140,
    VMOVLuv8i16 = 1141,
    VMOVNv2i32 = 1142,
    VMOVNv4i16 = 1143,
    VMOVNv8i8 = 1144,
    VMOVRRD = 1145,
    VMOVRRS = 1146,
    VMOVRS = 1147,
    VMOVS = 1148,
    VMOVSR = 1149,
    VMOVSRR = 1150,
    VMOVScc = 1151,
    VMOVv16i8 = 1152,
    VMOVv1i64 = 1153,
    VMOVv2i32 = 1154,
    VMOVv2i64 = 1155,
    VMOVv4i16 = 1156,
    VMOVv4i32 = 1157,
    VMOVv8i16 = 1158,
    VMOVv8i8 = 1159,
    VMRS = 1160,
    VMRS_FPEXC = 1161,
    VMRS_FPSID = 1162,
    VMSR = 1163,
    VMSR_FPEXC = 1164,
    VMSR_FPSID = 1165,
    VMULD = 1166,
    VMULLp = 1167,
    VMULLslsv2i32 = 1168,
    VMULLslsv4i16 = 1169,
    VMULLsluv2i32 = 1170,
    VMULLsluv4i16 = 1171,
    VMULLsv2i64 = 1172,
    VMULLsv4i32 = 1173,
    VMULLsv8i16 = 1174,
    VMULLuv2i64 = 1175,
    VMULLuv4i32 = 1176,
    VMULLuv8i16 = 1177,
    VMULS = 1178,
    VMULfd = 1179,
    VMULfq = 1180,
    VMULpd = 1181,
    VMULpq = 1182,
    VMULslfd = 1183,
    VMULslfq = 1184,
    VMULslv2i32 = 1185,
    VMULslv4i16 = 1186,
    VMULslv4i32 = 1187,
    VMULslv8i16 = 1188,
    VMULv16i8 = 1189,
    VMULv2i32 = 1190,
    VMULv4i16 = 1191,
    VMULv4i32 = 1192,
    VMULv8i16 = 1193,
    VMULv8i8 = 1194,
    VMVNd = 1195,
    VMVNq = 1196,
    VMVNv2i32 = 1197,
    VMVNv4i16 = 1198,
    VMVNv4i32 = 1199,
    VMVNv8i16 = 1200,
    VNEGD = 1201,
    VNEGS = 1202,
    VNEGf32q = 1203,
    VNEGfd = 1204,
    VNEGs16d = 1205,
    VNEGs16q = 1206,
    VNEGs32d = 1207,
    VNEGs32q = 1208,
    VNEGs8d = 1209,
    VNEGs8q = 1210,
    VNMLAD = 1211,
    VNMLAS = 1212,
    VNMLSD = 1213,
    VNMLSS = 1214,
    VNMULD = 1215,
    VNMULS = 1216,
    VORNd = 1217,
    VORNq = 1218,
    VORRd = 1219,
    VORRiv2i32 = 1220,
    VORRiv4i16 = 1221,
    VORRiv4i32 = 1222,
    VORRiv8i16 = 1223,
    VORRq = 1224,
    VPADALsv16i8 = 1225,
    VPADALsv2i32 = 1226,
    VPADALsv4i16 = 1227,
    VPADALsv4i32 = 1228,
    VPADALsv8i16 = 1229,
    VPADALsv8i8 = 1230,
    VPADALuv16i8 = 1231,
    VPADALuv2i32 = 1232,
    VPADALuv4i16 = 1233,
    VPADALuv4i32 = 1234,
    VPADALuv8i16 = 1235,
    VPADALuv8i8 = 1236,
    VPADDLsv16i8 = 1237,
    VPADDLsv2i32 = 1238,
    VPADDLsv4i16 = 1239,
    VPADDLsv4i32 = 1240,
    VPADDLsv8i16 = 1241,
    VPADDLsv8i8 = 1242,
    VPADDLuv16i8 = 1243,
    VPADDLuv2i32 = 1244,
    VPADDLuv4i16 = 1245,
    VPADDLuv4i32 = 1246,
    VPADDLuv8i16 = 1247,
    VPADDLuv8i8 = 1248,
    VPADDf = 1249,
    VPADDi16 = 1250,
    VPADDi32 = 1251,
    VPADDi8 = 1252,
    VPMAXf = 1253,
    VPMAXs16 = 1254,
    VPMAXs32 = 1255,
    VPMAXs8 = 1256,
    VPMAXu16 = 1257,
    VPMAXu32 = 1258,
    VPMAXu8 = 1259,
    VPMINf = 1260,
    VPMINs16 = 1261,
    VPMINs32 = 1262,
    VPMINs8 = 1263,
    VPMINu16 = 1264,
    VPMINu32 = 1265,
    VPMINu8 = 1266,
    VQABSv16i8 = 1267,
    VQABSv2i32 = 1268,
    VQABSv4i16 = 1269,
    VQABSv4i32 = 1270,
    VQABSv8i16 = 1271,
    VQABSv8i8 = 1272,
    VQADDsv16i8 = 1273,
    VQADDsv1i64 = 1274,
    VQADDsv2i32 = 1275,
    VQADDsv2i64 = 1276,
    VQADDsv4i16 = 1277,
    VQADDsv4i32 = 1278,
    VQADDsv8i16 = 1279,
    VQADDsv8i8 = 1280,
    VQADDuv16i8 = 1281,
    VQADDuv1i64 = 1282,
    VQADDuv2i32 = 1283,
    VQADDuv2i64 = 1284,
    VQADDuv4i16 = 1285,
    VQADDuv4i32 = 1286,
    VQADDuv8i16 = 1287,
    VQADDuv8i8 = 1288,
    VQDMLALslv2i32 = 1289,
    VQDMLALslv4i16 = 1290,
    VQDMLALv2i64 = 1291,
    VQDMLALv4i32 = 1292,
    VQDMLSLslv2i32 = 1293,
    VQDMLSLslv4i16 = 1294,
    VQDMLSLv2i64 = 1295,
    VQDMLSLv4i32 = 1296,
    VQDMULHslv2i32 = 1297,
    VQDMULHslv4i16 = 1298,
    VQDMULHslv4i32 = 1299,
    VQDMULHslv8i16 = 1300,
    VQDMULHv2i32 = 1301,
    VQDMULHv4i16 = 1302,
    VQDMULHv4i32 = 1303,
    VQDMULHv8i16 = 1304,
    VQDMULLslv2i32 = 1305,
    VQDMULLslv4i16 = 1306,
    VQDMULLv2i64 = 1307,
    VQDMULLv4i32 = 1308,
    VQMOVNsuv2i32 = 1309,
    VQMOVNsuv4i16 = 1310,
    VQMOVNsuv8i8 = 1311,
    VQMOVNsv2i32 = 1312,
    VQMOVNsv4i16 = 1313,
    VQMOVNsv8i8 = 1314,
    VQMOVNuv2i32 = 1315,
    VQMOVNuv4i16 = 1316,
    VQMOVNuv8i8 = 1317,
    VQNEGv16i8 = 1318,
    VQNEGv2i32 = 1319,
    VQNEGv4i16 = 1320,
    VQNEGv4i32 = 1321,
    VQNEGv8i16 = 1322,
    VQNEGv8i8 = 1323,
    VQRDMULHslv2i32 = 1324,
    VQRDMULHslv4i16 = 1325,
    VQRDMULHslv4i32 = 1326,
    VQRDMULHslv8i16 = 1327,
    VQRDMULHv2i32 = 1328,
    VQRDMULHv4i16 = 1329,
    VQRDMULHv4i32 = 1330,
    VQRDMULHv8i16 = 1331,
    VQRSHLsv16i8 = 1332,
    VQRSHLsv1i64 = 1333,
    VQRSHLsv2i32 = 1334,
    VQRSHLsv2i64 = 1335,
    VQRSHLsv4i16 = 1336,
    VQRSHLsv4i32 = 1337,
    VQRSHLsv8i16 = 1338,
    VQRSHLsv8i8 = 1339,
    VQRSHLuv16i8 = 1340,
    VQRSHLuv1i64 = 1341,
    VQRSHLuv2i32 = 1342,
    VQRSHLuv2i64 = 1343,
    VQRSHLuv4i16 = 1344,
    VQRSHLuv4i32 = 1345,
    VQRSHLuv8i16 = 1346,
    VQRSHLuv8i8 = 1347,
    VQRSHRNsv2i32 = 1348,
    VQRSHRNsv4i16 = 1349,
    VQRSHRNsv8i8 = 1350,
    VQRSHRNuv2i32 = 1351,
    VQRSHRNuv4i16 = 1352,
    VQRSHRNuv8i8 = 1353,
    VQRSHRUNv2i32 = 1354,
    VQRSHRUNv4i16 = 1355,
    VQRSHRUNv8i8 = 1356,
    VQSHLsiv16i8 = 1357,
    VQSHLsiv1i64 = 1358,
    VQSHLsiv2i32 = 1359,
    VQSHLsiv2i64 = 1360,
    VQSHLsiv4i16 = 1361,
    VQSHLsiv4i32 = 1362,
    VQSHLsiv8i16 = 1363,
    VQSHLsiv8i8 = 1364,
    VQSHLsuv16i8 = 1365,
    VQSHLsuv1i64 = 1366,
    VQSHLsuv2i32 = 1367,
    VQSHLsuv2i64 = 1368,
    VQSHLsuv4i16 = 1369,
    VQSHLsuv4i32 = 1370,
    VQSHLsuv8i16 = 1371,
    VQSHLsuv8i8 = 1372,
    VQSHLsv16i8 = 1373,
    VQSHLsv1i64 = 1374,
    VQSHLsv2i32 = 1375,
    VQSHLsv2i64 = 1376,
    VQSHLsv4i16 = 1377,
    VQSHLsv4i32 = 1378,
    VQSHLsv8i16 = 1379,
    VQSHLsv8i8 = 1380,
    VQSHLuiv16i8 = 1381,
    VQSHLuiv1i64 = 1382,
    VQSHLuiv2i32 = 1383,
    VQSHLuiv2i64 = 1384,
    VQSHLuiv4i16 = 1385,
    VQSHLuiv4i32 = 1386,
    VQSHLuiv8i16 = 1387,
    VQSHLuiv8i8 = 1388,
    VQSHLuv16i8 = 1389,
    VQSHLuv1i64 = 1390,
    VQSHLuv2i32 = 1391,
    VQSHLuv2i64 = 1392,
    VQSHLuv4i16 = 1393,
    VQSHLuv4i32 = 1394,
    VQSHLuv8i16 = 1395,
    VQSHLuv8i8 = 1396,
    VQSHRNsv2i32 = 1397,
    VQSHRNsv4i16 = 1398,
    VQSHRNsv8i8 = 1399,
    VQSHRNuv2i32 = 1400,
    VQSHRNuv4i16 = 1401,
    VQSHRNuv8i8 = 1402,
    VQSHRUNv2i32 = 1403,
    VQSHRUNv4i16 = 1404,
    VQSHRUNv8i8 = 1405,
    VQSUBsv16i8 = 1406,
    VQSUBsv1i64 = 1407,
    VQSUBsv2i32 = 1408,
    VQSUBsv2i64 = 1409,
    VQSUBsv4i16 = 1410,
    VQSUBsv4i32 = 1411,
    VQSUBsv8i16 = 1412,
    VQSUBsv8i8 = 1413,
    VQSUBuv16i8 = 1414,
    VQSUBuv1i64 = 1415,
    VQSUBuv2i32 = 1416,
    VQSUBuv2i64 = 1417,
    VQSUBuv4i16 = 1418,
    VQSUBuv4i32 = 1419,
    VQSUBuv8i16 = 1420,
    VQSUBuv8i8 = 1421,
    VRADDHNv2i32 = 1422,
    VRADDHNv4i16 = 1423,
    VRADDHNv8i8 = 1424,
    VRECPEd = 1425,
    VRECPEfd = 1426,
    VRECPEfq = 1427,
    VRECPEq = 1428,
    VRECPSfd = 1429,
    VRECPSfq = 1430,
    VREV16d8 = 1431,
    VREV16q8 = 1432,
    VREV32d16 = 1433,
    VREV32d8 = 1434,
    VREV32q16 = 1435,
    VREV32q8 = 1436,
    VREV64d16 = 1437,
    VREV64d32 = 1438,
    VREV64d8 = 1439,
    VREV64q16 = 1440,
    VREV64q32 = 1441,
    VREV64q8 = 1442,
    VRHADDsv16i8 = 1443,
    VRHADDsv2i32 = 1444,
    VRHADDsv4i16 = 1445,
    VRHADDsv4i32 = 1446,
    VRHADDsv8i16 = 1447,
    VRHADDsv8i8 = 1448,
    VRHADDuv16i8 = 1449,
    VRHADDuv2i32 = 1450,
    VRHADDuv4i16 = 1451,
    VRHADDuv4i32 = 1452,
    VRHADDuv8i16 = 1453,
    VRHADDuv8i8 = 1454,
    VRSHLsv16i8 = 1455,
    VRSHLsv1i64 = 1456,
    VRSHLsv2i32 = 1457,
    VRSHLsv2i64 = 1458,
    VRSHLsv4i16 = 1459,
    VRSHLsv4i32 = 1460,
    VRSHLsv8i16 = 1461,
    VRSHLsv8i8 = 1462,
    VRSHLuv16i8 = 1463,
    VRSHLuv1i64 = 1464,
    VRSHLuv2i32 = 1465,
    VRSHLuv2i64 = 1466,
    VRSHLuv4i16 = 1467,
    VRSHLuv4i32 = 1468,
    VRSHLuv8i16 = 1469,
    VRSHLuv8i8 = 1470,
    VRSHRNv2i32 = 1471,
    VRSHRNv4i16 = 1472,
    VRSHRNv8i8 = 1473,
    VRSHRsv16i8 = 1474,
    VRSHRsv1i64 = 1475,
    VRSHRsv2i32 = 1476,
    VRSHRsv2i64 = 1477,
    VRSHRsv4i16 = 1478,
    VRSHRsv4i32 = 1479,
    VRSHRsv8i16 = 1480,
    VRSHRsv8i8 = 1481,
    VRSHRuv16i8 = 1482,
    VRSHRuv1i64 = 1483,
    VRSHRuv2i32 = 1484,
    VRSHRuv2i64 = 1485,
    VRSHRuv4i16 = 1486,
    VRSHRuv4i32 = 1487,
    VRSHRuv8i16 = 1488,
    VRSHRuv8i8 = 1489,
    VRSQRTEd = 1490,
    VRSQRTEfd = 1491,
    VRSQRTEfq = 1492,
    VRSQRTEq = 1493,
    VRSQRTSfd = 1494,
    VRSQRTSfq = 1495,
    VRSRAsv16i8 = 1496,
    VRSRAsv1i64 = 1497,
    VRSRAsv2i32 = 1498,
    VRSRAsv2i64 = 1499,
    VRSRAsv4i16 = 1500,
    VRSRAsv4i32 = 1501,
    VRSRAsv8i16 = 1502,
    VRSRAsv8i8 = 1503,
    VRSRAuv16i8 = 1504,
    VRSRAuv1i64 = 1505,
    VRSRAuv2i32 = 1506,
    VRSRAuv2i64 = 1507,
    VRSRAuv4i16 = 1508,
    VRSRAuv4i32 = 1509,
    VRSRAuv8i16 = 1510,
    VRSRAuv8i8 = 1511,
    VRSUBHNv2i32 = 1512,
    VRSUBHNv4i16 = 1513,
    VRSUBHNv8i8 = 1514,
    VSETLNi16 = 1515,
    VSETLNi32 = 1516,
    VSETLNi8 = 1517,
    VSHLLi16 = 1518,
    VSHLLi32 = 1519,
    VSHLLi8 = 1520,
    VSHLLsv2i64 = 1521,
    VSHLLsv4i32 = 1522,
    VSHLLsv8i16 = 1523,
    VSHLLuv2i64 = 1524,
    VSHLLuv4i32 = 1525,
    VSHLLuv8i16 = 1526,
    VSHLiv16i8 = 1527,
    VSHLiv1i64 = 1528,
    VSHLiv2i32 = 1529,
    VSHLiv2i64 = 1530,
    VSHLiv4i16 = 1531,
    VSHLiv4i32 = 1532,
    VSHLiv8i16 = 1533,
    VSHLiv8i8 = 1534,
    VSHLsv16i8 = 1535,
    VSHLsv1i64 = 1536,
    VSHLsv2i32 = 1537,
    VSHLsv2i64 = 1538,
    VSHLsv4i16 = 1539,
    VSHLsv4i32 = 1540,
    VSHLsv8i16 = 1541,
    VSHLsv8i8 = 1542,
    VSHLuv16i8 = 1543,
    VSHLuv1i64 = 1544,
    VSHLuv2i32 = 1545,
    VSHLuv2i64 = 1546,
    VSHLuv4i16 = 1547,
    VSHLuv4i32 = 1548,
    VSHLuv8i16 = 1549,
    VSHLuv8i8 = 1550,
    VSHRNv2i32 = 1551,
    VSHRNv4i16 = 1552,
    VSHRNv8i8 = 1553,
    VSHRsv16i8 = 1554,
    VSHRsv1i64 = 1555,
    VSHRsv2i32 = 1556,
    VSHRsv2i64 = 1557,
    VSHRsv4i16 = 1558,
    VSHRsv4i32 = 1559,
    VSHRsv8i16 = 1560,
    VSHRsv8i8 = 1561,
    VSHRuv16i8 = 1562,
    VSHRuv1i64 = 1563,
    VSHRuv2i32 = 1564,
    VSHRuv2i64 = 1565,
    VSHRuv4i16 = 1566,
    VSHRuv4i32 = 1567,
    VSHRuv8i16 = 1568,
    VSHRuv8i8 = 1569,
    VSHTOD = 1570,
    VSHTOS = 1571,
    VSITOD = 1572,
    VSITOS = 1573,
    VSLIv16i8 = 1574,
    VSLIv1i64 = 1575,
    VSLIv2i32 = 1576,
    VSLIv2i64 = 1577,
    VSLIv4i16 = 1578,
    VSLIv4i32 = 1579,
    VSLIv8i16 = 1580,
    VSLIv8i8 = 1581,
    VSLTOD = 1582,
    VSLTOS = 1583,
    VSQRTD = 1584,
    VSQRTS = 1585,
    VSRAsv16i8 = 1586,
    VSRAsv1i64 = 1587,
    VSRAsv2i32 = 1588,
    VSRAsv2i64 = 1589,
    VSRAsv4i16 = 1590,
    VSRAsv4i32 = 1591,
    VSRAsv8i16 = 1592,
    VSRAsv8i8 = 1593,
    VSRAuv16i8 = 1594,
    VSRAuv1i64 = 1595,
    VSRAuv2i32 = 1596,
    VSRAuv2i64 = 1597,
    VSRAuv4i16 = 1598,
    VSRAuv4i32 = 1599,
    VSRAuv8i16 = 1600,
    VSRAuv8i8 = 1601,
    VSRIv16i8 = 1602,
    VSRIv1i64 = 1603,
    VSRIv2i32 = 1604,
    VSRIv2i64 = 1605,
    VSRIv4i16 = 1606,
    VSRIv4i32 = 1607,
    VSRIv8i16 = 1608,
    VSRIv8i8 = 1609,
    VST1LNd16 = 1610,
    VST1LNd16_UPD = 1611,
    VST1LNd32 = 1612,
    VST1LNd32_UPD = 1613,
    VST1LNd8 = 1614,
    VST1LNd8_UPD = 1615,
    VST1LNq16Pseudo = 1616,
    VST1LNq16Pseudo_UPD = 1617,
    VST1LNq32Pseudo = 1618,
    VST1LNq32Pseudo_UPD = 1619,
    VST1LNq8Pseudo = 1620,
    VST1LNq8Pseudo_UPD = 1621,
    VST1d16 = 1622,
    VST1d16Q = 1623,
    VST1d16Q_UPD = 1624,
    VST1d16T = 1625,
    VST1d16T_UPD = 1626,
    VST1d16_UPD = 1627,
    VST1d32 = 1628,
    VST1d32Q = 1629,
    VST1d32Q_UPD = 1630,
    VST1d32T = 1631,
    VST1d32T_UPD = 1632,
    VST1d32_UPD = 1633,
    VST1d64 = 1634,
    VST1d64Q = 1635,
    VST1d64QPseudo = 1636,
    VST1d64QPseudo_UPD = 1637,
    VST1d64Q_UPD = 1638,
    VST1d64T = 1639,
    VST1d64TPseudo = 1640,
    VST1d64TPseudo_UPD = 1641,
    VST1d64T_UPD = 1642,
    VST1d64_UPD = 1643,
    VST1d8 = 1644,
    VST1d8Q = 1645,
    VST1d8Q_UPD = 1646,
    VST1d8T = 1647,
    VST1d8T_UPD = 1648,
    VST1d8_UPD = 1649,
    VST1q16 = 1650,
    VST1q16Pseudo = 1651,
    VST1q16Pseudo_UPD = 1652,
    VST1q16_UPD = 1653,
    VST1q32 = 1654,
    VST1q32Pseudo = 1655,
    VST1q32Pseudo_UPD = 1656,
    VST1q32_UPD = 1657,
    VST1q64 = 1658,
    VST1q64Pseudo = 1659,
    VST1q64Pseudo_UPD = 1660,
    VST1q64_UPD = 1661,
    VST1q8 = 1662,
    VST1q8Pseudo = 1663,
    VST1q8Pseudo_UPD = 1664,
    VST1q8_UPD = 1665,
    VST2LNd16 = 1666,
    VST2LNd16Pseudo = 1667,
    VST2LNd16Pseudo_UPD = 1668,
    VST2LNd16_UPD = 1669,
    VST2LNd32 = 1670,
    VST2LNd32Pseudo = 1671,
    VST2LNd32Pseudo_UPD = 1672,
    VST2LNd32_UPD = 1673,
    VST2LNd8 = 1674,
    VST2LNd8Pseudo = 1675,
    VST2LNd8Pseudo_UPD = 1676,
    VST2LNd8_UPD = 1677,
    VST2LNq16 = 1678,
    VST2LNq16Pseudo = 1679,
    VST2LNq16Pseudo_UPD = 1680,
    VST2LNq16_UPD = 1681,
    VST2LNq32 = 1682,
    VST2LNq32Pseudo = 1683,
    VST2LNq32Pseudo_UPD = 1684,
    VST2LNq32_UPD = 1685,
    VST2b16 = 1686,
    VST2b16_UPD = 1687,
    VST2b32 = 1688,
    VST2b32_UPD = 1689,
    VST2b8 = 1690,
    VST2b8_UPD = 1691,
    VST2d16 = 1692,
    VST2d16Pseudo = 1693,
    VST2d16Pseudo_UPD = 1694,
    VST2d16_UPD = 1695,
    VST2d32 = 1696,
    VST2d32Pseudo = 1697,
    VST2d32Pseudo_UPD = 1698,
    VST2d32_UPD = 1699,
    VST2d8 = 1700,
    VST2d8Pseudo = 1701,
    VST2d8Pseudo_UPD = 1702,
    VST2d8_UPD = 1703,
    VST2q16 = 1704,
    VST2q16Pseudo = 1705,
    VST2q16Pseudo_UPD = 1706,
    VST2q16_UPD = 1707,
    VST2q32 = 1708,
    VST2q32Pseudo = 1709,
    VST2q32Pseudo_UPD = 1710,
    VST2q32_UPD = 1711,
    VST2q8 = 1712,
    VST2q8Pseudo = 1713,
    VST2q8Pseudo_UPD = 1714,
    VST2q8_UPD = 1715,
    VST3LNd16 = 1716,
    VST3LNd16Pseudo = 1717,
    VST3LNd16Pseudo_UPD = 1718,
    VST3LNd16_UPD = 1719,
    VST3LNd32 = 1720,
    VST3LNd32Pseudo = 1721,
    VST3LNd32Pseudo_UPD = 1722,
    VST3LNd32_UPD = 1723,
    VST3LNd8 = 1724,
    VST3LNd8Pseudo = 1725,
    VST3LNd8Pseudo_UPD = 1726,
    VST3LNd8_UPD = 1727,
    VST3LNq16 = 1728,
    VST3LNq16Pseudo = 1729,
    VST3LNq16Pseudo_UPD = 1730,
    VST3LNq16_UPD = 1731,
    VST3LNq32 = 1732,
    VST3LNq32Pseudo = 1733,
    VST3LNq32Pseudo_UPD = 1734,
    VST3LNq32_UPD = 1735,
    VST3d16 = 1736,
    VST3d16Pseudo = 1737,
    VST3d16Pseudo_UPD = 1738,
    VST3d16_UPD = 1739,
    VST3d32 = 1740,
    VST3d32Pseudo = 1741,
    VST3d32Pseudo_UPD = 1742,
    VST3d32_UPD = 1743,
    VST3d8 = 1744,
    VST3d8Pseudo = 1745,
    VST3d8Pseudo_UPD = 1746,
    VST3d8_UPD = 1747,
    VST3q16 = 1748,
    VST3q16Pseudo_UPD = 1749,
    VST3q16_UPD = 1750,
    VST3q16oddPseudo = 1751,
    VST3q16oddPseudo_UPD = 1752,
    VST3q32 = 1753,
    VST3q32Pseudo_UPD = 1754,
    VST3q32_UPD = 1755,
    VST3q32oddPseudo = 1756,
    VST3q32oddPseudo_UPD = 1757,
    VST3q8 = 1758,
    VST3q8Pseudo_UPD = 1759,
    VST3q8_UPD = 1760,
    VST3q8oddPseudo = 1761,
    VST3q8oddPseudo_UPD = 1762,
    VST4LNd16 = 1763,
    VST4LNd16Pseudo = 1764,
    VST4LNd16Pseudo_UPD = 1765,
    VST4LNd16_UPD = 1766,
    VST4LNd32 = 1767,
    VST4LNd32Pseudo = 1768,
    VST4LNd32Pseudo_UPD = 1769,
    VST4LNd32_UPD = 1770,
    VST4LNd8 = 1771,
    VST4LNd8Pseudo = 1772,
    VST4LNd8Pseudo_UPD = 1773,
    VST4LNd8_UPD = 1774,
    VST4LNq16 = 1775,
    VST4LNq16Pseudo = 1776,
    VST4LNq16Pseudo_UPD = 1777,
    VST4LNq16_UPD = 1778,
    VST4LNq32 = 1779,
    VST4LNq32Pseudo = 1780,
    VST4LNq32Pseudo_UPD = 1781,
    VST4LNq32_UPD = 1782,
    VST4d16 = 1783,
    VST4d16Pseudo = 1784,
    VST4d16Pseudo_UPD = 1785,
    VST4d16_UPD = 1786,
    VST4d32 = 1787,
    VST4d32Pseudo = 1788,
    VST4d32Pseudo_UPD = 1789,
    VST4d32_UPD = 1790,
    VST4d8 = 1791,
    VST4d8Pseudo = 1792,
    VST4d8Pseudo_UPD = 1793,
    VST4d8_UPD = 1794,
    VST4q16 = 1795,
    VST4q16Pseudo_UPD = 1796,
    VST4q16_UPD = 1797,
    VST4q16oddPseudo = 1798,
    VST4q16oddPseudo_UPD = 1799,
    VST4q32 = 1800,
    VST4q32Pseudo_UPD = 1801,
    VST4q32_UPD = 1802,
    VST4q32oddPseudo = 1803,
    VST4q32oddPseudo_UPD = 1804,
    VST4q8 = 1805,
    VST4q8Pseudo_UPD = 1806,
    VST4q8_UPD = 1807,
    VST4q8oddPseudo = 1808,
    VST4q8oddPseudo_UPD = 1809,
    VSTMDDB_UPD = 1810,
    VSTMDIA = 1811,
    VSTMDIA_UPD = 1812,
    VSTMQIA = 1813,
    VSTMSDB_UPD = 1814,
    VSTMSIA = 1815,
    VSTMSIA_UPD = 1816,
    VSTRD = 1817,
    VSTRS = 1818,
    VSUBD = 1819,
    VSUBHNv2i32 = 1820,
    VSUBHNv4i16 = 1821,
    VSUBHNv8i8 = 1822,
    VSUBLsv2i64 = 1823,
    VSUBLsv4i32 = 1824,
    VSUBLsv8i16 = 1825,
    VSUBLuv2i64 = 1826,
    VSUBLuv4i32 = 1827,
    VSUBLuv8i16 = 1828,
    VSUBS = 1829,
    VSUBWsv2i64 = 1830,
    VSUBWsv4i32 = 1831,
    VSUBWsv8i16 = 1832,
    VSUBWuv2i64 = 1833,
    VSUBWuv4i32 = 1834,
    VSUBWuv8i16 = 1835,
    VSUBfd = 1836,
    VSUBfq = 1837,
    VSUBv16i8 = 1838,
    VSUBv1i64 = 1839,
    VSUBv2i32 = 1840,
    VSUBv2i64 = 1841,
    VSUBv4i16 = 1842,
    VSUBv4i32 = 1843,
    VSUBv8i16 = 1844,
    VSUBv8i8 = 1845,
    VSWPd = 1846,
    VSWPq = 1847,
    VTBL1 = 1848,
    VTBL2 = 1849,
    VTBL2Pseudo = 1850,
    VTBL3 = 1851,
    VTBL3Pseudo = 1852,
    VTBL4 = 1853,
    VTBL4Pseudo = 1854,
    VTBX1 = 1855,
    VTBX2 = 1856,
    VTBX2Pseudo = 1857,
    VTBX3 = 1858,
    VTBX3Pseudo = 1859,
    VTBX4 = 1860,
    VTBX4Pseudo = 1861,
    VTOSHD = 1862,
    VTOSHS = 1863,
    VTOSIRD = 1864,
    VTOSIRS = 1865,
    VTOSIZD = 1866,
    VTOSIZS = 1867,
    VTOSLD = 1868,
    VTOSLS = 1869,
    VTOUHD = 1870,
    VTOUHS = 1871,
    VTOUIRD = 1872,
    VTOUIRS = 1873,
    VTOUIZD = 1874,
    VTOUIZS = 1875,
    VTOULD = 1876,
    VTOULS = 1877,
    VTRNd16 = 1878,
    VTRNd32 = 1879,
    VTRNd8 = 1880,
    VTRNq16 = 1881,
    VTRNq32 = 1882,
    VTRNq8 = 1883,
    VTSTv16i8 = 1884,
    VTSTv2i32 = 1885,
    VTSTv4i16 = 1886,
    VTSTv4i32 = 1887,
    VTSTv8i16 = 1888,
    VTSTv8i8 = 1889,
    VUHTOD = 1890,
    VUHTOS = 1891,
    VUITOD = 1892,
    VUITOS = 1893,
    VULTOD = 1894,
    VULTOS = 1895,
    VUZPd16 = 1896,
    VUZPd32 = 1897,
    VUZPd8 = 1898,
    VUZPq16 = 1899,
    VUZPq32 = 1900,
    VUZPq8 = 1901,
    VZIPd16 = 1902,
    VZIPd32 = 1903,
    VZIPd8 = 1904,
    VZIPq16 = 1905,
    VZIPq32 = 1906,
    VZIPq8 = 1907,
    WFE = 1908,
    WFI = 1909,
    YIELD = 1910,
    t2ABS = 1911,
    t2ADCri = 1912,
    t2ADCrr = 1913,
    t2ADCrs = 1914,
    t2ADDSri = 1915,
    t2ADDSrr = 1916,
    t2ADDSrs = 1917,
    t2ADDri = 1918,
    t2ADDri12 = 1919,
    t2ADDrr = 1920,
    t2ADDrs = 1921,
    t2ADR = 1922,
    t2ANDri = 1923,
    t2ANDrr = 1924,
    t2ANDrs = 1925,
    t2ASRri = 1926,
    t2ASRrr = 1927,
    t2B = 1928,
    t2BFC = 1929,
    t2BFI = 1930,
    t2BICri = 1931,
    t2BICrr = 1932,
    t2BICrs = 1933,
    t2BR_JT = 1934,
    t2BXJ = 1935,
    t2Bcc = 1936,
    t2CDP2 = 1937,
    t2CLREX = 1938,
    t2CLZ = 1939,
    t2CMNzri = 1940,
    t2CMNzrr = 1941,
    t2CMNzrs = 1942,
    t2CMPri = 1943,
    t2CMPrr = 1944,
    t2CMPrs = 1945,
    t2CPS1p = 1946,
    t2CPS2p = 1947,
    t2CPS3p = 1948,
    t2DBG = 1949,
    t2DMB = 1950,
    t2DSB = 1951,
    t2EORri = 1952,
    t2EORrr = 1953,
    t2EORrs = 1954,
    t2ISB = 1955,
    t2IT = 1956,
    t2Int_eh_sjlj_setjmp = 1957,
    t2Int_eh_sjlj_setjmp_nofp = 1958,
    t2LDC2L_OFFSET = 1959,
    t2LDC2L_OPTION = 1960,
    t2LDC2L_POST = 1961,
    t2LDC2L_PRE = 1962,
    t2LDC2_OFFSET = 1963,
    t2LDC2_OPTION = 1964,
    t2LDC2_POST = 1965,
    t2LDC2_PRE = 1966,
    t2LDCL_OFFSET = 1967,
    t2LDCL_OPTION = 1968,
    t2LDCL_POST = 1969,
    t2LDCL_PRE = 1970,
    t2LDC_OFFSET = 1971,
    t2LDC_OPTION = 1972,
    t2LDC_POST = 1973,
    t2LDC_PRE = 1974,
    t2LDMDB = 1975,
    t2LDMDB_UPD = 1976,
    t2LDMIA = 1977,
    t2LDMIA_RET = 1978,
    t2LDMIA_UPD = 1979,
    t2LDRBT = 1980,
    t2LDRB_POST = 1981,
    t2LDRB_PRE = 1982,
    t2LDRBi12 = 1983,
    t2LDRBi8 = 1984,
    t2LDRBpci = 1985,
    t2LDRBs = 1986,
    t2LDRD_POST = 1987,
    t2LDRD_PRE = 1988,
    t2LDRDi8 = 1989,
    t2LDREX = 1990,
    t2LDREXB = 1991,
    t2LDREXD = 1992,
    t2LDREXH = 1993,
    t2LDRHT = 1994,
    t2LDRH_POST = 1995,
    t2LDRH_PRE = 1996,
    t2LDRHi12 = 1997,
    t2LDRHi8 = 1998,
    t2LDRHpci = 1999,
    t2LDRHs = 2000,
    t2LDRSBT = 2001,
    t2LDRSB_POST = 2002,
    t2LDRSB_PRE = 2003,
    t2LDRSBi12 = 2004,
    t2LDRSBi8 = 2005,
    t2LDRSBpci = 2006,
    t2LDRSBs = 2007,
    t2LDRSHT = 2008,
    t2LDRSH_POST = 2009,
    t2LDRSH_PRE = 2010,
    t2LDRSHi12 = 2011,
    t2LDRSHi8 = 2012,
    t2LDRSHpci = 2013,
    t2LDRSHs = 2014,
    t2LDRT = 2015,
    t2LDR_POST = 2016,
    t2LDR_PRE = 2017,
    t2LDRi12 = 2018,
    t2LDRi8 = 2019,
    t2LDRpci = 2020,
    t2LDRpci_pic = 2021,
    t2LDRs = 2022,
    t2LEApcrel = 2023,
    t2LEApcrelJT = 2024,
    t2LSLri = 2025,
    t2LSLrr = 2026,
    t2LSRri = 2027,
    t2LSRrr = 2028,
    t2MCR = 2029,
    t2MCR2 = 2030,
    t2MCRR = 2031,
    t2MCRR2 = 2032,
    t2MLA = 2033,
    t2MLS = 2034,
    t2MOVCCasr = 2035,
    t2MOVCCi = 2036,
    t2MOVCCi16 = 2037,
    t2MOVCCi32imm = 2038,
    t2MOVCClsl = 2039,
    t2MOVCClsr = 2040,
    t2MOVCCr = 2041,
    t2MOVCCror = 2042,
    t2MOVTi16 = 2043,
    t2MOVTi16_ga_pcrel = 2044,
    t2MOV_ga_dyn = 2045,
    t2MOV_ga_pcrel = 2046,
    t2MOVi = 2047,
    t2MOVi16 = 2048,
    t2MOVi16_ga_pcrel = 2049,
    t2MOVi32imm = 2050,
    t2MOVr = 2051,
    t2MOVsra_flag = 2052,
    t2MOVsrl_flag = 2053,
    t2MRC = 2054,
    t2MRC2 = 2055,
    t2MRRC = 2056,
    t2MRRC2 = 2057,
    t2MRS_AR = 2058,
    t2MRS_M = 2059,
    t2MRSsys_AR = 2060,
    t2MSR_AR = 2061,
    t2MSR_M = 2062,
    t2MUL = 2063,
    t2MVNCCi = 2064,
    t2MVNi = 2065,
    t2MVNr = 2066,
    t2MVNs = 2067,
    t2NOP = 2068,
    t2ORNri = 2069,
    t2ORNrr = 2070,
    t2ORNrs = 2071,
    t2ORRri = 2072,
    t2ORRrr = 2073,
    t2ORRrs = 2074,
    t2PKHBT = 2075,
    t2PKHTB = 2076,
    t2PLDWi12 = 2077,
    t2PLDWi8 = 2078,
    t2PLDWs = 2079,
    t2PLDi12 = 2080,
    t2PLDi8 = 2081,
    t2PLDs = 2082,
    t2PLIi12 = 2083,
    t2PLIi8 = 2084,
    t2PLIs = 2085,
    t2QADD = 2086,
    t2QADD16 = 2087,
    t2QADD8 = 2088,
    t2QASX = 2089,
    t2QDADD = 2090,
    t2QDSUB = 2091,
    t2QSAX = 2092,
    t2QSUB = 2093,
    t2QSUB16 = 2094,
    t2QSUB8 = 2095,
    t2RBIT = 2096,
    t2REV = 2097,
    t2REV16 = 2098,
    t2REVSH = 2099,
    t2RFEDB = 2100,
    t2RFEDBW = 2101,
    t2RFEIA = 2102,
    t2RFEIAW = 2103,
    t2RORri = 2104,
    t2RORrr = 2105,
    t2RRX = 2106,
    t2RSBSri = 2107,
    t2RSBSrs = 2108,
    t2RSBri = 2109,
    t2RSBrr = 2110,
    t2RSBrs = 2111,
    t2SADD16 = 2112,
    t2SADD8 = 2113,
    t2SASX = 2114,
    t2SBCri = 2115,
    t2SBCrr = 2116,
    t2SBCrs = 2117,
    t2SBFX = 2118,
    t2SDIV = 2119,
    t2SEL = 2120,
    t2SEV = 2121,
    t2SHADD16 = 2122,
    t2SHADD8 = 2123,
    t2SHASX = 2124,
    t2SHSAX = 2125,
    t2SHSUB16 = 2126,
    t2SHSUB8 = 2127,
    t2SMC = 2128,
    t2SMLABB = 2129,
    t2SMLABT = 2130,
    t2SMLAD = 2131,
    t2SMLADX = 2132,
    t2SMLAL = 2133,
    t2SMLALBB = 2134,
    t2SMLALBT = 2135,
    t2SMLALD = 2136,
    t2SMLALDX = 2137,
    t2SMLALTB = 2138,
    t2SMLALTT = 2139,
    t2SMLATB = 2140,
    t2SMLATT = 2141,
    t2SMLAWB = 2142,
    t2SMLAWT = 2143,
    t2SMLSD = 2144,
    t2SMLSDX = 2145,
    t2SMLSLD = 2146,
    t2SMLSLDX = 2147,
    t2SMMLA = 2148,
    t2SMMLAR = 2149,
    t2SMMLS = 2150,
    t2SMMLSR = 2151,
    t2SMMUL = 2152,
    t2SMMULR = 2153,
    t2SMUAD = 2154,
    t2SMUADX = 2155,
    t2SMULBB = 2156,
    t2SMULBT = 2157,
    t2SMULL = 2158,
    t2SMULTB = 2159,
    t2SMULTT = 2160,
    t2SMULWB = 2161,
    t2SMULWT = 2162,
    t2SMUSD = 2163,
    t2SMUSDX = 2164,
    t2SRSDB = 2165,
    t2SRSDB_UPD = 2166,
    t2SRSIA = 2167,
    t2SRSIA_UPD = 2168,
    t2SSAT = 2169,
    t2SSAT16 = 2170,
    t2SSAX = 2171,
    t2SSUB16 = 2172,
    t2SSUB8 = 2173,
    t2STC2L_OFFSET = 2174,
    t2STC2L_OPTION = 2175,
    t2STC2L_POST = 2176,
    t2STC2L_PRE = 2177,
    t2STC2_OFFSET = 2178,
    t2STC2_OPTION = 2179,
    t2STC2_POST = 2180,
    t2STC2_PRE = 2181,
    t2STCL_OFFSET = 2182,
    t2STCL_OPTION = 2183,
    t2STCL_POST = 2184,
    t2STCL_PRE = 2185,
    t2STC_OFFSET = 2186,
    t2STC_OPTION = 2187,
    t2STC_POST = 2188,
    t2STC_PRE = 2189,
    t2STMDB = 2190,
    t2STMDB_UPD = 2191,
    t2STMIA = 2192,
    t2STMIA_UPD = 2193,
    t2STRBT = 2194,
    t2STRB_POST = 2195,
    t2STRB_PRE = 2196,
    t2STRB_preidx = 2197,
    t2STRBi12 = 2198,
    t2STRBi8 = 2199,
    t2STRBs = 2200,
    t2STRD_POST = 2201,
    t2STRD_PRE = 2202,
    t2STRDi8 = 2203,
    t2STREX = 2204,
    t2STREXB = 2205,
    t2STREXD = 2206,
    t2STREXH = 2207,
    t2STRHT = 2208,
    t2STRH_POST = 2209,
    t2STRH_PRE = 2210,
    t2STRH_preidx = 2211,
    t2STRHi12 = 2212,
    t2STRHi8 = 2213,
    t2STRHs = 2214,
    t2STRT = 2215,
    t2STR_POST = 2216,
    t2STR_PRE = 2217,
    t2STR_preidx = 2218,
    t2STRi12 = 2219,
    t2STRi8 = 2220,
    t2STRs = 2221,
    t2SUBSri = 2222,
    t2SUBSrr = 2223,
    t2SUBSrs = 2224,
    t2SUBri = 2225,
    t2SUBri12 = 2226,
    t2SUBrr = 2227,
    t2SUBrs = 2228,
    t2SXTAB = 2229,
    t2SXTAB16 = 2230,
    t2SXTAH = 2231,
    t2SXTB = 2232,
    t2SXTB16 = 2233,
    t2SXTH = 2234,
    t2TBB = 2235,
    t2TBB_JT = 2236,
    t2TBH = 2237,
    t2TBH_JT = 2238,
    t2TEQri = 2239,
    t2TEQrr = 2240,
    t2TEQrs = 2241,
    t2TSTri = 2242,
    t2TSTrr = 2243,
    t2TSTrs = 2244,
    t2UADD16 = 2245,
    t2UADD8 = 2246,
    t2UASX = 2247,
    t2UBFX = 2248,
    t2UDIV = 2249,
    t2UHADD16 = 2250,
    t2UHADD8 = 2251,
    t2UHASX = 2252,
    t2UHSAX = 2253,
    t2UHSUB16 = 2254,
    t2UHSUB8 = 2255,
    t2UMAAL = 2256,
    t2UMLAL = 2257,
    t2UMULL = 2258,
    t2UQADD16 = 2259,
    t2UQADD8 = 2260,
    t2UQASX = 2261,
    t2UQSAX = 2262,
    t2UQSUB16 = 2263,
    t2UQSUB8 = 2264,
    t2USAD8 = 2265,
    t2USADA8 = 2266,
    t2USAT = 2267,
    t2USAT16 = 2268,
    t2USAX = 2269,
    t2USUB16 = 2270,
    t2USUB8 = 2271,
    t2UXTAB = 2272,
    t2UXTAB16 = 2273,
    t2UXTAH = 2274,
    t2UXTB = 2275,
    t2UXTB16 = 2276,
    t2UXTH = 2277,
    t2WFE = 2278,
    t2WFI = 2279,
    t2YIELD = 2280,
    tADC = 2281,
    tADDhirr = 2282,
    tADDi3 = 2283,
    tADDi8 = 2284,
    tADDrSP = 2285,
    tADDrSPi = 2286,
    tADDrr = 2287,
    tADDspi = 2288,
    tADDspr = 2289,
    tADJCALLSTACKDOWN = 2290,
    tADJCALLSTACKUP = 2291,
    tADR = 2292,
    tAND = 2293,
    tASRri = 2294,
    tASRrr = 2295,
    tB = 2296,
    tBIC = 2297,
    tBKPT = 2298,
    tBL = 2299,
    tBLXi = 2300,
    tBLXi_r9 = 2301,
    tBLXr = 2302,
    tBLXr_r9 = 2303,
    tBLr9 = 2304,
    tBRIND = 2305,
    tBR_JTr = 2306,
    tBX = 2307,
    tBX_CALL = 2308,
    tBX_RET = 2309,
    tBX_RET_vararg = 2310,
    tBXr9_CALL = 2311,
    tBcc = 2312,
    tBfar = 2313,
    tCBNZ = 2314,
    tCBZ = 2315,
    tCDP = 2316,
    tCMNz = 2317,
    tCMPhir = 2318,
    tCMPi8 = 2319,
    tCMPr = 2320,
    tCPS = 2321,
    tEOR = 2322,
    tInt_eh_sjlj_longjmp = 2323,
    tInt_eh_sjlj_setjmp = 2324,
    tLDMIA = 2325,
    tLDMIA_UPD = 2326,
    tLDRBi = 2327,
    tLDRBr = 2328,
    tLDRHi = 2329,
    tLDRHr = 2330,
    tLDRSB = 2331,
    tLDRSH = 2332,
    tLDRi = 2333,
    tLDRpci = 2334,
    tLDRpciDIS = 2335,
    tLDRpci_pic = 2336,
    tLDRr = 2337,
    tLDRspi = 2338,
    tLEApcrel = 2339,
    tLEApcrelJT = 2340,
    tLSLri = 2341,
    tLSLrr = 2342,
    tLSRri = 2343,
    tLSRrr = 2344,
    tMOVCCr_pseudo = 2345,
    tMOVSr = 2346,
    tMOVi8 = 2347,
    tMOVr = 2348,
    tMUL = 2349,
    tMVN = 2350,
    tNOP = 2351,
    tORR = 2352,
    tPICADD = 2353,
    tPOP = 2354,
    tPOP_RET = 2355,
    tPUSH = 2356,
    tREV = 2357,
    tREV16 = 2358,
    tREVSH = 2359,
    tROR = 2360,
    tRSB = 2361,
    tSBC = 2362,
    tSETEND = 2363,
    tSEV = 2364,
    tSTMIA_UPD = 2365,
    tSTRBi = 2366,
    tSTRBr = 2367,
    tSTRHi = 2368,
    tSTRHr = 2369,
    tSTRi = 2370,
    tSTRr = 2371,
    tSTRspi = 2372,
    tSUBi3 = 2373,
    tSUBi8 = 2374,
    tSUBrr = 2375,
    tSUBspi = 2376,
    tSVC = 2377,
    tSXTB = 2378,
    tSXTH = 2379,
    tTAILJMPd = 2380,
    tTAILJMPdND = 2381,
    tTAILJMPr = 2382,
    tTAILJMPrND = 2383,
    tTPsoft = 2384,
    tTRAP = 2385,
    tTST = 2386,
    tUXTB = 2387,
    tUXTH = 2388,
    tWFE = 2389,
    tWFI = 2390,
    tYIELD = 2391,
    INSTRUCTION_LIST_END = 2392
  };
}
}



namespace llvm {
namespace ARM {
enum {
  FeatureAvoidPartialCPSR = 1ULL << 0,
  FeatureD16 = 1ULL << 1,
  FeatureDB = 1ULL << 2,
  FeatureDSPThumb2 = 1ULL << 3,
  FeatureFP16 = 1ULL << 4,
  FeatureHWDiv = 1ULL << 5,
  FeatureHasSlowFPVMLx = 1ULL << 6,
  FeatureMClass = 1ULL << 7,
  FeatureMP = 1ULL << 8,
  FeatureNEON = 1ULL << 9,
  FeatureNEONForFP = 1ULL << 10,
  FeatureNoARM = 1ULL << 11,
  FeaturePref32BitThumb = 1ULL << 12,
  FeatureSlowFPBrcc = 1ULL << 13,
  FeatureT2XtPk = 1ULL << 14,
  FeatureThumb2 = 1ULL << 15,
  FeatureVFP2 = 1ULL << 16,
  FeatureVFP3 = 1ULL << 17,
  FeatureVFPOnlySP = 1ULL << 18,
  FeatureVMLxForwarding = 1ULL << 19,
  HasV4TOps = 1ULL << 20,
  HasV5TEOps = 1ULL << 21,
  HasV5TOps = 1ULL << 22,
  HasV6Ops = 1ULL << 23,
  HasV6T2Ops = 1ULL << 24,
  HasV7Ops = 1ULL << 25,
  ModeNaCl = 1ULL << 26,
  ModeThumb = 1ULL << 27,
  ProcA8 = 1ULL << 28,
  ProcA9 = 1ULL << 29
};
}
}

extern "C" {
void __assert(const char *, const char *, int, const char *) __attribute__((__noreturn__));
}




namespace llvm {
  template<typename T>
  class SmallVectorImpl;
  class APInt;
  class StringRef {
  public:
    typedef const char *iterator;
    typedef const char *const_iterator;
    static const size_t npos = ~size_t(0);
    typedef size_t size_type;

  private:

    const char *Data;


    size_t Length;




    static size_t min(size_t a, size_t b) { return a < b ? a : b; }
    static size_t max(size_t a, size_t b) { return a > b ? a : b; }



    static int compareMemory(const char *Lhs, const char *Rhs, size_t Length) {
      if (Length == 0) { return 0; }
      return ::memcmp(Lhs,Rhs,Length);
    }

  public:




                 StringRef() : Data(0), Length(0) {}


                 StringRef(const char *Str)
      : Data(Str) {
        ((Str && "StringRef cannot be built from a NULL argument") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringRef.h", 67, "Str && \"StringRef cannot be built from a NULL argument\""));
        Length = ::strlen(Str);
      }


                 StringRef(const char *data, size_t length)
      : Data(data), Length(length) {
        (((data || length == 0) && "StringRef cannot be built from a NULL argument with non-null length") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringRef.h", 75, "(data || length == 0) && \"StringRef cannot be built from a NULL argument with non-null length\""));

      }


                 StringRef(const std::string &Str)
      : Data(Str.data()), Length(Str.length()) {}





    iterator begin() const { return Data; }

    iterator end() const { return Data + Length; }







    const char *data() const { return Data; }


    bool empty() const { return Length == 0; }


    size_t size() const { return Length; }


    char front() const {
      ((!empty()) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringRef.h", 106, "!empty()"));
      return Data[0];
    }


    char back() const {
      ((!empty()) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringRef.h", 112, "!empty()"));
      return Data[Length-1];
    }



    bool equals(StringRef RHS) const {
      return (Length == RHS.Length &&
              compareMemory(Data, RHS.Data, RHS.Length) == 0);
    }


    bool equals_lower(StringRef RHS) const {
      return Length == RHS.Length && compare_lower(RHS) == 0;
    }



    int compare(StringRef RHS) const {

      if (int Res = compareMemory(Data, RHS.Data, min(Length, RHS.Length)))
        return Res < 0 ? -1 : 1;


      if (Length == RHS.Length)
        return 0;
      return Length < RHS.Length ? -1 : 1;
    }


    int compare_lower(StringRef RHS) const;



    int compare_numeric(StringRef RHS) const;
    unsigned edit_distance(StringRef Other, bool AllowReplacements = true,
                           unsigned MaxEditDistance = 0);


    std::string str() const {
      if (Data == 0) return std::string();
      return std::string(Data, Length);
    }





    char operator[](size_t Index) const {
      ((Index < Length && "Invalid index!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringRef.h", 180, "Index < Length && \"Invalid index!\""));
      return Data[Index];
    }





    operator std::string() const {
      return str();
    }






    bool startswith(StringRef Prefix) const {
      return Length >= Prefix.Length &&
             compareMemory(Data, Prefix.Data, Prefix.Length) == 0;
    }


    bool endswith(StringRef Suffix) const {
      return Length >= Suffix.Length &&
        compareMemory(end() - Suffix.Length, Suffix.Data, Suffix.Length) == 0;
    }
    size_t find(char C, size_t From = 0) const {
      for (size_t i = min(From, Length), e = Length; i != e; ++i)
        if (Data[i] == C)
          return i;
      return npos;
    }





    size_t find(StringRef Str, size_t From = 0) const;





    size_t rfind(char C, size_t From = npos) const {
      From = min(From, Length);
      size_t i = From;
      while (i != 0) {
        --i;
        if (Data[i] == C)
          return i;
      }
      return npos;
    }





    size_t rfind(StringRef Str) const;



    size_type find_first_of(char C, size_t From = 0) const {
      return find(C, From);
    }





    size_type find_first_of(StringRef Chars, size_t From = 0) const;



    size_type find_first_not_of(char C, size_t From = 0) const;





    size_type find_first_not_of(StringRef Chars, size_t From = 0) const;



    size_type find_last_of(char C, size_t From = npos) const {
      return rfind(C, From);
    }





    size_type find_last_of(StringRef Chars, size_t From = npos) const;






    size_t count(char C) const {
      size_t Count = 0;
      for (size_t i = 0, e = Length; i != e; ++i)
        if (Data[i] == C)
          ++Count;
      return Count;
    }



    size_t count(StringRef Str) const;
    bool getAsInteger(unsigned Radix, long long &Result) const;
    bool getAsInteger(unsigned Radix, unsigned long long &Result) const;
    bool getAsInteger(unsigned Radix, int &Result) const;
    bool getAsInteger(unsigned Radix, unsigned &Result) const;
    bool getAsInteger(unsigned Radix, APInt &Result) const;
    StringRef substr(size_t Start, size_t N = npos) const {
      Start = min(Start, Length);
      return StringRef(Data + Start, min(N, Length - Start));
    }
    StringRef slice(size_t Start, size_t End) const {
      Start = min(Start, Length);
      End = min(max(Start, End), Length);
      return StringRef(Data + Start, End - Start);
    }
    std::pair<StringRef, StringRef> split(char Separator) const {
      size_t Idx = find(Separator);
      if (Idx == npos)
        return std::make_pair(*this, StringRef());
      return std::make_pair(slice(0, Idx), slice(Idx+1, npos));
    }
    std::pair<StringRef, StringRef> split(StringRef Separator) const {
      size_t Idx = find(Separator);
      if (Idx == npos)
        return std::make_pair(*this, StringRef());
      return std::make_pair(slice(0, Idx), slice(Idx + Separator.size(), npos));
    }
    void split(SmallVectorImpl<StringRef> &A,
               StringRef Separator, int MaxSplit = -1,
               bool KeepEmpty = true) const;
    std::pair<StringRef, StringRef> rsplit(char Separator) const {
      size_t Idx = rfind(Separator);
      if (Idx == npos)
        return std::make_pair(*this, StringRef());
      return std::make_pair(slice(0, Idx), slice(Idx+1, npos));
    }


  };




  inline bool operator==(StringRef LHS, StringRef RHS) {
    return LHS.equals(RHS);
  }

  inline bool operator!=(StringRef LHS, StringRef RHS) {
    return !(LHS == RHS);
  }

  inline bool operator<(StringRef LHS, StringRef RHS) {
    return LHS.compare(RHS) == -1;
  }

  inline bool operator<=(StringRef LHS, StringRef RHS) {
    return LHS.compare(RHS) != 1;
  }

  inline bool operator>(StringRef LHS, StringRef RHS) {
    return LHS.compare(RHS) == 1;
  }

  inline bool operator>=(StringRef LHS, StringRef RHS) {
    return LHS.compare(RHS) != -1;
  }

  inline std::string &operator+=(std::string &buffer, llvm::StringRef string) {
    return buffer.append(string.data(), string.size());
  }




  template <typename T> struct isPodLike;
  template <> struct isPodLike<StringRef> { static const bool value = true; };

}


namespace llvm {
  class Twine;


  typedef void (*fatal_error_handler_t)(void *user_data,
                                        const std::string& reason);
  void install_fatal_error_handler(fatal_error_handler_t handler,
                                   void *user_data = 0);




  void remove_fatal_error_handler();




  struct ScopedFatalErrorHandler {
    explicit ScopedFatalErrorHandler(fatal_error_handler_t handler,
                                     void *user_data = 0) {
      install_fatal_error_handler(handler, user_data);
    }

    ~ScopedFatalErrorHandler() { remove_fatal_error_handler(); }
  };
  __attribute__((noreturn)) void report_fatal_error(const char *reason);
  __attribute__((noreturn)) void report_fatal_error(const std::string &reason);
  __attribute__((noreturn)) void report_fatal_error(StringRef reason);
  __attribute__((noreturn)) void report_fatal_error(const Twine &reason);




  __attribute__((noreturn)) void llvm_unreachable_internal(const char *msg=0,
                                                         const char *file=0,
                                                         unsigned line=0);
}

namespace llvm {


namespace ARMCC {


  enum CondCodes {
    EQ,
    NE,
    HS,
    LO,
    MI,
    PL,
    VS,
    VC,
    HI,
    LS,
    GE,
    LT,
    GT,
    LE,
    AL
  };

  inline static CondCodes getOppositeCondition(CondCodes CC) {
    switch (CC) {
    default: ::llvm::llvm_unreachable_internal("Unknown condition code", "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h", 49);
    case EQ: return NE;
    case NE: return EQ;
    case HS: return LO;
    case LO: return HS;
    case MI: return PL;
    case PL: return MI;
    case VS: return VC;
    case VC: return VS;
    case HI: return LS;
    case LS: return HI;
    case GE: return LT;
    case LT: return GE;
    case GT: return LE;
    case LE: return GT;
    }
  }
}

inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
  switch (CC) {
  default: ::llvm::llvm_unreachable_internal("Unknown condition code", "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h", 70);
  case ARMCC::EQ: return "eq";
  case ARMCC::NE: return "ne";
  case ARMCC::HS: return "hs";
  case ARMCC::LO: return "lo";
  case ARMCC::MI: return "mi";
  case ARMCC::PL: return "pl";
  case ARMCC::VS: return "vs";
  case ARMCC::VC: return "vc";
  case ARMCC::HI: return "hi";
  case ARMCC::LS: return "ls";
  case ARMCC::GE: return "ge";
  case ARMCC::LT: return "lt";
  case ARMCC::GT: return "gt";
  case ARMCC::LE: return "le";
  case ARMCC::AL: return "al";
  }
}

namespace ARM_PROC {
  enum IMod {
    IE = 2,
    ID = 3
  };

  enum IFlags {
    F = 1,
    I = 2,
    A = 4
  };

  inline static const char *IFlagsToString(unsigned val) {
    switch (val) {
    default: ::llvm::llvm_unreachable_internal("Unknown iflags operand", "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h", 103);
    case F: return "f";
    case I: return "i";
    case A: return "a";
    }
  }

  inline static const char *IModToString(unsigned val) {
    switch (val) {
    default: ::llvm::llvm_unreachable_internal("Unknown imod operand", "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h", 112);
    case IE: return "ie";
    case ID: return "id";
    }
  }
}

namespace ARM_MB {


  enum MemBOpt {
    SY = 15,
    ST = 14,
    ISH = 11,
    ISHST = 10,
    NSH = 7,
    NSHST = 6,
    OSH = 3,
    OSHST = 2
  };

  inline static const char *MemBOptToString(unsigned val) {
    switch (val) {
    default: ::llvm::llvm_unreachable_internal("Unknown memory operation", "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h", 135);
    case SY: return "sy";
    case ST: return "st";
    case ISH: return "ish";
    case ISHST: return "ishst";
    case NSH: return "nsh";
    case NSHST: return "nshst";
    case OSH: return "osh";
    case OSHST: return "oshst";
    }
  }
}



inline static unsigned getARMRegisterNumbering(unsigned Reg) {
  using namespace ARM;
  switch (Reg) {
  default:
    ::llvm::llvm_unreachable_internal("Unknown ARM register!", "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h", 154);
  case R0: case S0: case D0: case Q0: return 0;
  case R1: case S1: case D1: case Q1: return 1;
  case R2: case S2: case D2: case Q2: return 2;
  case R3: case S3: case D3: case Q3: return 3;
  case R4: case S4: case D4: case Q4: return 4;
  case R5: case S5: case D5: case Q5: return 5;
  case R6: case S6: case D6: case Q6: return 6;
  case R7: case S7: case D7: case Q7: return 7;
  case R8: case S8: case D8: case Q8: return 8;
  case R9: case S9: case D9: case Q9: return 9;
  case R10: case S10: case D10: case Q10: return 10;
  case R11: case S11: case D11: case Q11: return 11;
  case R12: case S12: case D12: case Q12: return 12;
  case SP: case S13: case D13: case Q13: return 13;
  case LR: case S14: case D14: case Q14: return 14;
  case PC: case S15: case D15: case Q15: return 15;

  case S16: case D16: return 16;
  case S17: case D17: return 17;
  case S18: case D18: return 18;
  case S19: case D19: return 19;
  case S20: case D20: return 20;
  case S21: case D21: return 21;
  case S22: case D22: return 22;
  case S23: case D23: return 23;
  case S24: case D24: return 24;
  case S25: case D25: return 25;
  case S26: case D26: return 26;
  case S27: case D27: return 27;
  case S28: case D28: return 28;
  case S29: case D29: return 29;
  case S30: case D30: return 30;
  case S31: case D31: return 31;
  }
}



static inline bool isARMLowRegister(unsigned Reg) {
  using namespace ARM;
  switch (Reg) {
  case R0: case R1: case R2: case R3:
  case R4: case R5: case R6: case R7:
    return true;
  default:
    return false;
  }
}




namespace ARMII {


  enum IndexMode {
    IndexModeNone = 0,
    IndexModePre = 1,
    IndexModePost = 2,
    IndexModeUpd = 3
  };


  enum AddrMode {
    AddrModeNone = 0,
    AddrMode1 = 1,
    AddrMode2 = 2,
    AddrMode3 = 3,
    AddrMode4 = 4,
    AddrMode5 = 5,
    AddrMode6 = 6,
    AddrModeT1_1 = 7,
    AddrModeT1_2 = 8,
    AddrModeT1_4 = 9,
    AddrModeT1_s = 10,
    AddrModeT2_i12 = 11,
    AddrModeT2_i8 = 12,
    AddrModeT2_so = 13,
    AddrModeT2_pc = 14,
    AddrModeT2_i8s4 = 15,
    AddrMode_i12 = 16
  };

  inline static const char *AddrModeToString(AddrMode addrmode) {
    switch (addrmode) {
    default: ::llvm::llvm_unreachable_internal("Unknown memory operation", "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h", 240);
    case AddrModeNone: return "AddrModeNone";
    case AddrMode1: return "AddrMode1";
    case AddrMode2: return "AddrMode2";
    case AddrMode3: return "AddrMode3";
    case AddrMode4: return "AddrMode4";
    case AddrMode5: return "AddrMode5";
    case AddrMode6: return "AddrMode6";
    case AddrModeT1_1: return "AddrModeT1_1";
    case AddrModeT1_2: return "AddrModeT1_2";
    case AddrModeT1_4: return "AddrModeT1_4";
    case AddrModeT1_s: return "AddrModeT1_s";
    case AddrModeT2_i12: return "AddrModeT2_i12";
    case AddrModeT2_i8: return "AddrModeT2_i8";
    case AddrModeT2_so: return "AddrModeT2_so";
    case AddrModeT2_pc: return "AddrModeT2_pc";
    case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
    case AddrMode_i12: return "AddrMode_i12";
    }
  }


  enum TOF {



    MO_NO_FLAG,



    MO_LO16,



    MO_HI16,





    MO_LO16_NONLAZY,




    MO_HI16_NONLAZY,





    MO_LO16_NONLAZY_PIC,





    MO_HI16_NONLAZY_PIC,



    MO_PLT
  };

  enum {





    AddrModeMask = 0x1f,




    IndexModeShift = 5,
    IndexModeMask = 3 << IndexModeShift,




    FormShift = 7,
    FormMask = 0x3f << FormShift,


    Pseudo = 0 << FormShift,


    MulFrm = 1 << FormShift,


    BrFrm = 2 << FormShift,
    BrMiscFrm = 3 << FormShift,


    DPFrm = 4 << FormShift,
    DPSoRegFrm = 5 << FormShift,


    LdFrm = 6 << FormShift,
    StFrm = 7 << FormShift,
    LdMiscFrm = 8 << FormShift,
    StMiscFrm = 9 << FormShift,
    LdStMulFrm = 10 << FormShift,

    LdStExFrm = 11 << FormShift,


    ArithMiscFrm = 12 << FormShift,
    SatFrm = 13 << FormShift,


    ExtFrm = 14 << FormShift,


    VFPUnaryFrm = 15 << FormShift,
    VFPBinaryFrm = 16 << FormShift,
    VFPConv1Frm = 17 << FormShift,
    VFPConv2Frm = 18 << FormShift,
    VFPConv3Frm = 19 << FormShift,
    VFPConv4Frm = 20 << FormShift,
    VFPConv5Frm = 21 << FormShift,
    VFPLdStFrm = 22 << FormShift,
    VFPLdStMulFrm = 23 << FormShift,
    VFPMiscFrm = 24 << FormShift,


    ThumbFrm = 25 << FormShift,


    MiscFrm = 26 << FormShift,


    NGetLnFrm = 27 << FormShift,
    NSetLnFrm = 28 << FormShift,
    NDupFrm = 29 << FormShift,
    NLdStFrm = 30 << FormShift,
    N1RegModImmFrm= 31 << FormShift,
    N2RegFrm = 32 << FormShift,
    NVCVTFrm = 33 << FormShift,
    NVDupLnFrm = 34 << FormShift,
    N2RegVShLFrm = 35 << FormShift,
    N2RegVShRFrm = 36 << FormShift,
    N3RegFrm = 37 << FormShift,
    N3RegVShFrm = 38 << FormShift,
    NVExtFrm = 39 << FormShift,
    NVMulSLFrm = 40 << FormShift,
    NVTBLFrm = 41 << FormShift,






    UnaryDP = 1 << 13,



    Xform16Bit = 1 << 14,





    ThumbArithFlagSetting = 1 << 18,



    DomainShift = 15,
    DomainMask = 7 << DomainShift,
    DomainGeneral = 0 << DomainShift,
    DomainVFP = 1 << DomainShift,
    DomainNEON = 2 << DomainShift,
    DomainNEONA8 = 4 << DomainShift,







    ShiftTypeShift = 4,

    M_BitShift = 5,
    ShiftImmShift = 5,
    ShiftShift = 7,
    N_BitShift = 7,
    ImmHiShift = 8,
    SoRotImmShift = 8,
    RegRsShift = 8,
    ExtRotImmShift = 10,
    RegRdLoShift = 12,
    RegRdShift = 12,
    RegRdHiShift = 16,
    RegRnShift = 16,
    S_BitShift = 20,
    W_BitShift = 21,
    AM3_I_BitShift = 22,
    D_BitShift = 22,
    U_BitShift = 23,
    P_BitShift = 24,
    I_BitShift = 25,
    CondShift = 28
  };

}

}



namespace llvm {


  namespace Reloc {
    enum Model { Default, Static, PIC_, DynamicNoPIC };
  }


  namespace CodeModel {
    enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
  }

}

namespace llvm {

  class MCCodeGenInfo {


    Reloc::Model RelocationModel;



    CodeModel::Model CMModel;

  public:
    void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
                           CodeModel::Model CM = CodeModel::Default);

    Reloc::Model getRelocationModel() const { return RelocationModel; }

    CodeModel::Model getCodeModel() const { return CMModel; }
  };
}




namespace llvm {

class InstrItineraryData;
class JITCodeEmitter;
class MCAsmInfo;
class MCCodeGenInfo;
class MCContext;
class Pass;
class PassManager;
class PassManagerBase;
class Target;
class TargetData;
class TargetELFWriterInfo;
class TargetFrameLowering;
class TargetInstrInfo;
class TargetIntrinsicInfo;
class TargetJITInfo;
class TargetLowering;
class TargetRegisterInfo;
class TargetSelectionDAGInfo;
class TargetSubtargetInfo;
class formatted_raw_ostream;
class raw_ostream;


namespace CodeGenOpt {
  enum Level {
    None,
    Less,
    Default,
    Aggressive
  };
}

namespace Sched {
  enum Preference {
    None,
    Latency,
    RegPressure,
    Hybrid,
    ILP
  };
}







class TargetMachine {
  TargetMachine(const TargetMachine &);
  void operator=(const TargetMachine &);
protected:
  TargetMachine(const Target &T, StringRef TargetTriple,
                StringRef CPU, StringRef FS);



  virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }


  const Target &TheTarget;



  std::string TargetTriple;
  std::string TargetCPU;
  std::string TargetFS;


  const MCCodeGenInfo *CodeGenInfo;



  const MCAsmInfo *AsmInfo;

  unsigned MCRelaxAll : 1;
  unsigned MCNoExecStack : 1;
  unsigned MCSaveTempLabels : 1;
  unsigned MCUseLoc : 1;
  unsigned MCUseCFI : 1;

public:
  virtual ~TargetMachine();

  const Target &getTarget() const { return TheTarget; }

  const StringRef getTargetTriple() const { return TargetTriple; }
  const StringRef getTargetCPU() const { return TargetCPU; }
  const StringRef getTargetFeatureString() const { return TargetFS; }







  virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
  virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
  virtual const TargetLowering *getTargetLowering() const { return 0; }
  virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
  virtual const TargetData *getTargetData() const { return 0; }



  const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }




  template<typename STC> const STC &getSubtarget() const {
    return *static_cast<const STC*>(getSubtargetImpl());
  }





  virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }




  virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }




  virtual TargetJITInfo *getJITInfo() { return 0; }




  virtual const InstrItineraryData *getInstrItineraryData() const {
    return 0;
  }




  virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }



  bool hasMCRelaxAll() const { return MCRelaxAll; }



  void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }



  bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }



  void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }


  bool hasMCNoExecStack() const { return MCNoExecStack; }


  void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }


  bool hasMCUseLoc() const { return MCUseLoc; }


  void setMCUseLoc(bool Value) { MCUseLoc = Value; }


  bool hasMCUseCFI() const { return MCUseCFI; }


  void setMCUseCFI(bool Value) { MCUseCFI = Value; }



  Reloc::Model getRelocationModel() const;



  CodeModel::Model getCodeModel() const;



  static bool getAsmVerbosityDefault();



  static void setAsmVerbosityDefault(bool);



  static bool getDataSections();



  static bool getFunctionSections();


  static void setDataSections(bool);



  static void setFunctionSections(bool);




  enum CodeGenFileType {
    CGFT_AssemblyFile,
    CGFT_ObjectFile,
    CGFT_Null
  };



  virtual bool getEnableTailMergeDefault() const { return true; }





  virtual bool addPassesToEmitFile(PassManagerBase &,
                                   formatted_raw_ostream &,
                                   CodeGenFileType,
                                   CodeGenOpt::Level,
                                   bool = true) {
    return true;
  }







  virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                          JITCodeEmitter &,
                                          CodeGenOpt::Level,
                                          bool = true) {
    return true;
  }






  virtual bool addPassesToEmitMC(PassManagerBase &,
                                 MCContext *&,
                                 raw_ostream &,
                                 CodeGenOpt::Level,
                                 bool = true) {
    return true;
  }
};




class LLVMTargetMachine : public TargetMachine {
protected:
  LLVMTargetMachine(const Target &T, StringRef TargetTriple,
                    StringRef CPU, StringRef FS,
                    Reloc::Model RM, CodeModel::Model CM);

private:



  bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
                              bool DisableVerify, MCContext *&OutCtx);

public:




  virtual bool addPassesToEmitFile(PassManagerBase &PM,
                                   formatted_raw_ostream &Out,
                                   CodeGenFileType FileType,
                                   CodeGenOpt::Level,
                                   bool DisableVerify = true);







  virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
                                          JITCodeEmitter &MCE,
                                          CodeGenOpt::Level,
                                          bool DisableVerify = true);






  virtual bool addPassesToEmitMC(PassManagerBase &PM,
                                 MCContext *&Ctx,
                                 raw_ostream &OS,
                                 CodeGenOpt::Level OptLevel,
                                 bool DisableVerify = true);





  virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
    return true;
  }



  virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
    return true;
  }




  virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
    return false;
  }





  virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
    return false;
  }





  virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
    return false;
  }




  virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
    return false;
  }





  virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
                              JITCodeEmitter &) {
    return true;
  }



  virtual bool getEnableTailMergeDefault() const { return true; }
};

}


namespace llvm {

class ARMAsmPrinter;
class ARMBaseTargetMachine;
class FunctionPass;
class JITCodeEmitter;
class MachineInstr;
class MCInst;

FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
                               CodeGenOpt::Level OptLevel);

FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
                                          JITCodeEmitter &JCE);

FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
FunctionPass *createARMExpandPseudoPass();
FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
FunctionPass *createARMConstantIslandPass();
FunctionPass *createMLxExpansionPass();
FunctionPass *createThumb2ITBlockPass();
FunctionPass *createThumb2SizeReductionPass();

void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                  ARMAsmPrinter &AP);

}
namespace llvm {
namespace sys {



inline uint16_t SwapByteOrder_16(uint16_t value) {





  uint16_t Hi = value << 8;
  uint16_t Lo = value >> 8;
  return Hi | Lo;

}



inline uint32_t SwapByteOrder_32(uint32_t value) {


  return __builtin_bswap32(value);
}



inline uint64_t SwapByteOrder_64(uint64_t value) {


  return __builtin_bswap64(value);







}

inline unsigned char SwapByteOrder(unsigned char C) { return C; }
inline signed char SwapByteOrder(signed char C) { return C; }
inline char SwapByteOrder(char C) { return C; }

inline unsigned short SwapByteOrder(unsigned short C) { return SwapByteOrder_16(C); }
inline signed short SwapByteOrder( signed short C) { return SwapByteOrder_16(C); }

inline unsigned int SwapByteOrder(unsigned int C) { return SwapByteOrder_32(C); }
inline signed int SwapByteOrder( signed int C) { return SwapByteOrder_32(C); }





inline unsigned long SwapByteOrder(unsigned long C) { return SwapByteOrder_64(C); }
inline signed long SwapByteOrder( signed long C) { return SwapByteOrder_64(C); }




inline unsigned long long SwapByteOrder(unsigned long long C) {
  return SwapByteOrder_64(C);
}
inline signed long long SwapByteOrder(signed long long C) {
  return SwapByteOrder_64(C);
}

}
}

namespace llvm {






inline uint32_t Hi_32(uint64_t Value) {
  return static_cast<uint32_t>(Value >> 32);
}


inline uint32_t Lo_32(uint64_t Value) {
  return static_cast<uint32_t>(Value);
}


template<unsigned N>
inline bool isInt(int64_t x) {
  return N >= 64 || (-((1L)<<(N-1)) <= x && x < ((1L)<<(N-1)));
}

template<>
inline bool isInt<8>(int64_t x) {
  return static_cast<int8_t>(x) == x;
}
template<>
inline bool isInt<16>(int64_t x) {
  return static_cast<int16_t>(x) == x;
}
template<>
inline bool isInt<32>(int64_t x) {
  return static_cast<int32_t>(x) == x;
}


template<unsigned N>
inline bool isUInt(uint64_t x) {
  return N >= 64 || x < ((1UL)<<N);
}

template<>
inline bool isUInt<8>(uint64_t x) {
  return static_cast<uint8_t>(x) == x;
}
template<>
inline bool isUInt<16>(uint64_t x) {
  return static_cast<uint16_t>(x) == x;
}
template<>
inline bool isUInt<32>(uint64_t x) {
  return static_cast<uint32_t>(x) == x;
}



inline bool isUIntN(unsigned N, uint64_t x) {
  return x == (x & (~0ULL >> (64 - N)));
}



inline bool isIntN(unsigned N, int64_t x) {
  return N >= 64 || (-((1L)<<(N-1)) <= x && x < ((1L)<<(N-1)));
}




inline bool isMask_32(uint32_t Value) {
  return Value && ((Value + 1) & Value) == 0;
}




inline bool isMask_64(uint64_t Value) {
  return Value && ((Value + 1) & Value) == 0;
}




inline bool isShiftedMask_32(uint32_t Value) {
  return isMask_32((Value - 1) | Value);
}



inline bool isShiftedMask_64(uint64_t Value) {
  return isMask_64((Value - 1) | Value);
}



inline bool isPowerOf2_32(uint32_t Value) {
  return Value && !(Value & (Value - 1));
}



inline bool isPowerOf2_64(uint64_t Value) {
  return Value && !(Value & (Value - int64_t(1L)));
}



inline uint16_t ByteSwap_16(uint16_t Value) {
  return sys::SwapByteOrder_16(Value);
}



inline uint32_t ByteSwap_32(uint32_t Value) {
  return sys::SwapByteOrder_32(Value);
}



inline uint64_t ByteSwap_64(uint64_t Value) {
  return sys::SwapByteOrder_64(Value);
}





inline unsigned CountLeadingZeros_32(uint32_t Value) {
  unsigned Count;



  if (!Value) return 32;

  Count = __builtin_clz(Value);
  return Count;
}





inline unsigned CountLeadingOnes_32(uint32_t Value) {
  return CountLeadingZeros_32(~Value);
}





inline unsigned CountLeadingZeros_64(uint64_t Value) {
  unsigned Count;



  if (!Value) return 64;

  Count = __builtin_clzll(Value);
  return Count;
}





inline unsigned CountLeadingOnes_64(uint64_t Value) {
  return CountLeadingZeros_64(~Value);
}





inline unsigned CountTrailingZeros_32(uint32_t Value) {

  return Value ? __builtin_ctz(Value) : 32;
}





inline unsigned CountTrailingOnes_32(uint32_t Value) {
  return CountTrailingZeros_32(~Value);
}





inline unsigned CountTrailingZeros_64(uint64_t Value) {

  return Value ? __builtin_ctzll(Value) : 64;
}





inline unsigned CountTrailingOnes_64(uint64_t Value) {
  return CountTrailingZeros_64(~Value);
}




inline unsigned CountPopulation_32(uint32_t Value) {

  return __builtin_popcount(Value);





}



inline unsigned CountPopulation_64(uint64_t Value) {

  return __builtin_popcountll(Value);






}




inline unsigned Log2_32(uint32_t Value) {
  return 31 - CountLeadingZeros_32(Value);
}



inline unsigned Log2_64(uint64_t Value) {
  return 63 - CountLeadingZeros_64(Value);
}




inline unsigned Log2_32_Ceil(uint32_t Value) {
  return 32-CountLeadingZeros_32(Value-1);
}



inline unsigned Log2_64_Ceil(uint64_t Value) {
  return 64-CountLeadingZeros_64(Value-1);
}



inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
  while (B) {
    uint64_t T = B;
    B = A % B;
    A = T;
  }
  return A;
}



inline double BitsToDouble(uint64_t Bits) {
  union {
    uint64_t L;
    double D;
  } T;
  T.L = Bits;
  return T.D;
}



inline float BitsToFloat(uint32_t Bits) {
  union {
    uint32_t I;
    float F;
  } T;
  T.I = Bits;
  return T.F;
}





inline uint64_t DoubleToBits(double Double) {
  union {
    uint64_t L;
    double D;
  } T;
  T.D = Double;
  return T.L;
}





inline uint32_t FloatToBits(float Float) {
  union {
    uint32_t I;
    float F;
  } T;
  T.F = Float;
  return T.I;
}


int IsNAN(float f);
int IsNAN(double d);


int IsInf(float f);
int IsInf(double d);



static inline uint64_t MinAlign(uint64_t A, uint64_t B) {

  return (A | B) & -(A | B);
}



static inline uint64_t NextPowerOf2(uint64_t A) {
  A |= (A >> 1);
  A |= (A >> 2);
  A |= (A >> 4);
  A |= (A >> 8);
  A |= (A >> 16);
  A |= (A >> 32);
  return A + 1;
}
inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
  return ((Value + Align - 1) / Align) * Align;
}




inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
  return RoundUpToAlignment(Value, Align) - Value;
}




inline int64_t abs64(int64_t x) {
  return (x < 0) ? -x : x;
}



template <unsigned B> inline int32_t SignExtend32(uint32_t x) {
  return int32_t(x << (32 - B)) >> (32 - B);
}



template <unsigned B> inline int64_t SignExtend64(uint64_t x) {
  return int64_t(x << (64 - B)) >> (64 - B);
}

}
namespace llvm {




template <typename T>
class PointerLikeTypeTraits {



};


template<typename T>
class PointerLikeTypeTraits<T*> {
public:
  static inline void *getAsVoidPointer(T* P) { return P; }
  static inline T *getFromVoidPointer(void *P) {
    return static_cast<T*>(P);
  }







  enum { NumLowBitsAvailable = 2 };
};


template<typename T>
class PointerLikeTypeTraits<const T*> {
  typedef PointerLikeTypeTraits<T*> NonConst;

public:
  static inline const void *getAsVoidPointer(const T* P) {
    return NonConst::getAsVoidPointer(const_cast<T*>(P));
  }
  static inline const T *getFromVoidPointer(const void *P) {
    return NonConst::getFromVoidPointer(const_cast<void*>(P));
  }
  enum { NumLowBitsAvailable = NonConst::NumLowBitsAvailable };
};


template<>
class PointerLikeTypeTraits<uintptr_t> {
public:
  static inline void *getAsVoidPointer(uintptr_t P) {
    return reinterpret_cast<void*>(P);
  }
  static inline uintptr_t getFromVoidPointer(void *P) {
    return reinterpret_cast<uintptr_t>(P);
  }

  enum { NumLowBitsAvailable = 0 };
};

}
namespace llvm {

namespace dont_use
{
    template<typename T> char is_class_helper(void(T::*)());
    template<typename T> double is_class_helper(...);
}

template <typename T>
struct is_class
{



 public:
    enum { value = sizeof(char) == sizeof(dont_use::is_class_helper<T>(0)) };
};




template <typename T>
struct isPodLike {


  static const bool value = !is_class<T>::value;
};


template<typename T, typename U>
struct isPodLike<std::pair<T, U> > {
  static const bool value = isPodLike<T>::value & isPodLike<U>::value;
};




template<typename T, typename U>
struct is_same {
  static const bool value = false;
};

template<typename T>
struct is_same<T, T> {
  static const bool value = true;
};


template<bool Cond, typename T = void>
struct enable_if_c {
  typedef T type;
};

template<typename T> struct enable_if_c<false, T> { };


template<typename Cond, typename T = void>
struct enable_if : public enable_if_c<Cond::value, T> { };

namespace dont_use {
  template<typename Base> char base_of_helper(const volatile Base*);
  template<typename Base> double base_of_helper(...);
}



template<typename Base, typename Derived>
struct is_base_of {
  static const bool value
    = is_class<Base>::value && is_class<Derived>::value &&
      sizeof(char) == sizeof(dont_use::base_of_helper<Base>((Derived*)0));
};



template <typename T> struct remove_pointer { typedef T type; };
template <typename T> struct remove_pointer<T*> { typedef T type; };
template <typename T> struct remove_pointer<T*const> { typedef T type; };
template <typename T> struct remove_pointer<T*volatile> { typedef T type; };
template <typename T> struct remove_pointer<T*const volatile> {
    typedef T type; };

template <bool, typename T, typename F>
struct conditional { typedef T type; };

template <typename T, typename F>
struct conditional<false, T, F> { typedef F type; };

}
namespace llvm {

template<typename T>
struct DenseMapInfo {




};


template<typename T>
struct DenseMapInfo<T*> {
  static inline T* getEmptyKey() {
    intptr_t Val = -1;
    Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
    return reinterpret_cast<T*>(Val);
  }
  static inline T* getTombstoneKey() {
    intptr_t Val = -2;
    Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
    return reinterpret_cast<T*>(Val);
  }
  static unsigned getHashValue(const T *PtrVal) {
    return (unsigned((uintptr_t)PtrVal) >> 4) ^
           (unsigned((uintptr_t)PtrVal) >> 9);
  }
  static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; }
};


template<> struct DenseMapInfo<char> {
  static inline char getEmptyKey() { return ~0; }
  static inline char getTombstoneKey() { return ~0 - 1; }
  static unsigned getHashValue(const char& Val) { return Val * 37U; }
  static bool isEqual(const char &LHS, const char &RHS) {
    return LHS == RHS;
  }
};


template<> struct DenseMapInfo<unsigned> {
  static inline unsigned getEmptyKey() { return ~0; }
  static inline unsigned getTombstoneKey() { return ~0U - 1; }
  static unsigned getHashValue(const unsigned& Val) { return Val * 37U; }
  static bool isEqual(const unsigned& LHS, const unsigned& RHS) {
    return LHS == RHS;
  }
};


template<> struct DenseMapInfo<unsigned long> {
  static inline unsigned long getEmptyKey() { return ~0UL; }
  static inline unsigned long getTombstoneKey() { return ~0UL - 1L; }
  static unsigned getHashValue(const unsigned long& Val) {
    return (unsigned)(Val * 37UL);
  }
  static bool isEqual(const unsigned long& LHS, const unsigned long& RHS) {
    return LHS == RHS;
  }
};


template<> struct DenseMapInfo<unsigned long long> {
  static inline unsigned long long getEmptyKey() { return ~0ULL; }
  static inline unsigned long long getTombstoneKey() { return ~0ULL - 1ULL; }
  static unsigned getHashValue(const unsigned long long& Val) {
    return (unsigned)(Val * 37ULL);
  }
  static bool isEqual(const unsigned long long& LHS,
                      const unsigned long long& RHS) {
    return LHS == RHS;
  }
};


template<> struct DenseMapInfo<int> {
  static inline int getEmptyKey() { return 0x7fffffff; }
  static inline int getTombstoneKey() { return -0x7fffffff - 1; }
  static unsigned getHashValue(const int& Val) { return (unsigned)(Val * 37U); }
  static bool isEqual(const int& LHS, const int& RHS) {
    return LHS == RHS;
  }
};


template<> struct DenseMapInfo<long> {
  static inline long getEmptyKey() {
    return (1UL << (sizeof(long) * 8 - 1)) - 1L;
  }
  static inline long getTombstoneKey() { return getEmptyKey() - 1L; }
  static unsigned getHashValue(const long& Val) {
    return (unsigned)(Val * 37UL);
  }
  static bool isEqual(const long& LHS, const long& RHS) {
    return LHS == RHS;
  }
};


template<> struct DenseMapInfo<long long> {
  static inline long long getEmptyKey() { return 0x7fffffffffffffffLL; }
  static inline long long getTombstoneKey() { return -0x7fffffffffffffffLL-1; }
  static unsigned getHashValue(const long long& Val) {
    return (unsigned)(Val * 37ULL);
  }
  static bool isEqual(const long long& LHS,
                      const long long& RHS) {
    return LHS == RHS;
  }
};


template<typename T, typename U>
struct DenseMapInfo<std::pair<T, U> > {
  typedef std::pair<T, U> Pair;
  typedef DenseMapInfo<T> FirstInfo;
  typedef DenseMapInfo<U> SecondInfo;

  static inline Pair getEmptyKey() {
    return std::make_pair(FirstInfo::getEmptyKey(),
                          SecondInfo::getEmptyKey());
  }
  static inline Pair getTombstoneKey() {
    return std::make_pair(FirstInfo::getTombstoneKey(),
                          SecondInfo::getTombstoneKey());
  }
  static unsigned getHashValue(const Pair& PairVal) {
    uint64_t key = (uint64_t)FirstInfo::getHashValue(PairVal.first) << 32
          | (uint64_t)SecondInfo::getHashValue(PairVal.second);
    key += ~(key << 32);
    key ^= (key >> 22);
    key += ~(key << 13);
    key ^= (key >> 8);
    key += (key << 3);
    key ^= (key >> 15);
    key += ~(key << 27);
    key ^= (key >> 31);
    return (unsigned)key;
  }
  static bool isEqual(const Pair &LHS, const Pair &RHS) {
    return FirstInfo::isEqual(LHS.first, RHS.first) &&
           SecondInfo::isEqual(LHS.second, RHS.second);
  }
};

}



















namespace std __attribute__ ((__visibility__ ("default"))) {


  class locale;


  template<typename _CharT>
    inline bool
    isspace(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    isprint(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    iscntrl(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    isupper(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    islower(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    isalpha(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    isdigit(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    ispunct(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    isxdigit(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    isalnum(_CharT, const locale&);

  template<typename _CharT>
    inline bool
    isgraph(_CharT, const locale&);

  template<typename _CharT>
    inline _CharT
    toupper(_CharT, const locale&);

  template<typename _CharT>
    inline _CharT
    tolower(_CharT, const locale&);


  class ctype_base;
  template<typename _CharT>
    class ctype;
  template<> class ctype<char>;

  template<> class ctype<wchar_t>;

  template<typename _CharT>
    class ctype_byname;


  class codecvt_base;
  class __enc_traits;
  template<typename _InternT, typename _ExternT, typename _StateT>
    class codecvt;
  template<> class codecvt<char, char, mbstate_t>;

  template<> class codecvt<wchar_t, char, mbstate_t>;

  template<typename _InternT, typename _ExternT, typename _StateT>
    class codecvt_byname;



  template<typename _CharT, typename _InIter = istreambuf_iterator<_CharT> >
    class num_get;
  template<typename _CharT, typename _OutIter = ostreambuf_iterator<_CharT> >
    class num_put;

  template<typename _CharT> class numpunct;
  template<typename _CharT> class numpunct_byname;


  template<typename _CharT>
    class collate;
  template<typename _CharT> class
    collate_byname;


  class time_base;
  template<typename _CharT, typename _InIter = istreambuf_iterator<_CharT> >
    class time_get;
  template<typename _CharT, typename _InIter = istreambuf_iterator<_CharT> >
    class time_get_byname;
  template<typename _CharT, typename _OutIter = ostreambuf_iterator<_CharT> >
    class time_put;
  template<typename _CharT, typename _OutIter = ostreambuf_iterator<_CharT> >
    class time_put_byname;


  class money_base;

  template<typename _CharT, typename _InIter = istreambuf_iterator<_CharT> >
    class money_get;
  template<typename _CharT, typename _OutIter = ostreambuf_iterator<_CharT> >
    class money_put;

  template<typename _CharT, bool _Intl = false>
    class moneypunct;
  template<typename _CharT, bool _Intl = false>
    class moneypunct_byname;


  class messages_base;
  template<typename _CharT>
    class messages;
  template<typename _CharT>
    class messages_byname;

  template<typename _Facet>
    bool
    has_facet(const locale& __loc) throw();

  template<typename _Facet>
    const _Facet&
    use_facet(const locale& __loc);

  template<typename _Facet>
    inline const _Facet&
    __check_facet(const _Facet* __f)
    {
      if (!__f)
 __throw_bad_cast();
      return *__f;
    }

}









namespace std __attribute__ ((__visibility__ ("default"))) {
  class locale
  {
  public:


    typedef int category;


    class facet;
    class id;
    class _Impl;

    friend class facet;
    friend class _Impl;

    template<typename _Facet>
      friend bool
      has_facet(const locale&) throw();

    template<typename _Facet>
      friend const _Facet&
      use_facet(const locale&);

    template<typename _Cache>
      friend struct __use_cache;
    static const category none = 0;
    static const category ctype = 1L << 0;
    static const category numeric = 1L << 1;
    static const category collate = 1L << 2;
    static const category time = 1L << 3;
    static const category monetary = 1L << 4;
    static const category messages = 1L << 5;
    static const category all = (ctype | numeric | collate |
        time | monetary | messages);
    locale() throw();
    locale(const locale& __other) throw();
    explicit
    locale(const char* __s);
    locale(const locale& __base, const char* __s, category __cat);
    locale(const locale& __base, const locale& __add, category __cat);
    template<typename _Facet>
      locale(const locale& __other, _Facet* __f);


    ~locale() throw();
    const locale&
    operator=(const locale& __other) throw();
    template<typename _Facet>
      locale
      combine(const locale& __other) const;






    string
    name() const;
    bool
    operator==(const locale& __other) const throw ();







    inline bool
    operator!=(const locale& __other) const throw ()
    { return !(this->operator==(__other)); }
    template<typename _Char, typename _Traits, typename _Alloc>
      bool
      operator()(const basic_string<_Char, _Traits, _Alloc>& __s1,
   const basic_string<_Char, _Traits, _Alloc>& __s2) const;
    static locale
    global(const locale&);




    static const locale&
    classic();

  private:

    _Impl* _M_impl;


    static _Impl* _S_classic;


    static _Impl* _S_global;





    static const char* const* const _S_categories;
    enum { _S_categories_size = 6 + 0 };


    static __gthread_once_t _S_once;


    explicit
    locale(_Impl*) throw();

    static void
    _S_initialize();

    static void
    _S_initialize_once();

    static category
    _S_normalize_category(category);

    void
    _M_coalesce(const locale& __base, const locale& __add, category __cat);
  };
  class locale::facet
  {
  private:
    friend class locale;
    friend class locale::_Impl;

    mutable _Atomic_word _M_refcount;


    static __c_locale _S_c_locale;


    static const char _S_c_name[2];


    static __gthread_once_t _S_once;


    static void
    _S_initialize_once();

  protected:
    explicit
    facet(size_t __refs = 0) throw() : _M_refcount(__refs ? 1 : 0)
    { }


    virtual
    ~facet();

    static void
    _S_create_c_locale(__c_locale& __cloc, const char* __s,
         __c_locale __old = 0);

    static __c_locale
    _S_clone_c_locale(__c_locale& __cloc);

    static void
    _S_destroy_c_locale(__c_locale& __cloc);



    static __c_locale
    _S_get_c_locale();

    static const char*
    _S_get_c_name();

  private:
    inline void
    _M_add_reference() const throw()
    { __gnu_cxx::__atomic_add_dispatch(&_M_refcount, 1); }

    inline void
    _M_remove_reference() const throw()
    {
      if (__gnu_cxx::__exchange_and_add_dispatch(&_M_refcount, -1) == 1)
 {
   if (true)
     { delete this; }
   if (false)
     { }
 }
    }

    facet(const facet&);

    facet&
    operator=(const facet&);
  };
  class locale::id
  {
  private:
    friend class locale;
    friend class locale::_Impl;

    template<typename _Facet>
      friend const _Facet&
      use_facet(const locale&);

    template<typename _Facet>
      friend bool
      has_facet(const locale&) throw ();




    mutable size_t _M_index;


    static _Atomic_word _S_refcount;

    void
    operator=(const id&);

    id(const id&);

  public:



    id() { }

    size_t
    _M_id() const;
  };



  class locale::_Impl
  {
  public:

    friend class locale;
    friend class locale::facet;

    template<typename _Facet>
      friend bool
      has_facet(const locale&) throw();

    template<typename _Facet>
      friend const _Facet&
      use_facet(const locale&);

    template<typename _Cache>
      friend struct __use_cache;

  private:

    _Atomic_word _M_refcount;
    const facet** _M_facets;
    size_t _M_facets_size;
    const facet** _M_caches;
    char** _M_names;
    static const locale::id* const _S_id_ctype[];
    static const locale::id* const _S_id_numeric[];
    static const locale::id* const _S_id_collate[];
    static const locale::id* const _S_id_time[];
    static const locale::id* const _S_id_monetary[];
    static const locale::id* const _S_id_messages[];
    static const locale::id* const* const _S_facet_categories[];

    inline void
    _M_add_reference() throw()
    { __gnu_cxx::__atomic_add_dispatch(&_M_refcount, 1); }

    inline void
    _M_remove_reference() throw()
    {
      if (__gnu_cxx::__exchange_and_add_dispatch(&_M_refcount, -1) == 1)
 {
   if (true)
     { delete this; }
   if (false)
     { }
 }
    }

    _Impl(const _Impl&, size_t);
    _Impl(const char*, size_t);
    _Impl(size_t) throw();

   ~_Impl() throw();

    _Impl(const _Impl&);

    void
    operator=(const _Impl&);

    inline bool
    _M_check_same_name()
    {
      bool __ret = true;
      if (_M_names[1])

 for (size_t __i = 0; __ret && __i < _S_categories_size - 1; ++__i)
   __ret = std::strcmp(_M_names[__i], _M_names[__i + 1]) == 0;
      return __ret;
    }

    void
    _M_replace_categories(const _Impl*, category);

    void
    _M_replace_category(const _Impl*, const locale::id* const*);

    void
    _M_replace_facet(const _Impl*, const locale::id*);

    void
    _M_install_facet(const locale::id*, const facet*);

    template<typename _Facet>
      inline void
      _M_init_facet(_Facet* __facet)
      { _M_install_facet(&_Facet::id, __facet); }

    void
    _M_install_cache(const facet*, size_t);
  };

  template<typename _Facet>
    locale::locale(const locale& __other, _Facet* __f)
    {
      _M_impl = new _Impl(*__other._M_impl, 1);

      if (true)
 { _M_impl->_M_install_facet(&_Facet::id, __f); }
      if (false)
 {
   _M_impl->_M_remove_reference();
                          ;
 }
      delete [] _M_impl->_M_names[0];
      _M_impl->_M_names[0] = 0;
    }

}

namespace std __attribute__ ((__visibility__ ("default"))) {





  enum _Ios_Fmtflags
    {
      _S_boolalpha = 1L << 0,
      _S_dec = 1L << 1,
      _S_fixed = 1L << 2,
      _S_hex = 1L << 3,
      _S_internal = 1L << 4,
      _S_left = 1L << 5,
      _S_oct = 1L << 6,
      _S_right = 1L << 7,
      _S_scientific = 1L << 8,
      _S_showbase = 1L << 9,
      _S_showpoint = 1L << 10,
      _S_showpos = 1L << 11,
      _S_skipws = 1L << 12,
      _S_unitbuf = 1L << 13,
      _S_uppercase = 1L << 14,
      _S_adjustfield = _S_left | _S_right | _S_internal,
      _S_basefield = _S_dec | _S_oct | _S_hex,
      _S_floatfield = _S_scientific | _S_fixed,
      _S_ios_fmtflags_end = 1L << 16
    };

  inline _Ios_Fmtflags
  operator&(_Ios_Fmtflags __a, _Ios_Fmtflags __b)
  { return _Ios_Fmtflags(static_cast<int>(__a) & static_cast<int>(__b)); }

  inline _Ios_Fmtflags
  operator|(_Ios_Fmtflags __a, _Ios_Fmtflags __b)
  { return _Ios_Fmtflags(static_cast<int>(__a) | static_cast<int>(__b)); }

  inline _Ios_Fmtflags
  operator^(_Ios_Fmtflags __a, _Ios_Fmtflags __b)
  { return _Ios_Fmtflags(static_cast<int>(__a) ^ static_cast<int>(__b)); }

  inline _Ios_Fmtflags&
  operator|=(_Ios_Fmtflags& __a, _Ios_Fmtflags __b)
  { return __a = __a | __b; }

  inline _Ios_Fmtflags&
  operator&=(_Ios_Fmtflags& __a, _Ios_Fmtflags __b)
  { return __a = __a & __b; }

  inline _Ios_Fmtflags&
  operator^=(_Ios_Fmtflags& __a, _Ios_Fmtflags __b)
  { return __a = __a ^ __b; }

  inline _Ios_Fmtflags
  operator~(_Ios_Fmtflags __a)
  { return _Ios_Fmtflags(~static_cast<int>(__a)); }


  enum _Ios_Openmode
    {
      _S_app = 1L << 0,
      _S_ate = 1L << 1,
      _S_bin = 1L << 2,
      _S_in = 1L << 3,
      _S_out = 1L << 4,
      _S_trunc = 1L << 5,
      _S_ios_openmode_end = 1L << 16
    };

  inline _Ios_Openmode
  operator&(_Ios_Openmode __a, _Ios_Openmode __b)
  { return _Ios_Openmode(static_cast<int>(__a) & static_cast<int>(__b)); }

  inline _Ios_Openmode
  operator|(_Ios_Openmode __a, _Ios_Openmode __b)
  { return _Ios_Openmode(static_cast<int>(__a) | static_cast<int>(__b)); }

  inline _Ios_Openmode
  operator^(_Ios_Openmode __a, _Ios_Openmode __b)
  { return _Ios_Openmode(static_cast<int>(__a) ^ static_cast<int>(__b)); }

  inline _Ios_Openmode&
  operator|=(_Ios_Openmode& __a, _Ios_Openmode __b)
  { return __a = __a | __b; }

  inline _Ios_Openmode&
  operator&=(_Ios_Openmode& __a, _Ios_Openmode __b)
  { return __a = __a & __b; }

  inline _Ios_Openmode&
  operator^=(_Ios_Openmode& __a, _Ios_Openmode __b)
  { return __a = __a ^ __b; }

  inline _Ios_Openmode
  operator~(_Ios_Openmode __a)
  { return _Ios_Openmode(~static_cast<int>(__a)); }


  enum _Ios_Iostate
    {
      _S_goodbit = 0,
      _S_badbit = 1L << 0,
      _S_eofbit = 1L << 1,
      _S_failbit = 1L << 2,
      _S_ios_iostate_end = 1L << 16
    };

  inline _Ios_Iostate
  operator&(_Ios_Iostate __a, _Ios_Iostate __b)
  { return _Ios_Iostate(static_cast<int>(__a) & static_cast<int>(__b)); }

  inline _Ios_Iostate
  operator|(_Ios_Iostate __a, _Ios_Iostate __b)
  { return _Ios_Iostate(static_cast<int>(__a) | static_cast<int>(__b)); }

  inline _Ios_Iostate
  operator^(_Ios_Iostate __a, _Ios_Iostate __b)
  { return _Ios_Iostate(static_cast<int>(__a) ^ static_cast<int>(__b)); }

  inline _Ios_Iostate&
  operator|=(_Ios_Iostate& __a, _Ios_Iostate __b)
  { return __a = __a | __b; }

  inline _Ios_Iostate&
  operator&=(_Ios_Iostate& __a, _Ios_Iostate __b)
  { return __a = __a & __b; }

  inline _Ios_Iostate&
  operator^=(_Ios_Iostate& __a, _Ios_Iostate __b)
  { return __a = __a ^ __b; }

  inline _Ios_Iostate
  operator~(_Ios_Iostate __a)
  { return _Ios_Iostate(~static_cast<int>(__a)); }

  enum _Ios_Seekdir
    {
      _S_beg = 0,
      _S_cur = 1,
      _S_end = 2,
      _S_ios_seekdir_end = 1L << 16
    };
  class ios_base
  {
  public:



    class failure : public exception
    {
    public:


      explicit
      failure(const string& __str) throw();



      virtual
      ~failure() throw();

      virtual const char*
      what() const throw();

    private:
      string _M_msg;
    };
    typedef _Ios_Fmtflags fmtflags;


    static const fmtflags boolalpha = _S_boolalpha;


    static const fmtflags dec = _S_dec;


    static const fmtflags fixed = _S_fixed;


    static const fmtflags hex = _S_hex;




    static const fmtflags internal = _S_internal;



    static const fmtflags left = _S_left;


    static const fmtflags oct = _S_oct;



    static const fmtflags right = _S_right;


    static const fmtflags scientific = _S_scientific;



    static const fmtflags showbase = _S_showbase;



    static const fmtflags showpoint = _S_showpoint;


    static const fmtflags showpos = _S_showpos;


    static const fmtflags skipws = _S_skipws;


    static const fmtflags unitbuf = _S_unitbuf;



    static const fmtflags uppercase = _S_uppercase;


    static const fmtflags adjustfield = _S_adjustfield;


    static const fmtflags basefield = _S_basefield;


    static const fmtflags floatfield = _S_floatfield;
    typedef _Ios_Iostate iostate;



    static const iostate badbit = _S_badbit;


    static const iostate eofbit = _S_eofbit;




    static const iostate failbit = _S_failbit;


    static const iostate goodbit = _S_goodbit;
    typedef _Ios_Openmode openmode;


    static const openmode app = _S_app;


    static const openmode ate = _S_ate;





    static const openmode binary = _S_bin;


    static const openmode in = _S_in;


    static const openmode out = _S_out;


    static const openmode trunc = _S_trunc;
    typedef _Ios_Seekdir seekdir;


    static const seekdir beg = _S_beg;


    static const seekdir cur = _S_cur;


    static const seekdir end = _S_end;


    typedef int io_state;
    typedef int open_mode;
    typedef int seek_dir;

    typedef std::streampos streampos;
    typedef std::streamoff streamoff;
    enum event
    {
      erase_event,
      imbue_event,
      copyfmt_event
    };
    typedef void (*event_callback) (event, ios_base&, int);
    void
    register_callback(event_callback __fn, int __index);

  protected:






    streamsize _M_precision;
    streamsize _M_width;
    fmtflags _M_flags;
    iostate _M_exception;
    iostate _M_streambuf_state;




    struct _Callback_list
    {

      _Callback_list* _M_next;
      ios_base::event_callback _M_fn;
      int _M_index;
      _Atomic_word _M_refcount;

      _Callback_list(ios_base::event_callback __fn, int __index,
       _Callback_list* __cb)
      : _M_next(__cb), _M_fn(__fn), _M_index(__index), _M_refcount(0) { }

      void
      _M_add_reference() { __gnu_cxx::__atomic_add_dispatch(&_M_refcount, 1); }


      int
      _M_remove_reference()
      { return __gnu_cxx::__exchange_and_add_dispatch(&_M_refcount, -1); }
    };

     _Callback_list* _M_callbacks;

    void
    _M_call_callbacks(event __ev) throw();

    void
    _M_dispose_callbacks(void);


    struct _Words
    {
      void* _M_pword;
      long _M_iword;
      _Words() : _M_pword(0), _M_iword(0) { }
    };


    _Words _M_word_zero;



    enum { _S_local_word_size = 8 };
    _Words _M_local_word[_S_local_word_size];


    int _M_word_size;
    _Words* _M_word;

    _Words&
    _M_grow_words(int __index, bool __iword);


    locale _M_ios_locale;

    void
    _M_init();

  public:





    class Init
    {
      friend class ios_base;
    public:
      Init();
      ~Init();

    private:
      static _Atomic_word _S_refcount;
      static bool _S_synced_with_stdio;
    };






    inline fmtflags
    flags() const { return _M_flags; }
    inline fmtflags
    flags(fmtflags __fmtfl)
    {
      fmtflags __old = _M_flags;
      _M_flags = __fmtfl;
      return __old;
    }
    inline fmtflags
    setf(fmtflags __fmtfl)
    {
      fmtflags __old = _M_flags;
      _M_flags |= __fmtfl;
      return __old;
    }
    inline fmtflags
    setf(fmtflags __fmtfl, fmtflags __mask)
    {
      fmtflags __old = _M_flags;
      _M_flags &= ~__mask;
      _M_flags |= (__fmtfl & __mask);
      return __old;
    }







    inline void
    unsetf(fmtflags __mask) { _M_flags &= ~__mask; }
    inline streamsize
    precision() const { return _M_precision; }






    inline streamsize
    precision(streamsize __prec)
    {
      streamsize __old = _M_precision;
      _M_precision = __prec;
      return __old;
    }







    inline streamsize
    width() const { return _M_width; }






    inline streamsize
    width(streamsize __wide)
    {
      streamsize __old = _M_width;
      _M_width = __wide;
      return __old;
    }
    static bool
    sync_with_stdio(bool __sync = true);
    locale
    imbue(const locale& __loc);
    inline locale
    getloc() const { return _M_ios_locale; }
    inline const locale&
    _M_getloc() const { return _M_ios_locale; }
    static int
    xalloc() throw();
    inline long&
    iword(int __ix)
    {
      _Words& __word = (__ix < _M_word_size)
   ? _M_word[__ix] : _M_grow_words(__ix, true);
      return __word._M_iword;
    }
    inline void*&
    pword(int __ix)
    {
      _Words& __word = (__ix < _M_word_size)
   ? _M_word[__ix] : _M_grow_words(__ix, false);
      return __word._M_pword;
    }
    virtual ~ios_base();

  protected:
    ios_base();



  private:
    ios_base(const ios_base&);

    ios_base&
    operator=(const ios_base&);
  };



  inline ios_base&
  boolalpha(ios_base& __base)
  {
    __base.setf(ios_base::boolalpha);
    return __base;
  }


  inline ios_base&
  noboolalpha(ios_base& __base)
  {
    __base.unsetf(ios_base::boolalpha);
    return __base;
  }


  inline ios_base&
  showbase(ios_base& __base)
  {
    __base.setf(ios_base::showbase);
    return __base;
  }


  inline ios_base&
  noshowbase(ios_base& __base)
  {
    __base.unsetf(ios_base::showbase);
    return __base;
  }


  inline ios_base&
  showpoint(ios_base& __base)
  {
    __base.setf(ios_base::showpoint);
    return __base;
  }


  inline ios_base&
  noshowpoint(ios_base& __base)
  {
    __base.unsetf(ios_base::showpoint);
    return __base;
  }


  inline ios_base&
  showpos(ios_base& __base)
  {
    __base.setf(ios_base::showpos);
    return __base;
  }


  inline ios_base&
  noshowpos(ios_base& __base)
  {
    __base.unsetf(ios_base::showpos);
    return __base;
  }


  inline ios_base&
  skipws(ios_base& __base)
  {
    __base.setf(ios_base::skipws);
    return __base;
  }


  inline ios_base&
  noskipws(ios_base& __base)
  {
    __base.unsetf(ios_base::skipws);
    return __base;
  }


  inline ios_base&
  uppercase(ios_base& __base)
  {
    __base.setf(ios_base::uppercase);
    return __base;
  }


  inline ios_base&
  nouppercase(ios_base& __base)
  {
    __base.unsetf(ios_base::uppercase);
    return __base;
  }


  inline ios_base&
  unitbuf(ios_base& __base)
  {
     __base.setf(ios_base::unitbuf);
     return __base;
  }


  inline ios_base&
  nounitbuf(ios_base& __base)
  {
     __base.unsetf(ios_base::unitbuf);
     return __base;
  }



  inline ios_base&
  internal(ios_base& __base)
  {
     __base.setf(ios_base::internal, ios_base::adjustfield);
     return __base;
  }


  inline ios_base&
  left(ios_base& __base)
  {
    __base.setf(ios_base::left, ios_base::adjustfield);
    return __base;
  }


  inline ios_base&
  right(ios_base& __base)
  {
    __base.setf(ios_base::right, ios_base::adjustfield);
    return __base;
  }



  inline ios_base&
  dec(ios_base& __base)
  {
    __base.setf(ios_base::dec, ios_base::basefield);
    return __base;
  }


  inline ios_base&
  hex(ios_base& __base)
  {
    __base.setf(ios_base::hex, ios_base::basefield);
    return __base;
  }


  inline ios_base&
  oct(ios_base& __base)
  {
    __base.setf(ios_base::oct, ios_base::basefield);
    return __base;
  }



  inline ios_base&
  fixed(ios_base& __base)
  {
    __base.setf(ios_base::fixed, ios_base::floatfield);
    return __base;
  }


  inline ios_base&
  scientific(ios_base& __base)
  {
    __base.setf(ios_base::scientific, ios_base::floatfield);
    return __base;
  }

}








namespace std __attribute__ ((__visibility__ ("default"))) {






  template<typename _CharT, typename _Traits>
    streamsize
    __copy_streambufs_eof(basic_streambuf<_CharT, _Traits>*,
     basic_streambuf<_CharT, _Traits>*, bool&);
  template<typename _CharT, typename _Traits>
    class basic_streambuf
    {
    public:






      typedef _CharT char_type;
      typedef _Traits traits_type;
      typedef typename traits_type::int_type int_type;
      typedef typename traits_type::pos_type pos_type;
      typedef typename traits_type::off_type off_type;
      typedef basic_streambuf<char_type, traits_type> __streambuf_type;


      friend class basic_ios<char_type, traits_type>;
      friend class basic_istream<char_type, traits_type>;
      friend class basic_ostream<char_type, traits_type>;
      friend class istreambuf_iterator<char_type, traits_type>;
      friend class ostreambuf_iterator<char_type, traits_type>;

      friend streamsize
      __copy_streambufs_eof<>(__streambuf_type*, __streambuf_type*, bool&);

      template<typename _CharT2>
        friend typename __gnu_cxx::__enable_if<__is_char<_CharT2>::__value,
            _CharT2*>::__type
        __copy_aux(istreambuf_iterator<_CharT2>,
     istreambuf_iterator<_CharT2>, _CharT2*);

      template<typename _CharT2>
        friend typename __gnu_cxx::__enable_if<__is_char<_CharT2>::__value,
      istreambuf_iterator<_CharT2> >::__type
        find(istreambuf_iterator<_CharT2>, istreambuf_iterator<_CharT2>,
      const _CharT2&);

      template<typename _CharT2, typename _Traits2>
        friend basic_istream<_CharT2, _Traits2>&
        operator>>(basic_istream<_CharT2, _Traits2>&, _CharT2*);

      template<typename _CharT2, typename _Traits2, typename _Alloc>
        friend basic_istream<_CharT2, _Traits2>&
        operator>>(basic_istream<_CharT2, _Traits2>&,
     basic_string<_CharT2, _Traits2, _Alloc>&);

      template<typename _CharT2, typename _Traits2, typename _Alloc>
        friend basic_istream<_CharT2, _Traits2>&
        getline(basic_istream<_CharT2, _Traits2>&,
  basic_string<_CharT2, _Traits2, _Alloc>&, _CharT2);

    protected:
      char_type* _M_in_beg;
      char_type* _M_in_cur;
      char_type* _M_in_end;
      char_type* _M_out_beg;
      char_type* _M_out_cur;
      char_type* _M_out_end;






      locale _M_buf_locale;

  public:

      virtual
      ~basic_streambuf()
      { }
      locale
      pubimbue(const locale &__loc)
      {
 locale __tmp(this->getloc());
 this->imbue(__loc);
 _M_buf_locale = __loc;
 return __tmp;
      }
      locale
      getloc() const
      { return _M_buf_locale; }
      __streambuf_type*
      pubsetbuf(char_type* __s, streamsize __n)
      { return this->setbuf(__s, __n); }

      pos_type
      pubseekoff(off_type __off, ios_base::seekdir __way,
   ios_base::openmode __mode = ios_base::in | ios_base::out)
      { return this->seekoff(__off, __way, __mode); }

      pos_type
      pubseekpos(pos_type __sp,
   ios_base::openmode __mode = ios_base::in | ios_base::out)
      { return this->seekpos(__sp, __mode); }

      int
      pubsync() { return this->sync(); }
      streamsize
      in_avail()
      {
 const streamsize __ret = this->egptr() - this->gptr();
 return __ret ? __ret : this->showmanyc();
      }
      int_type
      snextc()
      {
 int_type __ret = traits_type::eof();
 if (__builtin_expect(!traits_type::eq_int_type(this->sbumpc(),
             __ret), true))
   __ret = this->sgetc();
 return __ret;
      }
      int_type
      sbumpc()
      {
 int_type __ret;
 if (__builtin_expect(this->gptr() < this->egptr(), true))
   {
     __ret = traits_type::to_int_type(*this->gptr());
     this->gbump(1);
   }
 else
   __ret = this->uflow();
 return __ret;
      }
      int_type
      sgetc()
      {
 int_type __ret;
 if (__builtin_expect(this->gptr() < this->egptr(), true))
   __ret = traits_type::to_int_type(*this->gptr());
 else
   __ret = this->underflow();
 return __ret;
      }
      streamsize
      sgetn(char_type* __s, streamsize __n)
      { return this->xsgetn(__s, __n); }
      int_type
      sputbackc(char_type __c)
      {
 int_type __ret;
 const bool __testpos = this->eback() < this->gptr();
 if (__builtin_expect(!__testpos ||
        !traits_type::eq(__c, this->gptr()[-1]), false))
   __ret = this->pbackfail(traits_type::to_int_type(__c));
 else
   {
     this->gbump(-1);
     __ret = traits_type::to_int_type(*this->gptr());
   }
 return __ret;
      }
      int_type
      sungetc()
      {
 int_type __ret;
 if (__builtin_expect(this->eback() < this->gptr(), true))
   {
     this->gbump(-1);
     __ret = traits_type::to_int_type(*this->gptr());
   }
 else
   __ret = this->pbackfail();
 return __ret;
      }
      int_type
      sputc(char_type __c)
      {
 int_type __ret;
 if (__builtin_expect(this->pptr() < this->epptr(), true))
   {
     *this->pptr() = __c;
     this->pbump(1);
     __ret = traits_type::to_int_type(__c);
   }
 else
   __ret = this->overflow(traits_type::to_int_type(__c));
 return __ret;
      }
      streamsize
      sputn(const char_type* __s, streamsize __n)
      { return this->xsputn(__s, __n); }

    protected:
      basic_streambuf()
      : _M_in_beg(0), _M_in_cur(0), _M_in_end(0),
      _M_out_beg(0), _M_out_cur(0), _M_out_end(0),
      _M_buf_locale(locale())
      { }
      char_type*
      eback() const { return _M_in_beg; }

      char_type*
      gptr() const { return _M_in_cur; }

      char_type*
      egptr() const { return _M_in_end; }
      void
      gbump(int __n) { _M_in_cur += __n; }
      void
      setg(char_type* __gbeg, char_type* __gnext, char_type* __gend)
      {
 _M_in_beg = __gbeg;
 _M_in_cur = __gnext;
 _M_in_end = __gend;
      }
      char_type*
      pbase() const { return _M_out_beg; }

      char_type*
      pptr() const { return _M_out_cur; }

      char_type*
      epptr() const { return _M_out_end; }
      void
      pbump(int __n) { _M_out_cur += __n; }
      void
      setp(char_type* __pbeg, char_type* __pend)
      {
 _M_out_beg = _M_out_cur = __pbeg;
 _M_out_end = __pend;
      }
      virtual void
      imbue(const locale&)
      { }
      virtual basic_streambuf<char_type,_Traits>*
      setbuf(char_type*, streamsize)
      { return this; }
      virtual pos_type
      seekoff(off_type, ios_base::seekdir,
       ios_base::openmode = ios_base::in | ios_base::out)
      { return pos_type(off_type(-1)); }
      virtual pos_type
      seekpos(pos_type,
       ios_base::openmode = ios_base::in | ios_base::out)
      { return pos_type(off_type(-1)); }
      virtual int
      sync() { return 0; }
      virtual streamsize
      showmanyc() { return 0; }
      virtual streamsize
      xsgetn(char_type* __s, streamsize __n);
      virtual int_type
      underflow()
      { return traits_type::eof(); }
      virtual int_type
      uflow()
      {
 int_type __ret = traits_type::eof();
 const bool __testeof = traits_type::eq_int_type(this->underflow(),
       __ret);
 if (!__testeof)
   {
     __ret = traits_type::to_int_type(*this->gptr());
     this->gbump(1);
   }
 return __ret;
      }
      virtual int_type
      pbackfail(int_type = traits_type::eof())
      { return traits_type::eof(); }
      virtual streamsize
      xsputn(const char_type* __s, streamsize __n);
      virtual int_type
      overflow(int_type = traits_type::eof())
      { return traits_type::eof(); }
    private:


      basic_streambuf(const __streambuf_type& __sb)
      : _M_in_beg(__sb._M_in_beg), _M_in_cur(__sb._M_in_cur),
      _M_in_end(__sb._M_in_end), _M_out_beg(__sb._M_out_beg),
      _M_out_cur(__sb._M_out_cur), _M_out_end(__sb._M_out_cur),
      _M_buf_locale(__sb._M_buf_locale)
      { }

      __streambuf_type&
      operator=(const __streambuf_type&) { return *this; };
    };


  template<>
    streamsize
    __copy_streambufs_eof(basic_streambuf<char>* __sbin,
     basic_streambuf<char>* __sbout, bool& __ineof);

  template<>
    streamsize
    __copy_streambufs_eof(basic_streambuf<wchar_t>* __sbin,
     basic_streambuf<wchar_t>* __sbout, bool& __ineof);


}




namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _CharT, typename _Traits>
    streamsize
    basic_streambuf<_CharT, _Traits>::
    xsgetn(char_type* __s, streamsize __n)
    {
      streamsize __ret = 0;
      while (__ret < __n)
 {
   const streamsize __buf_len = this->egptr() - this->gptr();
   if (__buf_len)
     {
       const streamsize __remaining = __n - __ret;
       const streamsize __len = std::min(__buf_len, __remaining);
       traits_type::copy(__s, this->gptr(), __len);
       __ret += __len;
       __s += __len;
       this->gbump(__len);
     }

   if (__ret < __n)
     {
       const int_type __c = this->uflow();
       if (!traits_type::eq_int_type(__c, traits_type::eof()))
  {
    traits_type::assign(*__s++, traits_type::to_char_type(__c));
    ++__ret;
  }
       else
  break;
     }
 }
      return __ret;
    }

  template<typename _CharT, typename _Traits>
    streamsize
    basic_streambuf<_CharT, _Traits>::
    xsputn(const char_type* __s, streamsize __n)
    {
      streamsize __ret = 0;
      while (__ret < __n)
 {
   const streamsize __buf_len = this->epptr() - this->pptr();
   if (__buf_len)
     {
       const streamsize __remaining = __n - __ret;
       const streamsize __len = std::min(__buf_len, __remaining);
       traits_type::copy(this->pptr(), __s, __len);
       __ret += __len;
       __s += __len;
       this->pbump(__len);
     }

   if (__ret < __n)
     {
       int_type __c = this->overflow(traits_type::to_int_type(*__s));
       if (!traits_type::eq_int_type(__c, traits_type::eof()))
  {
    ++__ret;
    ++__s;
  }
       else
  break;
     }
 }
      return __ret;
    }




  template<typename _CharT, typename _Traits>
    streamsize
    __copy_streambufs_eof(basic_streambuf<_CharT, _Traits>* __sbin,
     basic_streambuf<_CharT, _Traits>* __sbout,
     bool& __ineof)
    {
      streamsize __ret = 0;
      __ineof = true;
      typename _Traits::int_type __c = __sbin->sgetc();
      while (!_Traits::eq_int_type(__c, _Traits::eof()))
 {
   __c = __sbout->sputc(_Traits::to_char_type(__c));
   if (_Traits::eq_int_type(__c, _Traits::eof()))
     {
       __ineof = false;
       break;
     }
   ++__ret;
   __c = __sbin->snextc();
 }
      return __ret;
    }

  template<typename _CharT, typename _Traits>
    inline streamsize
    __copy_streambufs(basic_streambuf<_CharT, _Traits>* __sbin,
        basic_streambuf<_CharT, _Traits>* __sbout)
    {
      bool __ineof;
      return __copy_streambufs_eof(__sbin, __sbout, __ineof);
    }





  extern template class basic_streambuf<char>;
  extern template
    streamsize
    __copy_streambufs(basic_streambuf<char>*,
        basic_streambuf<char>*);
  extern template
    streamsize
    __copy_streambufs_eof(basic_streambuf<char>*,
     basic_streambuf<char>*, bool&);


  extern template class basic_streambuf<wchar_t>;
  extern template
    streamsize
    __copy_streambufs(basic_streambuf<wchar_t>*,
        basic_streambuf<wchar_t>*);
  extern template
    streamsize
    __copy_streambufs_eof(basic_streambuf<wchar_t>*,
     basic_streambuf<wchar_t>*, bool&);



}





namespace std __attribute__ ((__visibility__ ("default"))) {



  template<typename _CharT, typename _Traits>
    class istreambuf_iterator
    : public iterator<input_iterator_tag, _CharT, typename _Traits::off_type,
        _CharT*, _CharT&>
    {
    public:



      typedef _CharT char_type;
      typedef _Traits traits_type;
      typedef typename _Traits::int_type int_type;
      typedef basic_streambuf<_CharT, _Traits> streambuf_type;
      typedef basic_istream<_CharT, _Traits> istream_type;


      template<typename _CharT2>
 friend typename __gnu_cxx::__enable_if<__is_char<_CharT2>::__value,
                      ostreambuf_iterator<_CharT2> >::__type
 copy(istreambuf_iterator<_CharT2>, istreambuf_iterator<_CharT2>,
      ostreambuf_iterator<_CharT2>);

      template<typename _CharT2>
 friend typename __gnu_cxx::__enable_if<__is_char<_CharT2>::__value,
            _CharT2*>::__type
 __copy_aux(istreambuf_iterator<_CharT2>, istreambuf_iterator<_CharT2>,
     _CharT2*);

      template<typename _CharT2>
 friend typename __gnu_cxx::__enable_if<__is_char<_CharT2>::__value,
               istreambuf_iterator<_CharT2> >::__type
 find(istreambuf_iterator<_CharT2>, istreambuf_iterator<_CharT2>,
      const _CharT2&);

    private:







      mutable streambuf_type* _M_sbuf;
      mutable int_type _M_c;

    public:

      istreambuf_iterator() throw()
      : _M_sbuf(0), _M_c(traits_type::eof()) { }


      istreambuf_iterator(istream_type& __s) throw()
      : _M_sbuf(__s.rdbuf()), _M_c(traits_type::eof()) { }


      istreambuf_iterator(streambuf_type* __s) throw()
      : _M_sbuf(__s), _M_c(traits_type::eof()) { }




      char_type
      operator*() const
      {







 return traits_type::to_char_type(_M_get());
      }


      istreambuf_iterator&
      operator++()
      {


                        ;
 if (_M_sbuf)
   {
     _M_sbuf->sbumpc();
     _M_c = traits_type::eof();
   }
 return *this;
      }


      istreambuf_iterator
      operator++(int)
      {


                        ;

 istreambuf_iterator __old = *this;
 if (_M_sbuf)
   {
     __old._M_c = _M_sbuf->sbumpc();
     _M_c = traits_type::eof();
   }
 return __old;
      }





      bool
      equal(const istreambuf_iterator& __b) const
      {
 const bool __thiseof = _M_at_eof();
 const bool __beof = __b._M_at_eof();
 return (__thiseof && __beof || (!__thiseof && !__beof));
      }

    private:
      int_type
      _M_get() const
      {
 const int_type __eof = traits_type::eof();
 int_type __ret = __eof;
 if (_M_sbuf)
   {
     if (!traits_type::eq_int_type(_M_c, __eof))
       __ret = _M_c;
     else if (!traits_type::eq_int_type((__ret = _M_sbuf->sgetc()),
            __eof))
       _M_c = __ret;
     else
       _M_sbuf = 0;
   }
 return __ret;
      }

      bool
      _M_at_eof() const
      {
 const int_type __eof = traits_type::eof();
 return traits_type::eq_int_type(_M_get(), __eof);
      }
    };

  template<typename _CharT, typename _Traits>
    inline bool
    operator==(const istreambuf_iterator<_CharT, _Traits>& __a,
        const istreambuf_iterator<_CharT, _Traits>& __b)
    { return __a.equal(__b); }

  template<typename _CharT, typename _Traits>
    inline bool
    operator!=(const istreambuf_iterator<_CharT, _Traits>& __a,
        const istreambuf_iterator<_CharT, _Traits>& __b)
    { return !__a.equal(__b); }


  template<typename _CharT, typename _Traits>
    class ostreambuf_iterator
    : public iterator<output_iterator_tag, void, void, void, void>
    {
    public:



      typedef _CharT char_type;
      typedef _Traits traits_type;
      typedef basic_streambuf<_CharT, _Traits> streambuf_type;
      typedef basic_ostream<_CharT, _Traits> ostream_type;


      template<typename _CharT2>
 friend typename __gnu_cxx::__enable_if<__is_char<_CharT2>::__value,
                      ostreambuf_iterator<_CharT2> >::__type
 copy(istreambuf_iterator<_CharT2>, istreambuf_iterator<_CharT2>,
      ostreambuf_iterator<_CharT2>);

    private:
      streambuf_type* _M_sbuf;
      bool _M_failed;

    public:

      ostreambuf_iterator(ostream_type& __s) throw ()
      : _M_sbuf(__s.rdbuf()), _M_failed(!_M_sbuf) { }


      ostreambuf_iterator(streambuf_type* __s) throw ()
      : _M_sbuf(__s), _M_failed(!_M_sbuf) { }


      ostreambuf_iterator&
      operator=(_CharT __c)
      {
 if (!_M_failed &&
     _Traits::eq_int_type(_M_sbuf->sputc(__c), _Traits::eof()))
   _M_failed = true;
 return *this;
      }


      ostreambuf_iterator&
      operator*()
      { return *this; }


      ostreambuf_iterator&
      operator++(int)
      { return *this; }


      ostreambuf_iterator&
      operator++()
      { return *this; }


      bool
      failed() const throw()
      { return _M_failed; }

      ostreambuf_iterator&
      _M_put(const _CharT* __ws, streamsize __len)
      {
 if (__builtin_expect(!_M_failed, true)
     && __builtin_expect(this->_M_sbuf->sputn(__ws, __len) != __len,
    false))
   _M_failed = true;
 return *this;
      }
    };


  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
                           ostreambuf_iterator<_CharT> >::__type
    copy(istreambuf_iterator<_CharT> __first,
  istreambuf_iterator<_CharT> __last,
  ostreambuf_iterator<_CharT> __result)
    {
      if (__first._M_sbuf && !__last._M_sbuf && !__result._M_failed)
 {
   bool __ineof;
   __copy_streambufs_eof(__first._M_sbuf, __result._M_sbuf, __ineof);
   if (!__ineof)
     __result._M_failed = true;
 }
      return __result;
    }

  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
            ostreambuf_iterator<_CharT> >::__type
    __copy_aux(_CharT* __first, _CharT* __last,
        ostreambuf_iterator<_CharT> __result)
    {
      const streamsize __num = __last - __first;
      if (__num > 0)
 __result._M_put(__first, __num);
      return __result;
    }

  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
        ostreambuf_iterator<_CharT> >::__type
    __copy_aux(const _CharT* __first, const _CharT* __last,
        ostreambuf_iterator<_CharT> __result)
    {
      const streamsize __num = __last - __first;
      if (__num > 0)
 __result._M_put(__first, __num);
      return __result;
    }

  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
            _CharT*>::__type
    __copy_aux(istreambuf_iterator<_CharT> __first,
        istreambuf_iterator<_CharT> __last, _CharT* __result)
    {
      typedef istreambuf_iterator<_CharT> __is_iterator_type;
      typedef typename __is_iterator_type::traits_type traits_type;
      typedef typename __is_iterator_type::streambuf_type streambuf_type;
      typedef typename traits_type::int_type int_type;

      if (__first._M_sbuf && !__last._M_sbuf)
 {
   streambuf_type* __sb = __first._M_sbuf;
   int_type __c = __sb->sgetc();
   while (!traits_type::eq_int_type(__c, traits_type::eof()))
     {
       const streamsize __n = __sb->egptr() - __sb->gptr();
       if (__n > 1)
  {
    traits_type::copy(__result, __sb->gptr(), __n);
    __sb->gbump(__n);
    __result += __n;
    __c = __sb->underflow();
  }
       else
  {
    *__result++ = traits_type::to_char_type(__c);
    __c = __sb->snextc();
  }
     }
 }
      return __result;
    }

  template<typename _CharT>
    typename __gnu_cxx::__enable_if<__is_char<_CharT>::__value,
          istreambuf_iterator<_CharT> >::__type
    find(istreambuf_iterator<_CharT> __first,
  istreambuf_iterator<_CharT> __last, const _CharT& __val)
    {
      typedef istreambuf_iterator<_CharT> __is_iterator_type;
      typedef typename __is_iterator_type::traits_type traits_type;
      typedef typename __is_iterator_type::streambuf_type streambuf_type;
      typedef typename traits_type::int_type int_type;

      if (__first._M_sbuf && !__last._M_sbuf)
 {
   const int_type __ival = traits_type::to_int_type(__val);
   streambuf_type* __sb = __first._M_sbuf;
   int_type __c = __sb->sgetc();
   while (!traits_type::eq_int_type(__c, traits_type::eof())
   && !traits_type::eq_int_type(__c, __ival))
     {
       streamsize __n = __sb->egptr() - __sb->gptr();
       if (__n > 1)
  {
    const _CharT* __p = traits_type::find(__sb->gptr(),
       __n, __val);
    if (__p)
      __n = __p - __sb->gptr();
    __sb->gbump(__n);
    __c = __sb->sgetc();
  }
       else
  __c = __sb->snextc();
     }

   if (!traits_type::eq_int_type(__c, traits_type::eof()))
     __first._M_c = __c;
   else
     __first._M_sbuf = 0;
 }
      return __first;
    }

}








typedef int wctrans_t;




typedef unsigned long wctype_t;
extern "C" {
int iswalnum(wint_t);
int iswalpha(wint_t);
int iswblank(wint_t);
int iswcntrl(wint_t);
int iswctype(wint_t, wctype_t);
int iswdigit(wint_t);
int iswgraph(wint_t);
int iswlower(wint_t);
int iswprint(wint_t);
int iswpunct(wint_t);
int iswspace(wint_t);
int iswupper(wint_t);
int iswxdigit(wint_t);
wint_t towctrans(wint_t, wctrans_t);
wint_t towlower(wint_t);
wint_t towupper(wint_t);
wctrans_t
 wctrans(const char *);
wctype_t
 wctype(const char *);


wint_t iswascii(wint_t);
wint_t iswhexnumber(wint_t);
wint_t iswideogram(wint_t);
wint_t iswnumber(wint_t);
wint_t iswphonogram(wint_t);
wint_t iswrune(wint_t);
wint_t iswspecial(wint_t);
wint_t nextwctype(wint_t, wctype_t);

}
namespace std __attribute__ ((__visibility__ ("default"))) {

  using ::wint_t;

  using ::wctype_t;
  using ::wctrans_t;

  using ::iswalnum;
  using ::iswalpha;

  using ::iswblank;

  using ::iswcntrl;
  using ::iswctype;
  using ::iswdigit;
  using ::iswgraph;
  using ::iswlower;
  using ::iswprint;
  using ::iswpunct;
  using ::iswspace;
  using ::iswupper;
  using ::iswxdigit;
  using ::towctrans;
  using ::towlower;
  using ::towupper;
  using ::wctrans;
  using ::wctype;

}
namespace std __attribute__ ((__visibility__ ("default"))) {


  struct ctype_base
  {

    typedef const int* __to_type;



    typedef unsigned long mask;


    static const mask upper = 0x00008000L;
    static const mask lower = 0x00001000L;
    static const mask alpha = 0x00000100L;
    static const mask digit = 0x00000400L;
    static const mask xdigit = 0x00010000L;
    static const mask space = 0x00004000L;
    static const mask print = 0x00040000L;
    static const mask graph = 0x00000100L | 0x00000400L | 0x00002000L;
    static const mask cntrl = 0x00000200L;
    static const mask punct = 0x00002000L;
    static const mask alnum = 0x00000100L | 0x00000400L;
  };

}





namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _Tv>
    void
    __convert_to_v(const char* __in, _Tv& __out, ios_base::iostate& __err,
     const __c_locale& __cloc);


  template<>
    void
    __convert_to_v(const char*, float&, ios_base::iostate&,
     const __c_locale&);

  template<>
    void
    __convert_to_v(const char*, double&, ios_base::iostate&,
     const __c_locale&);

  template<>
    void
    __convert_to_v(const char*, long double&, ios_base::iostate&,
     const __c_locale&);



  template<typename _CharT, typename _Traits>
    struct __pad
    {
      static void
      _S_pad(ios_base& __io, _CharT __fill, _CharT* __news,
      const _CharT* __olds, const streamsize __newlen,
      const streamsize __oldlen, const bool __num);
    };






  template<typename _CharT>
    _CharT*
    __add_grouping(_CharT* __s, _CharT __sep,
     const char* __gbeg, size_t __gsize,
     const _CharT* __first, const _CharT* __last);




  template<typename _CharT>
    inline
    ostreambuf_iterator<_CharT>
    __write(ostreambuf_iterator<_CharT> __s, const _CharT* __ws, int __len)
    {
      __s._M_put(__ws, __len);
      return __s;
    }


  template<typename _CharT, typename _OutIter>
    inline
    _OutIter
    __write(_OutIter __s, const _CharT* __ws, int __len)
    {
      for (int __j = 0; __j < __len; __j++, ++__s)
 *__s = __ws[__j];
      return __s;
    }
  template<typename _CharT>
    class __ctype_abstract_base : public locale::facet, public ctype_base
    {
    public:


      typedef _CharT char_type;
      bool
      is(mask __m, char_type __c) const
      { return this->do_is(__m, __c); }
      const char_type*
      is(const char_type *__lo, const char_type *__hi, mask *__vec) const
      { return this->do_is(__lo, __hi, __vec); }
      const char_type*
      scan_is(mask __m, const char_type* __lo, const char_type* __hi) const
      { return this->do_scan_is(__m, __lo, __hi); }
      const char_type*
      scan_not(mask __m, const char_type* __lo, const char_type* __hi) const
      { return this->do_scan_not(__m, __lo, __hi); }
      char_type
      toupper(char_type __c) const
      { return this->do_toupper(__c); }
      const char_type*
      toupper(char_type *__lo, const char_type* __hi) const
      { return this->do_toupper(__lo, __hi); }
      char_type
      tolower(char_type __c) const
      { return this->do_tolower(__c); }
      const char_type*
      tolower(char_type* __lo, const char_type* __hi) const
      { return this->do_tolower(__lo, __hi); }
      char_type
      widen(char __c) const
      { return this->do_widen(__c); }
      const char*
      widen(const char* __lo, const char* __hi, char_type* __to) const
      { return this->do_widen(__lo, __hi, __to); }
      char
      narrow(char_type __c, char __dfault) const
      { return this->do_narrow(__c, __dfault); }
      const char_type*
      narrow(const char_type* __lo, const char_type* __hi,
       char __dfault, char *__to) const
      { return this->do_narrow(__lo, __hi, __dfault, __to); }

    protected:
      explicit
      __ctype_abstract_base(size_t __refs = 0): facet(__refs) { }

      virtual
      ~__ctype_abstract_base() { }
      virtual bool
      do_is(mask __m, char_type __c) const = 0;
      virtual const char_type*
      do_is(const char_type* __lo, const char_type* __hi,
     mask* __vec) const = 0;
      virtual const char_type*
      do_scan_is(mask __m, const char_type* __lo,
   const char_type* __hi) const = 0;
      virtual const char_type*
      do_scan_not(mask __m, const char_type* __lo,
    const char_type* __hi) const = 0;
      virtual char_type
      do_toupper(char_type) const = 0;
      virtual const char_type*
      do_toupper(char_type* __lo, const char_type* __hi) const = 0;
      virtual char_type
      do_tolower(char_type) const = 0;
      virtual const char_type*
      do_tolower(char_type* __lo, const char_type* __hi) const = 0;
      virtual char_type
      do_widen(char) const = 0;
      virtual const char*
      do_widen(const char* __lo, const char* __hi,
        char_type* __dest) const = 0;
      virtual char
      do_narrow(char_type, char __dfault) const = 0;
      virtual const char_type*
      do_narrow(const char_type* __lo, const char_type* __hi,
  char __dfault, char* __dest) const = 0;
    };
  template<typename _CharT>
    class ctype : public __ctype_abstract_base<_CharT>
    {
    public:

      typedef _CharT char_type;
      typedef typename __ctype_abstract_base<_CharT>::mask mask;


      static locale::id id;

      explicit
      ctype(size_t __refs = 0) : __ctype_abstract_base<_CharT>(__refs) { }

   protected:
      virtual
      ~ctype();

      virtual bool
      do_is(mask __m, char_type __c) const;

      virtual const char_type*
      do_is(const char_type* __lo, const char_type* __hi, mask* __vec) const;

      virtual const char_type*
      do_scan_is(mask __m, const char_type* __lo, const char_type* __hi) const;

      virtual const char_type*
      do_scan_not(mask __m, const char_type* __lo,
    const char_type* __hi) const;

      virtual char_type
      do_toupper(char_type __c) const;

      virtual const char_type*
      do_toupper(char_type* __lo, const char_type* __hi) const;

      virtual char_type
      do_tolower(char_type __c) const;

      virtual const char_type*
      do_tolower(char_type* __lo, const char_type* __hi) const;

      virtual char_type
      do_widen(char __c) const;

      virtual const char*
      do_widen(const char* __lo, const char* __hi, char_type* __dest) const;

      virtual char
      do_narrow(char_type, char __dfault) const;

      virtual const char_type*
      do_narrow(const char_type* __lo, const char_type* __hi,
  char __dfault, char* __dest) const;
    };

  template<typename _CharT>
    locale::id ctype<_CharT>::id;
  template<>
    class ctype<char> : public locale::facet, public ctype_base
    {
    public:


      typedef char char_type;

    protected:

      __c_locale _M_c_locale_ctype;
      bool _M_del;
      __to_type _M_toupper;
      __to_type _M_tolower;
      const mask* _M_table;
      mutable char _M_widen_ok;
      mutable char _M_widen[1 + static_cast<unsigned char>(-1)];
      mutable char _M_narrow[1 + static_cast<unsigned char>(-1)];
      mutable char _M_narrow_ok;


    public:

      static locale::id id;

      static const size_t table_size = 1 + static_cast<unsigned char>(-1);
      explicit
      ctype(const mask* __table = 0, bool __del = false, size_t __refs = 0);
      explicit
      ctype(__c_locale __cloc, const mask* __table = 0, bool __del = false,
     size_t __refs = 0);
      inline bool
      is(mask __m, char __c) const;
      inline const char*
      is(const char* __lo, const char* __hi, mask* __vec) const;
      inline const char*
      scan_is(mask __m, const char* __lo, const char* __hi) const;
      inline const char*
      scan_not(mask __m, const char* __lo, const char* __hi) const;
      char_type
      toupper(char_type __c) const
      { return this->do_toupper(__c); }
      const char_type*
      toupper(char_type *__lo, const char_type* __hi) const
      { return this->do_toupper(__lo, __hi); }
      char_type
      tolower(char_type __c) const
      { return this->do_tolower(__c); }
      const char_type*
      tolower(char_type* __lo, const char_type* __hi) const
      { return this->do_tolower(__lo, __hi); }
      char_type
      widen(char __c) const
      {
 if (_M_widen_ok)
   return _M_widen[static_cast<unsigned char>(__c)];
 this->_M_widen_init();
 return this->do_widen(__c);
      }
      const char*
      widen(const char* __lo, const char* __hi, char_type* __to) const
      {
 if (_M_widen_ok == 1)
   {
     memcpy(__to, __lo, __hi - __lo);
     return __hi;
   }
 if (!_M_widen_ok)
   _M_widen_init();
 return this->do_widen(__lo, __hi, __to);
      }
      char
      narrow(char_type __c, char __dfault) const
      {
 if (_M_narrow[static_cast<unsigned char>(__c)])
   return _M_narrow[static_cast<unsigned char>(__c)];
 const char __t = do_narrow(__c, __dfault);
 if (__t != __dfault)
   _M_narrow[static_cast<unsigned char>(__c)] = __t;
 return __t;
      }
      const char_type*
      narrow(const char_type* __lo, const char_type* __hi,
      char __dfault, char *__to) const
      {
 if (__builtin_expect(_M_narrow_ok == 1, true))
   {
     memcpy(__to, __lo, __hi - __lo);
     return __hi;
   }
 if (!_M_narrow_ok)
   _M_narrow_init();
 return this->do_narrow(__lo, __hi, __dfault, __to);
      }

    protected:


      const mask*
      table() const throw()
      { return _M_table; }


      static const mask*
      classic_table() throw();







      virtual
      ~ctype();
      virtual char_type
      do_toupper(char_type) const;
      virtual const char_type*
      do_toupper(char_type* __lo, const char_type* __hi) const;
      virtual char_type
      do_tolower(char_type) const;
      virtual const char_type*
      do_tolower(char_type* __lo, const char_type* __hi) const;
      virtual char_type
      do_widen(char __c) const
      { return __c; }
      virtual const char*
      do_widen(const char* __lo, const char* __hi, char_type* __dest) const
      {
 memcpy(__dest, __lo, __hi - __lo);
 return __hi;
      }
      virtual char
      do_narrow(char_type __c, char) const
      { return __c; }
      virtual const char_type*
      do_narrow(const char_type* __lo, const char_type* __hi,
  char, char* __dest) const
      {
 memcpy(__dest, __lo, __hi - __lo);
 return __hi;
      }

    private:

      void _M_widen_init() const
      {
 char __tmp[sizeof(_M_widen)];
 for (size_t __i = 0; __i < sizeof(_M_widen); ++__i)
   __tmp[__i] = __i;
 do_widen(__tmp, __tmp + sizeof(__tmp), _M_widen);

 _M_widen_ok = 1;

 if (memcmp(__tmp, _M_widen, sizeof(_M_widen)))
   _M_widen_ok = 2;
      }




      void _M_narrow_init() const
      {
 char __tmp[sizeof(_M_narrow)];
 for (size_t __i = 0; __i < sizeof(_M_narrow); ++__i)
   __tmp[__i] = __i;
 do_narrow(__tmp, __tmp + sizeof(__tmp), 0, _M_narrow);

 _M_narrow_ok = 1;
 if (memcmp(__tmp, _M_narrow, sizeof(_M_narrow)))
   _M_narrow_ok = 2;
 else
   {


     char __c;
     do_narrow(__tmp, __tmp + 1, 1, &__c);
     if (__c == 1)
       _M_narrow_ok = 2;
   }
      }
    };

  template<>
    const ctype<char>&
    use_facet<ctype<char> >(const locale& __loc);
  template<>
    class ctype<wchar_t> : public __ctype_abstract_base<wchar_t>
    {
    public:


      typedef wchar_t char_type;
      typedef wctype_t __wmask_type;

    protected:
      __c_locale _M_c_locale_ctype;


      bool _M_narrow_ok;
      char _M_narrow[128];
      wint_t _M_widen[1 + static_cast<unsigned char>(-1)];


      mask _M_bit[16];
      __wmask_type _M_wmask[16];

    public:


      static locale::id id;
      explicit
      ctype(size_t __refs = 0);
      explicit
      ctype(__c_locale __cloc, size_t __refs = 0);

    protected:
      __wmask_type
      _M_convert_to_wmask(const mask __m) const;


      virtual
      ~ctype();
      virtual bool
      do_is(mask __m, char_type __c) const;
      virtual const char_type*
      do_is(const char_type* __lo, const char_type* __hi, mask* __vec) const;
      virtual const char_type*
      do_scan_is(mask __m, const char_type* __lo, const char_type* __hi) const;
      virtual const char_type*
      do_scan_not(mask __m, const char_type* __lo,
    const char_type* __hi) const;
      virtual char_type
      do_toupper(char_type) const;
      virtual const char_type*
      do_toupper(char_type* __lo, const char_type* __hi) const;
      virtual char_type
      do_tolower(char_type) const;
      virtual const char_type*
      do_tolower(char_type* __lo, const char_type* __hi) const;
      virtual char_type
      do_widen(char) const;
      virtual const char*
      do_widen(const char* __lo, const char* __hi, char_type* __dest) const;
      virtual char
      do_narrow(char_type, char __dfault) const;
      virtual const char_type*
      do_narrow(const char_type* __lo, const char_type* __hi,
  char __dfault, char* __dest) const;


      void
      _M_initialize_ctype();
    };

  template<>
    const ctype<wchar_t>&
    use_facet<ctype<wchar_t> >(const locale& __loc);



  template<typename _CharT>
    class ctype_byname : public ctype<_CharT>
    {
    public:
      typedef _CharT char_type;

      explicit
      ctype_byname(const char* __s, size_t __refs = 0);

    protected:
      virtual
      ~ctype_byname() { };
    };


  template<>
    ctype_byname<char>::ctype_byname(const char*, size_t refs);

  template<>
    ctype_byname<wchar_t>::ctype_byname(const char*, size_t refs);

}



namespace std __attribute__ ((__visibility__ ("default"))) {

  bool
  ctype<char>::
  is(mask __m, char __c) const
  {
    if (_M_table)
      return _M_table[static_cast<unsigned char>(__c)] & __m;
    else
      return __istype(__c, __m);
  }

  const char*
  ctype<char>::
  is(const char* __low, const char* __high, mask* __vec) const
  {
    if (_M_table)
      while (__low < __high)
 *__vec++ = _M_table[static_cast<unsigned char>(*__low++)];
    else
      for (;__low < __high; ++__vec, ++__low)
 {

   *__vec = __maskrune (*__low, upper | lower | alpha | digit | xdigit
          | space | print | graph | cntrl | punct | alnum);
 }
    return __high;
  }

  const char*
  ctype<char>::
  scan_is(mask __m, const char* __low, const char* __high) const
  {
    if (_M_table)
      while (__low < __high
      && !(_M_table[static_cast<unsigned char>(*__low)] & __m))
 ++__low;
    else
      while (__low < __high && !this->is(__m, *__low))
 ++__low;
    return __low;
  }

  const char*
  ctype<char>::
  scan_not(mask __m, const char* __low, const char* __high) const
  {
    if (_M_table)
      while (__low < __high
      && (_M_table[static_cast<unsigned char>(*__low)] & __m) != 0)
 ++__low;
    else
      while (__low < __high && this->is(__m, *__low) != 0)
 ++__low;
    return __low;
  }


  inline bool
  ctype<wchar_t>::
  do_is(mask __m, wchar_t __c) const
  {
    return __istype (__c, __m);
  }

  inline const wchar_t*
  ctype<wchar_t>::
  do_is(const wchar_t* __lo, const wchar_t* __hi, mask* __vec) const
  {
    for (; __lo < __hi; ++__vec, ++__lo)
      *__vec = __maskrune (*__lo, upper | lower | alpha | digit | xdigit
      | space | print | graph | cntrl | punct | alnum);
    return __hi;
  }

  inline const wchar_t*
  ctype<wchar_t>::
  do_scan_is(mask __m, const wchar_t* __lo, const wchar_t* __hi) const
  {
    while (__lo < __hi && ! __istype (*__lo, __m))
      ++__lo;
    return __lo;
  }

  inline const wchar_t*
  ctype<wchar_t>::
  do_scan_not(mask __m, const char_type* __lo, const char_type* __hi) const
  {
    while (__lo < __hi && __istype (*__lo, __m))
      ++__lo;
    return __lo;
  }


}



namespace std __attribute__ ((__visibility__ ("default"))) {


  class codecvt_base
  {
  public:
    enum result
    {
      ok,
      partial,
      error,
      noconv
    };
  };
  template<typename _InternT, typename _ExternT, typename _StateT>
    class __codecvt_abstract_base
    : public locale::facet, public codecvt_base
    {
    public:

      typedef codecvt_base::result result;
      typedef _InternT intern_type;
      typedef _ExternT extern_type;
      typedef _StateT state_type;
      result
      out(state_type& __state, const intern_type* __from,
   const intern_type* __from_end, const intern_type*& __from_next,
   extern_type* __to, extern_type* __to_end,
   extern_type*& __to_next) const
      {
 return this->do_out(__state, __from, __from_end, __from_next,
       __to, __to_end, __to_next);
      }
      result
      unshift(state_type& __state, extern_type* __to, extern_type* __to_end,
       extern_type*& __to_next) const
      { return this->do_unshift(__state, __to,__to_end,__to_next); }
      result
      in(state_type& __state, const extern_type* __from,
  const extern_type* __from_end, const extern_type*& __from_next,
  intern_type* __to, intern_type* __to_end,
  intern_type*& __to_next) const
      {
 return this->do_in(__state, __from, __from_end, __from_next,
      __to, __to_end, __to_next);
      }

      int
      encoding() const throw()
      { return this->do_encoding(); }

      bool
      always_noconv() const throw()
      { return this->do_always_noconv(); }

      int
      length(state_type& __state, const extern_type* __from,
      const extern_type* __end, size_t __max) const
      { return this->do_length(__state, __from, __end, __max); }

      int
      max_length() const throw()
      { return this->do_max_length(); }

    protected:
      explicit
      __codecvt_abstract_base(size_t __refs = 0) : locale::facet(__refs) { }

      virtual
      ~__codecvt_abstract_base() { }
      virtual result
      do_out(state_type& __state, const intern_type* __from,
      const intern_type* __from_end, const intern_type*& __from_next,
      extern_type* __to, extern_type* __to_end,
      extern_type*& __to_next) const = 0;

      virtual result
      do_unshift(state_type& __state, extern_type* __to,
   extern_type* __to_end, extern_type*& __to_next) const = 0;

      virtual result
      do_in(state_type& __state, const extern_type* __from,
     const extern_type* __from_end, const extern_type*& __from_next,
     intern_type* __to, intern_type* __to_end,
     intern_type*& __to_next) const = 0;

      virtual int
      do_encoding() const throw() = 0;

      virtual bool
      do_always_noconv() const throw() = 0;

      virtual int
      do_length(state_type&, const extern_type* __from,
  const extern_type* __end, size_t __max) const = 0;

      virtual int
      do_max_length() const throw() = 0;
    };



  template<typename _InternT, typename _ExternT, typename _StateT>
    class codecvt
    : public __codecvt_abstract_base<_InternT, _ExternT, _StateT>
    {
    public:

      typedef codecvt_base::result result;
      typedef _InternT intern_type;
      typedef _ExternT extern_type;
      typedef _StateT state_type;

    protected:
      __c_locale _M_c_locale_codecvt;

    public:
      static locale::id id;

      explicit
      codecvt(size_t __refs = 0)
      : __codecvt_abstract_base<_InternT, _ExternT, _StateT> (__refs) { }

      explicit
      codecvt(__c_locale __cloc, size_t __refs = 0);

    protected:
      virtual
      ~codecvt() { }

      virtual result
      do_out(state_type& __state, const intern_type* __from,
      const intern_type* __from_end, const intern_type*& __from_next,
      extern_type* __to, extern_type* __to_end,
      extern_type*& __to_next) const;

      virtual result
      do_unshift(state_type& __state, extern_type* __to,
   extern_type* __to_end, extern_type*& __to_next) const;

      virtual result
      do_in(state_type& __state, const extern_type* __from,
     const extern_type* __from_end, const extern_type*& __from_next,
     intern_type* __to, intern_type* __to_end,
     intern_type*& __to_next) const;

      virtual int
      do_encoding() const throw();

      virtual bool
      do_always_noconv() const throw();

      virtual int
      do_length(state_type&, const extern_type* __from,
  const extern_type* __end, size_t __max) const;

      virtual int
      do_max_length() const throw();
    };

  template<typename _InternT, typename _ExternT, typename _StateT>
    locale::id codecvt<_InternT, _ExternT, _StateT>::id;


  template<>
    class codecvt<char, char, mbstate_t>
    : public __codecvt_abstract_base<char, char, mbstate_t>
    {
    public:

      typedef char intern_type;
      typedef char extern_type;
      typedef mbstate_t state_type;

    protected:
      __c_locale _M_c_locale_codecvt;

    public:
      static locale::id id;

      explicit
      codecvt(size_t __refs = 0);

      explicit
      codecvt(__c_locale __cloc, size_t __refs = 0);

    protected:
      virtual
      ~codecvt();

      virtual result
      do_out(state_type& __state, const intern_type* __from,
      const intern_type* __from_end, const intern_type*& __from_next,
      extern_type* __to, extern_type* __to_end,
      extern_type*& __to_next) const;

      virtual result
      do_unshift(state_type& __state, extern_type* __to,
   extern_type* __to_end, extern_type*& __to_next) const;

      virtual result
      do_in(state_type& __state, const extern_type* __from,
     const extern_type* __from_end, const extern_type*& __from_next,
     intern_type* __to, intern_type* __to_end,
     intern_type*& __to_next) const;

      virtual int
      do_encoding() const throw();

      virtual bool
      do_always_noconv() const throw();

      virtual int
      do_length(state_type&, const extern_type* __from,
  const extern_type* __end, size_t __max) const;

      virtual int
      do_max_length() const throw();
  };



  template<>
    class codecvt<wchar_t, char, mbstate_t>
    : public __codecvt_abstract_base<wchar_t, char, mbstate_t>
    {
    public:

      typedef wchar_t intern_type;
      typedef char extern_type;
      typedef mbstate_t state_type;

    protected:
      __c_locale _M_c_locale_codecvt;

    public:
      static locale::id id;

      explicit
      codecvt(size_t __refs = 0);

      explicit
      codecvt(__c_locale __cloc, size_t __refs = 0);

    protected:
      virtual
      ~codecvt();

      virtual result
      do_out(state_type& __state, const intern_type* __from,
      const intern_type* __from_end, const intern_type*& __from_next,
      extern_type* __to, extern_type* __to_end,
      extern_type*& __to_next) const;

      virtual result
      do_unshift(state_type& __state,
   extern_type* __to, extern_type* __to_end,
   extern_type*& __to_next) const;

      virtual result
      do_in(state_type& __state,
      const extern_type* __from, const extern_type* __from_end,
      const extern_type*& __from_next,
      intern_type* __to, intern_type* __to_end,
      intern_type*& __to_next) const;

      virtual
      int do_encoding() const throw();

      virtual
      bool do_always_noconv() const throw();

      virtual
      int do_length(state_type&, const extern_type* __from,
      const extern_type* __end, size_t __max) const;

      virtual int
      do_max_length() const throw();
    };



  template<typename _InternT, typename _ExternT, typename _StateT>
    class codecvt_byname : public codecvt<_InternT, _ExternT, _StateT>
    {
    public:
      explicit
      codecvt_byname(const char* __s, size_t __refs = 0)
      : codecvt<_InternT, _ExternT, _StateT>(__refs)
      {
 if (std::strcmp(__s, "C") != 0 && std::strcmp(__s, "POSIX") != 0)
   {
     this->_S_destroy_c_locale(this->_M_c_locale_codecvt);
     this->_S_create_c_locale(this->_M_c_locale_codecvt, __s);
   }
      }

    protected:
      virtual
      ~codecvt_byname() { }
    };

}

namespace std __attribute__ ((__visibility__ ("default"))) {


  class __num_base
  {
  public:


    enum
      {
        _S_ominus,
        _S_oplus,
        _S_ox,
        _S_oX,
        _S_odigits,
        _S_odigits_end = _S_odigits + 16,
        _S_oudigits = _S_odigits_end,
        _S_oudigits_end = _S_oudigits + 16,
        _S_oe = _S_odigits + 14,
        _S_oE = _S_oudigits + 14,
 _S_oend = _S_oudigits_end
      };






    static const char* _S_atoms_out;



    static const char* _S_atoms_in;

    enum
    {
      _S_iminus,
      _S_iplus,
      _S_ix,
      _S_iX,
      _S_izero,
      _S_ie = _S_izero + 14,
      _S_iE = _S_izero + 20,
      _S_iend = 26
    };



    static void
    _S_format_float(const ios_base& __io, char* __fptr, char __mod);
  };

  template<typename _CharT>
    struct __numpunct_cache : public locale::facet
    {
      const char* _M_grouping;
      size_t _M_grouping_size;
      bool _M_use_grouping;
      const _CharT* _M_truename;
      size_t _M_truename_size;
      const _CharT* _M_falsename;
      size_t _M_falsename_size;
      _CharT _M_decimal_point;
      _CharT _M_thousands_sep;





      _CharT _M_atoms_out[__num_base::_S_oend];





      _CharT _M_atoms_in[__num_base::_S_iend];

      bool _M_allocated;

      __numpunct_cache(size_t __refs = 0) : facet(__refs),
      _M_grouping(__null), _M_grouping_size(0), _M_use_grouping(false),
      _M_truename(__null), _M_truename_size(0), _M_falsename(__null),
      _M_falsename_size(0), _M_decimal_point(_CharT()),
      _M_thousands_sep(_CharT()), _M_allocated(false)
      { }

      ~__numpunct_cache();

      void
      _M_cache(const locale& __loc);

    private:
      __numpunct_cache&
      operator=(const __numpunct_cache&);

      explicit
      __numpunct_cache(const __numpunct_cache&);
    };

  template<typename _CharT>
    __numpunct_cache<_CharT>::~__numpunct_cache()
    {
      if (_M_allocated)
 {
   delete [] _M_grouping;
   delete [] _M_truename;
   delete [] _M_falsename;
 }
    }
  template<typename _CharT>
    class numpunct : public locale::facet
    {
    public:



      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;

      typedef __numpunct_cache<_CharT> __cache_type;

    protected:
      __cache_type* _M_data;

    public:

      static locale::id id;






      explicit
      numpunct(size_t __refs = 0) : facet(__refs), _M_data(__null)
      { _M_initialize_numpunct(); }
      explicit
      numpunct(__cache_type* __cache, size_t __refs = 0)
      : facet(__refs), _M_data(__cache)
      { _M_initialize_numpunct(); }
      explicit
      numpunct(__c_locale __cloc, size_t __refs = 0)
      : facet(__refs), _M_data(__null)
      { _M_initialize_numpunct(__cloc); }
      char_type
      decimal_point() const
      { return this->do_decimal_point(); }
      char_type
      thousands_sep() const
      { return this->do_thousands_sep(); }
      string
      grouping() const
      { return this->do_grouping(); }
      string_type
      truename() const
      { return this->do_truename(); }
      string_type
      falsename() const
      { return this->do_falsename(); }

    protected:

      virtual
      ~numpunct();
      virtual char_type
      do_decimal_point() const
      { return _M_data->_M_decimal_point; }
      virtual char_type
      do_thousands_sep() const
      { return _M_data->_M_thousands_sep; }
      virtual string
      do_grouping() const
      { return _M_data->_M_grouping; }
      virtual string_type
      do_truename() const
      { return _M_data->_M_truename; }
      virtual string_type
      do_falsename() const
      { return _M_data->_M_falsename; }


      void
      _M_initialize_numpunct(__c_locale __cloc = __null);
    };

  template<typename _CharT>
    locale::id numpunct<_CharT>::id;

  template<>
    numpunct<char>::~numpunct();

  template<>
    void
    numpunct<char>::_M_initialize_numpunct(__c_locale __cloc);


  template<>
    numpunct<wchar_t>::~numpunct();

  template<>
    void
    numpunct<wchar_t>::_M_initialize_numpunct(__c_locale __cloc);



  template<typename _CharT>
    class numpunct_byname : public numpunct<_CharT>
    {
    public:
      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;

      explicit
      numpunct_byname(const char* __s, size_t __refs = 0)
      : numpunct<_CharT>(__refs)
      {
 if (std::strcmp(__s, "C") != 0 && std::strcmp(__s, "POSIX") != 0)
   {
     __c_locale __tmp;
     this->_S_create_c_locale(__tmp, __s);
     this->_M_initialize_numpunct(__tmp);
     this->_S_destroy_c_locale(__tmp);
   }
      }

    protected:
      virtual
      ~numpunct_byname() { }
    };
  template<typename _CharT, typename _InIter>
    class num_get : public locale::facet
    {
    public:



      typedef _CharT char_type;
      typedef _InIter iter_type;



      static locale::id id;
      explicit
      num_get(size_t __refs = 0) : facet(__refs) { }
      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, bool& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }
      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, long& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }

      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, unsigned short& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }

      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, unsigned int& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }

      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, unsigned long& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }


      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, long long& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }

      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, unsigned long long& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }
      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, float& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }

      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, double& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }

      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, long double& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }
      iter_type
      get(iter_type __in, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, void*& __v) const
      { return this->do_get(__in, __end, __io, __err, __v); }

    protected:

      virtual ~num_get() { }

      iter_type
      _M_extract_float(iter_type, iter_type, ios_base&, ios_base::iostate&,
         string& __xtrc) const;

      template<typename _ValueT>
        iter_type
        _M_extract_int(iter_type, iter_type, ios_base&, ios_base::iostate&,
         _ValueT& __v) const;

      template<typename _CharT2>
      typename __gnu_cxx::__enable_if<__is_char<_CharT2>::__value, int>::__type
        _M_find(const _CharT2*, size_t __len, _CharT2 __c) const
        {
   int __ret = -1;
   if (__len <= 10)
     {
       if (__c >= _CharT2('0') && __c < _CharT2(_CharT2('0') + __len))
  __ret = __c - _CharT2('0');
     }
   else
     {
       if (__c >= _CharT2('0') && __c <= _CharT2('9'))
  __ret = __c - _CharT2('0');
       else if (__c >= _CharT2('a') && __c <= _CharT2('f'))
  __ret = 10 + (__c - _CharT2('a'));
       else if (__c >= _CharT2('A') && __c <= _CharT2('F'))
  __ret = 10 + (__c - _CharT2('A'));
     }
   return __ret;
 }

      template<typename _CharT2>
      typename __gnu_cxx::__enable_if<!__is_char<_CharT2>::__value,
          int>::__type
        _M_find(const _CharT2* __zero, size_t __len, _CharT2 __c) const
        {
   int __ret = -1;
   const char_type* __q = char_traits<_CharT2>::find(__zero, __len, __c);
   if (__q)
     {
       __ret = __q - __zero;
       if (__ret > 15)
  __ret -= 6;
     }
   return __ret;
 }
      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate&, bool&) const;


      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate&, long&) const;

      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
       unsigned short&) const;

      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      unsigned int&) const;

      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      unsigned long&) const;


      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      long long&) const;

      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      unsigned long long&) const;


      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      float&) const;

      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      double&) const;







      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      long double&) const;


      virtual iter_type
      do_get(iter_type, iter_type, ios_base&, ios_base::iostate& __err,
      void*&) const;
    };

  template<typename _CharT, typename _InIter>
    locale::id num_get<_CharT, _InIter>::id;
  template<typename _CharT, typename _OutIter>
    class num_put : public locale::facet
    {
    public:



      typedef _CharT char_type;
      typedef _OutIter iter_type;



      static locale::id id;
      explicit
      num_put(size_t __refs = 0) : facet(__refs) { }
      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill, bool __v) const
      { return this->do_put(__s, __f, __fill, __v); }
      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill, long __v) const
      { return this->do_put(__s, __f, __fill, __v); }

      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill,
   unsigned long __v) const
      { return this->do_put(__s, __f, __fill, __v); }


      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill, long long __v) const
      { return this->do_put(__s, __f, __fill, __v); }

      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill,
   unsigned long long __v) const
      { return this->do_put(__s, __f, __fill, __v); }
      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill, double __v) const
      { return this->do_put(__s, __f, __fill, __v); }

      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill,
   long double __v) const
      { return this->do_put(__s, __f, __fill, __v); }
      iter_type
      put(iter_type __s, ios_base& __f, char_type __fill,
   const void* __v) const
      { return this->do_put(__s, __f, __fill, __v); }

    protected:
      template<typename _ValueT>
        iter_type
        _M_insert_float(iter_type, ios_base& __io, char_type __fill,
   char __mod, _ValueT __v) const;

      void
      _M_group_float(const char* __grouping, size_t __grouping_size,
       char_type __sep, const char_type* __p, char_type* __new,
       char_type* __cs, int& __len) const;

      template<typename _ValueT>
        iter_type
        _M_insert_int(iter_type, ios_base& __io, char_type __fill,
        _ValueT __v) const;

      void
      _M_group_int(const char* __grouping, size_t __grouping_size,
     char_type __sep, ios_base& __io, char_type* __new,
     char_type* __cs, int& __len) const;

      void
      _M_pad(char_type __fill, streamsize __w, ios_base& __io,
      char_type* __new, const char_type* __cs, int& __len) const;


      virtual
      ~num_put() { };
      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, bool __v) const;

      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, long __v) const;

      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, unsigned long) const;


      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, long long __v) const;

      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, unsigned long long) const;


      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, double __v) const;






      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, long double __v) const;


      virtual iter_type
      do_put(iter_type, ios_base&, char_type __fill, const void* __v) const;







    };

  template <typename _CharT, typename _OutIter>
    locale::id num_put<_CharT, _OutIter>::id;
  template<typename _CharT>
    class collate : public locale::facet
    {
    public:



      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;


    protected:


      __c_locale _M_c_locale_collate;

    public:

      static locale::id id;
      explicit
      collate(size_t __refs = 0)
      : facet(__refs), _M_c_locale_collate(_S_get_c_locale())
      { }
      explicit
      collate(__c_locale __cloc, size_t __refs = 0)
      : facet(__refs), _M_c_locale_collate(_S_clone_c_locale(__cloc))
      { }
      int
      compare(const _CharT* __lo1, const _CharT* __hi1,
       const _CharT* __lo2, const _CharT* __hi2) const
      { return this->do_compare(__lo1, __hi1, __lo2, __hi2); }
      string_type
      transform(const _CharT* __lo, const _CharT* __hi) const
      { return this->do_transform(__lo, __hi); }
      long
      hash(const _CharT* __lo, const _CharT* __hi) const
      { return this->do_hash(__lo, __hi); }


      int
      _M_compare(const _CharT*, const _CharT*) const;

      size_t
      _M_transform(_CharT*, const _CharT*, size_t) const;

  protected:

      virtual
      ~collate()
      { _S_destroy_c_locale(_M_c_locale_collate); }
      virtual int
      do_compare(const _CharT* __lo1, const _CharT* __hi1,
   const _CharT* __lo2, const _CharT* __hi2) const;
      virtual string_type
      do_transform(const _CharT* __lo, const _CharT* __hi) const;
      virtual long
      do_hash(const _CharT* __lo, const _CharT* __hi) const;
    };

  template<typename _CharT>
    locale::id collate<_CharT>::id;


  template<>
    int
    collate<char>::_M_compare(const char*, const char*) const;

  template<>
    size_t
    collate<char>::_M_transform(char*, const char*, size_t) const;


  template<>
    int
    collate<wchar_t>::_M_compare(const wchar_t*, const wchar_t*) const;

  template<>
    size_t
    collate<wchar_t>::_M_transform(wchar_t*, const wchar_t*, size_t) const;



  template<typename _CharT>
    class collate_byname : public collate<_CharT>
    {
    public:


      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;


      explicit
      collate_byname(const char* __s, size_t __refs = 0)
      : collate<_CharT>(__refs)
      {
 if (std::strcmp(__s, "C") != 0 && std::strcmp(__s, "POSIX") != 0)
   {
     this->_S_destroy_c_locale(this->_M_c_locale_collate);
     this->_S_create_c_locale(this->_M_c_locale_collate, __s);
   }
      }

    protected:
      virtual
      ~collate_byname() { }
    };
  class time_base
  {
  public:
    enum dateorder { no_order, dmy, mdy, ymd, ydm };
  };

  template<typename _CharT>
    struct __timepunct_cache : public locale::facet
    {

      static const _CharT* _S_timezones[14];

      const _CharT* _M_date_format;
      const _CharT* _M_date_era_format;
      const _CharT* _M_time_format;
      const _CharT* _M_time_era_format;
      const _CharT* _M_date_time_format;
      const _CharT* _M_date_time_era_format;
      const _CharT* _M_am;
      const _CharT* _M_pm;
      const _CharT* _M_am_pm_format;


      const _CharT* _M_day1;
      const _CharT* _M_day2;
      const _CharT* _M_day3;
      const _CharT* _M_day4;
      const _CharT* _M_day5;
      const _CharT* _M_day6;
      const _CharT* _M_day7;


      const _CharT* _M_aday1;
      const _CharT* _M_aday2;
      const _CharT* _M_aday3;
      const _CharT* _M_aday4;
      const _CharT* _M_aday5;
      const _CharT* _M_aday6;
      const _CharT* _M_aday7;


      const _CharT* _M_month01;
      const _CharT* _M_month02;
      const _CharT* _M_month03;
      const _CharT* _M_month04;
      const _CharT* _M_month05;
      const _CharT* _M_month06;
      const _CharT* _M_month07;
      const _CharT* _M_month08;
      const _CharT* _M_month09;
      const _CharT* _M_month10;
      const _CharT* _M_month11;
      const _CharT* _M_month12;


      const _CharT* _M_amonth01;
      const _CharT* _M_amonth02;
      const _CharT* _M_amonth03;
      const _CharT* _M_amonth04;
      const _CharT* _M_amonth05;
      const _CharT* _M_amonth06;
      const _CharT* _M_amonth07;
      const _CharT* _M_amonth08;
      const _CharT* _M_amonth09;
      const _CharT* _M_amonth10;
      const _CharT* _M_amonth11;
      const _CharT* _M_amonth12;

      bool _M_allocated;

      __timepunct_cache(size_t __refs = 0) : facet(__refs),
      _M_date_format(__null), _M_date_era_format(__null), _M_time_format(__null),
      _M_time_era_format(__null), _M_date_time_format(__null),
      _M_date_time_era_format(__null), _M_am(__null), _M_pm(__null),
      _M_am_pm_format(__null), _M_day1(__null), _M_day2(__null), _M_day3(__null),
      _M_day4(__null), _M_day5(__null), _M_day6(__null), _M_day7(__null),
      _M_aday1(__null), _M_aday2(__null), _M_aday3(__null), _M_aday4(__null),
      _M_aday5(__null), _M_aday6(__null), _M_aday7(__null), _M_month01(__null),
      _M_month02(__null), _M_month03(__null), _M_month04(__null), _M_month05(__null),
      _M_month06(__null), _M_month07(__null), _M_month08(__null), _M_month09(__null),
      _M_month10(__null), _M_month11(__null), _M_month12(__null), _M_amonth01(__null),
      _M_amonth02(__null), _M_amonth03(__null), _M_amonth04(__null),
      _M_amonth05(__null), _M_amonth06(__null), _M_amonth07(__null),
      _M_amonth08(__null), _M_amonth09(__null), _M_amonth10(__null),
      _M_amonth11(__null), _M_amonth12(__null), _M_allocated(false)
      { }

      ~__timepunct_cache();

      void
      _M_cache(const locale& __loc);

    private:
      __timepunct_cache&
      operator=(const __timepunct_cache&);

      explicit
      __timepunct_cache(const __timepunct_cache&);
    };

  template<typename _CharT>
    __timepunct_cache<_CharT>::~__timepunct_cache()
    {
      if (_M_allocated)
 {

 }
    }


  template<>
    const char*
    __timepunct_cache<char>::_S_timezones[14];


  template<>
    const wchar_t*
    __timepunct_cache<wchar_t>::_S_timezones[14];



  template<typename _CharT>
    const _CharT* __timepunct_cache<_CharT>::_S_timezones[14];

  template<typename _CharT>
    class __timepunct : public locale::facet
    {
    public:

      typedef _CharT __char_type;
      typedef basic_string<_CharT> __string_type;
      typedef __timepunct_cache<_CharT> __cache_type;

    protected:
      __cache_type* _M_data;
      __c_locale _M_c_locale_timepunct;
      const char* _M_name_timepunct;

    public:

      static locale::id id;

      explicit
      __timepunct(size_t __refs = 0);

      explicit
      __timepunct(__cache_type* __cache, size_t __refs = 0);
      explicit
      __timepunct(__c_locale __cloc, const char* __s, size_t __refs = 0);



      void
      _M_put(_CharT* __s, size_t __maxlen, const _CharT* __format,
      const tm* __tm) const;

      void
      _M_date_formats(const _CharT** __date) const
      {

 __date[0] = _M_data->_M_date_format;
 __date[1] = _M_data->_M_date_era_format;
      }

      void
      _M_time_formats(const _CharT** __time) const
      {

 __time[0] = _M_data->_M_time_format;
 __time[1] = _M_data->_M_time_era_format;
      }

      void
      _M_date_time_formats(const _CharT** __dt) const
      {

 __dt[0] = _M_data->_M_date_time_format;
 __dt[1] = _M_data->_M_date_time_era_format;
      }

      void
      _M_am_pm_format(const _CharT* __ampm) const
      { __ampm = _M_data->_M_am_pm_format; }

      void
      _M_am_pm(const _CharT** __ampm) const
      {
 __ampm[0] = _M_data->_M_am;
 __ampm[1] = _M_data->_M_pm;
      }

      void
      _M_days(const _CharT** __days) const
      {
 __days[0] = _M_data->_M_day1;
 __days[1] = _M_data->_M_day2;
 __days[2] = _M_data->_M_day3;
 __days[3] = _M_data->_M_day4;
 __days[4] = _M_data->_M_day5;
 __days[5] = _M_data->_M_day6;
 __days[6] = _M_data->_M_day7;
      }

      void
      _M_days_abbreviated(const _CharT** __days) const
      {
 __days[0] = _M_data->_M_aday1;
 __days[1] = _M_data->_M_aday2;
 __days[2] = _M_data->_M_aday3;
 __days[3] = _M_data->_M_aday4;
 __days[4] = _M_data->_M_aday5;
 __days[5] = _M_data->_M_aday6;
 __days[6] = _M_data->_M_aday7;
      }

      void
      _M_months(const _CharT** __months) const
      {
 __months[0] = _M_data->_M_month01;
 __months[1] = _M_data->_M_month02;
 __months[2] = _M_data->_M_month03;
 __months[3] = _M_data->_M_month04;
 __months[4] = _M_data->_M_month05;
 __months[5] = _M_data->_M_month06;
 __months[6] = _M_data->_M_month07;
 __months[7] = _M_data->_M_month08;
 __months[8] = _M_data->_M_month09;
 __months[9] = _M_data->_M_month10;
 __months[10] = _M_data->_M_month11;
 __months[11] = _M_data->_M_month12;
      }

      void
      _M_months_abbreviated(const _CharT** __months) const
      {
 __months[0] = _M_data->_M_amonth01;
 __months[1] = _M_data->_M_amonth02;
 __months[2] = _M_data->_M_amonth03;
 __months[3] = _M_data->_M_amonth04;
 __months[4] = _M_data->_M_amonth05;
 __months[5] = _M_data->_M_amonth06;
 __months[6] = _M_data->_M_amonth07;
 __months[7] = _M_data->_M_amonth08;
 __months[8] = _M_data->_M_amonth09;
 __months[9] = _M_data->_M_amonth10;
 __months[10] = _M_data->_M_amonth11;
 __months[11] = _M_data->_M_amonth12;
      }

    protected:
      virtual
      ~__timepunct();


      void
      _M_initialize_timepunct(__c_locale __cloc = __null);
    };

  template<typename _CharT>
    locale::id __timepunct<_CharT>::id;


  template<>
    void
    __timepunct<char>::_M_initialize_timepunct(__c_locale __cloc);

  template<>
    void
    __timepunct<char>::_M_put(char*, size_t, const char*, const tm*) const;


  template<>
    void
    __timepunct<wchar_t>::_M_initialize_timepunct(__c_locale __cloc);

  template<>
    void
    __timepunct<wchar_t>::_M_put(wchar_t*, size_t, const wchar_t*,
     const tm*) const;


}



namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _CharT>
    __timepunct<_CharT>::__timepunct(size_t __refs)
    : facet(__refs), _M_data(__null)
    {
      _M_name_timepunct = _S_get_c_name();
      _M_initialize_timepunct();
    }

  template<typename _CharT>
    __timepunct<_CharT>::__timepunct(__cache_type* __cache, size_t __refs)
    : facet(__refs), _M_data(__cache)
    {
      _M_name_timepunct = _S_get_c_name();
      _M_initialize_timepunct();
    }

  template<typename _CharT>
    __timepunct<_CharT>::__timepunct(__c_locale __cloc, const char* __s,
         size_t __refs)
    : facet(__refs), _M_data(__null)
    {
      const size_t __len = std::strlen(__s) + 1;
      char* __tmp = new char[__len];
      std::memcpy(__tmp, __s, __len);
      _M_name_timepunct = __tmp;

      if (true)
 { _M_initialize_timepunct(__cloc); }
      if (false)
 {
   delete [] _M_name_timepunct;
                          ;
 }
    }

  template<typename _CharT>
    __timepunct<_CharT>::~__timepunct()
    {
      if (_M_name_timepunct != _S_get_c_name())
 delete [] _M_name_timepunct;
      delete _M_data;
      _S_destroy_c_locale(_M_c_locale_timepunct);
    }

}

namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _CharT, typename _InIter>
    class time_get : public locale::facet, public time_base
    {
    public:



      typedef _CharT char_type;
      typedef _InIter iter_type;

      typedef basic_string<_CharT> __string_type;


      static locale::id id;
      explicit
      time_get(size_t __refs = 0)
      : facet (__refs) { }
      dateorder
      date_order() const
      { return this->do_date_order(); }
      iter_type
      get_time(iter_type __beg, iter_type __end, ios_base& __io,
        ios_base::iostate& __err, tm* __tm) const
      { return this->do_get_time(__beg, __end, __io, __err, __tm); }
      iter_type
      get_date(iter_type __beg, iter_type __end, ios_base& __io,
        ios_base::iostate& __err, tm* __tm) const
      { return this->do_get_date(__beg, __end, __io, __err, __tm); }
      iter_type
      get_weekday(iter_type __beg, iter_type __end, ios_base& __io,
    ios_base::iostate& __err, tm* __tm) const
      { return this->do_get_weekday(__beg, __end, __io, __err, __tm); }
      iter_type
      get_monthname(iter_type __beg, iter_type __end, ios_base& __io,
      ios_base::iostate& __err, tm* __tm) const
      { return this->do_get_monthname(__beg, __end, __io, __err, __tm); }
      iter_type
      get_year(iter_type __beg, iter_type __end, ios_base& __io,
        ios_base::iostate& __err, tm* __tm) const
      { return this->do_get_year(__beg, __end, __io, __err, __tm); }

    protected:

      virtual
      ~time_get() { }
      virtual dateorder
      do_date_order() const;
      virtual iter_type
      do_get_time(iter_type __beg, iter_type __end, ios_base& __io,
    ios_base::iostate& __err, tm* __tm) const;
      virtual iter_type
      do_get_date(iter_type __beg, iter_type __end, ios_base& __io,
    ios_base::iostate& __err, tm* __tm) const;
      virtual iter_type
      do_get_weekday(iter_type __beg, iter_type __end, ios_base&,
       ios_base::iostate& __err, tm* __tm) const;
      virtual iter_type
      do_get_monthname(iter_type __beg, iter_type __end, ios_base&,
         ios_base::iostate& __err, tm* __tm) const;
      virtual iter_type
      do_get_year(iter_type __beg, iter_type __end, ios_base& __io,
    ios_base::iostate& __err, tm* __tm) const;


      iter_type
      _M_extract_num(iter_type __beg, iter_type __end, int& __member,
       int __min, int __max, size_t __len,
       ios_base& __io, ios_base::iostate& __err) const;



      iter_type
      _M_extract_name(iter_type __beg, iter_type __end, int& __member,
        const _CharT** __names, size_t __indexlen,
        ios_base& __io, ios_base::iostate& __err) const;


      iter_type
      _M_extract_via_format(iter_type __beg, iter_type __end, ios_base& __io,
       ios_base::iostate& __err, tm* __tm,
       const _CharT* __format) const;
    };

  template<typename _CharT, typename _InIter>
    locale::id time_get<_CharT, _InIter>::id;


  template<typename _CharT, typename _InIter>
    class time_get_byname : public time_get<_CharT, _InIter>
    {
    public:

      typedef _CharT char_type;
      typedef _InIter iter_type;

      explicit
      time_get_byname(const char*, size_t __refs = 0)
      : time_get<_CharT, _InIter>(__refs) { }

    protected:
      virtual
      ~time_get_byname() { }
    };
  template<typename _CharT, typename _OutIter>
    class time_put : public locale::facet
    {
    public:



      typedef _CharT char_type;
      typedef _OutIter iter_type;



      static locale::id id;
      explicit
      time_put(size_t __refs = 0)
      : facet(__refs) { }
      iter_type
      put(iter_type __s, ios_base& __io, char_type __fill, const tm* __tm,
   const _CharT* __beg, const _CharT* __end) const;
      iter_type
      put(iter_type __s, ios_base& __io, char_type __fill,
   const tm* __tm, char __format, char __mod = 0) const
      { return this->do_put(__s, __io, __fill, __tm, __format, __mod); }

    protected:

      virtual
      ~time_put()
      { }
      virtual iter_type
      do_put(iter_type __s, ios_base& __io, char_type __fill, const tm* __tm,
      char __format, char __mod) const;
    };

  template<typename _CharT, typename _OutIter>
    locale::id time_put<_CharT, _OutIter>::id;


  template<typename _CharT, typename _OutIter>
    class time_put_byname : public time_put<_CharT, _OutIter>
    {
    public:

      typedef _CharT char_type;
      typedef _OutIter iter_type;

      explicit
      time_put_byname(const char*, size_t __refs = 0)
      : time_put<_CharT, _OutIter>(__refs)
      { };

    protected:
      virtual
      ~time_put_byname() { }
    };
  class money_base
  {
  public:
    enum part { none, space, symbol, sign, value };
    struct pattern { char field[4]; };

    static const pattern _S_default_pattern;

    enum
    {
      _S_minus,
      _S_zero,
      _S_end = 11
    };



    static const char* _S_atoms;



    static pattern
    _S_construct_pattern(char __precedes, char __space, char __posn);
  };

  template<typename _CharT, bool _Intl>
    struct __moneypunct_cache : public locale::facet
    {
      const char* _M_grouping;
      size_t _M_grouping_size;
      bool _M_use_grouping;
      _CharT _M_decimal_point;
      _CharT _M_thousands_sep;
      const _CharT* _M_curr_symbol;
      size_t _M_curr_symbol_size;
      const _CharT* _M_positive_sign;
      size_t _M_positive_sign_size;
      const _CharT* _M_negative_sign;
      size_t _M_negative_sign_size;
      int _M_frac_digits;
      money_base::pattern _M_pos_format;
      money_base::pattern _M_neg_format;




      _CharT _M_atoms[money_base::_S_end];

      bool _M_allocated;

      __moneypunct_cache(size_t __refs = 0) : facet(__refs),
      _M_grouping(__null), _M_grouping_size(0), _M_use_grouping(false),
      _M_decimal_point(_CharT()), _M_thousands_sep(_CharT()),
      _M_curr_symbol(__null), _M_curr_symbol_size(0),
      _M_positive_sign(__null), _M_positive_sign_size(0),
      _M_negative_sign(__null), _M_negative_sign_size(0),
      _M_frac_digits(0),
      _M_pos_format(money_base::pattern()),
      _M_neg_format(money_base::pattern()), _M_allocated(false)
      { }

      ~__moneypunct_cache();

      void
      _M_cache(const locale& __loc);

    private:
      __moneypunct_cache&
      operator=(const __moneypunct_cache&);

      explicit
      __moneypunct_cache(const __moneypunct_cache&);
    };

  template<typename _CharT, bool _Intl>
    __moneypunct_cache<_CharT, _Intl>::~__moneypunct_cache()
    {
      if (_M_allocated)
 {
   delete [] _M_grouping;
   delete [] _M_curr_symbol;
   delete [] _M_positive_sign;
   delete [] _M_negative_sign;
 }
    }







  template<typename _CharT, bool _Intl>
    class moneypunct : public locale::facet, public money_base
    {
    public:



      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;

      typedef __moneypunct_cache<_CharT, _Intl> __cache_type;

    private:
      __cache_type* _M_data;

    public:


      static const bool intl = _Intl;

      static locale::id id;
      explicit
      moneypunct(size_t __refs = 0) : facet(__refs), _M_data(__null)
      { _M_initialize_moneypunct(); }
      explicit
      moneypunct(__cache_type* __cache, size_t __refs = 0)
      : facet(__refs), _M_data(__cache)
      { _M_initialize_moneypunct(); }
      explicit
      moneypunct(__c_locale __cloc, const char* __s, size_t __refs = 0)
      : facet(__refs), _M_data(__null)
      { _M_initialize_moneypunct(__cloc, __s); }
      char_type
      decimal_point() const
      { return this->do_decimal_point(); }
      char_type
      thousands_sep() const
      { return this->do_thousands_sep(); }
      string
      grouping() const
      { return this->do_grouping(); }
      string_type
      curr_symbol() const
      { return this->do_curr_symbol(); }
      string_type
      positive_sign() const
      { return this->do_positive_sign(); }
      string_type
      negative_sign() const
      { return this->do_negative_sign(); }
      int
      frac_digits() const
      { return this->do_frac_digits(); }
      pattern
      pos_format() const
      { return this->do_pos_format(); }

      pattern
      neg_format() const
      { return this->do_neg_format(); }


    protected:

      virtual
      ~moneypunct();
      virtual char_type
      do_decimal_point() const
      { return _M_data->_M_decimal_point; }
      virtual char_type
      do_thousands_sep() const
      { return _M_data->_M_thousands_sep; }
      virtual string
      do_grouping() const
      { return _M_data->_M_grouping; }
      virtual string_type
      do_curr_symbol() const
      { return _M_data->_M_curr_symbol; }
      virtual string_type
      do_positive_sign() const
      { return _M_data->_M_positive_sign; }
      virtual string_type
      do_negative_sign() const
      { return _M_data->_M_negative_sign; }
      virtual int
      do_frac_digits() const
      { return _M_data->_M_frac_digits; }
      virtual pattern
      do_pos_format() const
      { return _M_data->_M_pos_format; }
      virtual pattern
      do_neg_format() const
      { return _M_data->_M_neg_format; }


       void
       _M_initialize_moneypunct(__c_locale __cloc = __null,
    const char* __name = __null);
    };

  template<typename _CharT, bool _Intl>
    locale::id moneypunct<_CharT, _Intl>::id;

  template<typename _CharT, bool _Intl>
    const bool moneypunct<_CharT, _Intl>::intl;

  template<>
    moneypunct<char, true>::~moneypunct();

  template<>
    moneypunct<char, false>::~moneypunct();

  template<>
    void
    moneypunct<char, true>::_M_initialize_moneypunct(__c_locale, const char*);

  template<>
    void
    moneypunct<char, false>::_M_initialize_moneypunct(__c_locale, const char*);


  template<>
    moneypunct<wchar_t, true>::~moneypunct();

  template<>
    moneypunct<wchar_t, false>::~moneypunct();

  template<>
    void
    moneypunct<wchar_t, true>::_M_initialize_moneypunct(__c_locale,
       const char*);

  template<>
    void
    moneypunct<wchar_t, false>::_M_initialize_moneypunct(__c_locale,
        const char*);



  template<typename _CharT, bool _Intl>
    class moneypunct_byname : public moneypunct<_CharT, _Intl>
    {
    public:
      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;

      static const bool intl = _Intl;

      explicit
      moneypunct_byname(const char* __s, size_t __refs = 0)
      : moneypunct<_CharT, _Intl>(__refs)
      {
 if (std::strcmp(__s, "C") != 0 && std::strcmp(__s, "POSIX") != 0)
   {
     __c_locale __tmp;
     this->_S_create_c_locale(__tmp, __s);
     this->_M_initialize_moneypunct(__tmp);
     this->_S_destroy_c_locale(__tmp);
   }
      }

    protected:
      virtual
      ~moneypunct_byname() { }
    };

  template<typename _CharT, bool _Intl>
    const bool moneypunct_byname<_CharT, _Intl>::intl;
  template<typename _CharT, typename _InIter>
    class money_get : public locale::facet
    {
    public:



      typedef _CharT char_type;
      typedef _InIter iter_type;
      typedef basic_string<_CharT> string_type;



      static locale::id id;
      explicit
      money_get(size_t __refs = 0) : facet(__refs) { }
      iter_type
      get(iter_type __s, iter_type __end, bool __intl, ios_base& __io,
   ios_base::iostate& __err, long double& __units) const
      { return this->do_get(__s, __end, __intl, __io, __err, __units); }
      iter_type
      get(iter_type __s, iter_type __end, bool __intl, ios_base& __io,
   ios_base::iostate& __err, string_type& __digits) const
      { return this->do_get(__s, __end, __intl, __io, __err, __digits); }

    protected:

      virtual
      ~money_get() { }
      virtual iter_type
      do_get(iter_type __s, iter_type __end, bool __intl, ios_base& __io,
      ios_base::iostate& __err, long double& __units) const;
      virtual iter_type
      do_get(iter_type __s, iter_type __end, bool __intl, ios_base& __io,
      ios_base::iostate& __err, string_type& __digits) const;
      template<bool _Intl>
        iter_type
        _M_extract(iter_type __s, iter_type __end, ios_base& __io,
     ios_base::iostate& __err, string& __digits) const;
    };

  template<typename _CharT, typename _InIter>
    locale::id money_get<_CharT, _InIter>::id;
  template<typename _CharT, typename _OutIter>
    class money_put : public locale::facet
    {
    public:


      typedef _CharT char_type;
      typedef _OutIter iter_type;
      typedef basic_string<_CharT> string_type;



      static locale::id id;
      explicit
      money_put(size_t __refs = 0) : facet(__refs) { }
      iter_type
      put(iter_type __s, bool __intl, ios_base& __io,
   char_type __fill, long double __units) const
      { return this->do_put(__s, __intl, __io, __fill, __units); }
      iter_type
      put(iter_type __s, bool __intl, ios_base& __io,
   char_type __fill, const string_type& __digits) const
      { return this->do_put(__s, __intl, __io, __fill, __digits); }

    protected:

      virtual
      ~money_put() { }
      virtual iter_type
      do_put(iter_type __s, bool __intl, ios_base& __io, char_type __fill,
      long double __units) const;
      virtual iter_type
      do_put(iter_type __s, bool __intl, ios_base& __io, char_type __fill,
      const string_type& __digits) const;
      template<bool _Intl>
        iter_type
        _M_insert(iter_type __s, ios_base& __io, char_type __fill,
    const string_type& __digits) const;
    };

  template<typename _CharT, typename _OutIter>
    locale::id money_put<_CharT, _OutIter>::id;






  struct messages_base
  {
    typedef int catalog;
  };
  template<typename _CharT>
    class messages : public locale::facet, public messages_base
    {
    public:



      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;


    protected:


      __c_locale _M_c_locale_messages;
      const char* _M_name_messages;

    public:

      static locale::id id;
      explicit
      messages(size_t __refs = 0);
      explicit
      messages(__c_locale __cloc, const char* __s, size_t __refs = 0);
      catalog
      open(const basic_string<char>& __s, const locale& __loc) const
      { return this->do_open(__s, __loc); }
      catalog
      open(const basic_string<char>&, const locale&, const char*) const;
      string_type
      get(catalog __c, int __set, int __msgid, const string_type& __s) const
      { return this->do_get(__c, __set, __msgid, __s); }
      void
      close(catalog __c) const
      { return this->do_close(__c); }

    protected:

      virtual
      ~messages();
      virtual catalog
      do_open(const basic_string<char>&, const locale&) const;
      virtual string_type
      do_get(catalog, int, int, const string_type& __dfault) const;






      virtual void
      do_close(catalog) const;


      char*
      _M_convert_to_char(const string_type& __msg) const
      {

 return reinterpret_cast<char*>(const_cast<_CharT*>(__msg.c_str()));
      }


      string_type
      _M_convert_from_char(char*) const
      {
 return string_type();
      }
     };

  template<typename _CharT>
    locale::id messages<_CharT>::id;


  template<>
    string
    messages<char>::do_get(catalog, int, int, const string&) const;


  template<>
    wstring
    messages<wchar_t>::do_get(catalog, int, int, const wstring&) const;



   template<typename _CharT>
    class messages_byname : public messages<_CharT>
    {
    public:
      typedef _CharT char_type;
      typedef basic_string<_CharT> string_type;

      explicit
      messages_byname(const char* __s, size_t __refs = 0);

    protected:
      virtual
      ~messages_byname()
      { }
    };

}



namespace std __attribute__ ((__visibility__ ("default"))) {


  template<typename _CharT>
     messages<_CharT>::messages(size_t __refs)
     : facet(__refs)
     { _M_c_locale_messages = _S_get_c_locale(); }

  template<typename _CharT>
     messages<_CharT>::messages(__c_locale, const char*, size_t __refs)
     : facet(__refs)
     { _M_c_locale_messages = _S_get_c_locale(); }

  template<typename _CharT>
    typename messages<_CharT>::catalog
    messages<_CharT>::open(const basic_string<char>& __s, const locale& __loc,
      const char*) const
    { return this->do_open(__s, __loc); }


  template<typename _CharT>
    messages<_CharT>::~messages()
    { _S_destroy_c_locale(_M_c_locale_messages); }

  template<typename _CharT>
    typename messages<_CharT>::catalog
    messages<_CharT>::do_open(const basic_string<char>&, const locale&) const
    { return 0; }

  template<typename _CharT>
    typename messages<_CharT>::string_type
    messages<_CharT>::do_get(catalog, int, int,
        const string_type& __dfault) const
    { return __dfault; }

  template<typename _CharT>
    void
    messages<_CharT>::do_close(catalog) const
    { }


   template<typename _CharT>
     messages_byname<_CharT>::messages_byname(const char* __s, size_t __refs)
     : messages<_CharT>(__refs)
     {
 if (std::strcmp(__s, "C") != 0 && std::strcmp(__s, "POSIX") != 0)
   {
     this->_S_destroy_c_locale(this->_M_c_locale_messages);
     this->_S_create_c_locale(this->_M_c_locale_messages, __s);
   }
     }

}

namespace std __attribute__ ((__visibility__ ("default"))) {







  template<typename _CharT>
    inline bool
    isspace(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::space, __c); }


  template<typename _CharT>
    inline bool
    isprint(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::print, __c); }


  template<typename _CharT>
    inline bool
    iscntrl(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::cntrl, __c); }


  template<typename _CharT>
    inline bool
    isupper(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::upper, __c); }


  template<typename _CharT>
    inline bool
    islower(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::lower, __c); }


  template<typename _CharT>
    inline bool
    isalpha(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::alpha, __c); }


  template<typename _CharT>
    inline bool
    isdigit(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::digit, __c); }


  template<typename _CharT>
    inline bool
    ispunct(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::punct, __c); }


  template<typename _CharT>
    inline bool
    isxdigit(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::xdigit, __c); }


  template<typename _CharT>
    inline bool
    isalnum(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::alnum, __c); }


  template<typename _CharT>
    inline bool
    isgraph(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).is(ctype_base::graph, __c); }


  template<typename _CharT>
    inline _CharT
    toupper(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).toupper(__c); }


  template<typename _CharT>
    inline _CharT
    tolower(_CharT __c, const locale& __loc)
    { return use_facet<ctype<_CharT> >(__loc).tolower(__c); }

}

namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _CharT, typename _Traits>
    class basic_ios : public ios_base
    {
    public:






      typedef _CharT char_type;
      typedef typename _Traits::int_type int_type;
      typedef typename _Traits::pos_type pos_type;
      typedef typename _Traits::off_type off_type;
      typedef _Traits traits_type;
      typedef ctype<_CharT> __ctype_type;
      typedef num_put<_CharT, ostreambuf_iterator<_CharT, _Traits> >
           __num_put_type;
      typedef num_get<_CharT, istreambuf_iterator<_CharT, _Traits> >
           __num_get_type;



    protected:
      basic_ostream<_CharT, _Traits>* _M_tie;
      mutable char_type _M_fill;
      mutable bool _M_fill_init;
      basic_streambuf<_CharT, _Traits>* _M_streambuf;


      const __ctype_type* _M_ctype;

      const __num_put_type* _M_num_put;

      const __num_get_type* _M_num_get;

    public:







      operator void*() const
      { return this->fail() ? 0 : const_cast<basic_ios*>(this); }

      bool
      operator!() const
      { return this->fail(); }
      iostate
      rdstate() const
      { return _M_streambuf_state; }
      void
      clear(iostate __state = goodbit);







      void
      setstate(iostate __state)
      { this->clear(this->rdstate() | __state); }




      void
      _M_setstate(iostate __state)
      {


 _M_streambuf_state |= __state;
 if (this->exceptions() & __state)
                          ;
      }







      bool
      good() const
      { return this->rdstate() == 0; }







      bool
      eof() const
      { return (this->rdstate() & eofbit) != 0; }
      bool
      fail() const
      { return (this->rdstate() & (badbit | failbit)) != 0; }







      bool
      bad() const
      { return (this->rdstate() & badbit) != 0; }
      iostate
      exceptions() const
      { return _M_exception; }
      void
      exceptions(iostate __except)
      {
        _M_exception = __except;
        this->clear(_M_streambuf_state);
      }







      explicit
      basic_ios(basic_streambuf<_CharT, _Traits>* __sb)
      : ios_base(), _M_tie(0), _M_fill(), _M_fill_init(false), _M_streambuf(0),
      _M_ctype(0), _M_num_put(0), _M_num_get(0)
      { this->init(__sb); }







      virtual
      ~basic_ios() { }
      basic_ostream<_CharT, _Traits>*
      tie() const
      { return _M_tie; }
      basic_ostream<_CharT, _Traits>*
      tie(basic_ostream<_CharT, _Traits>* __tiestr)
      {
        basic_ostream<_CharT, _Traits>* __old = _M_tie;
        _M_tie = __tiestr;
        return __old;
      }







      basic_streambuf<_CharT, _Traits>*
      rdbuf() const
      { return _M_streambuf; }
      basic_streambuf<_CharT, _Traits>*
      rdbuf(basic_streambuf<_CharT, _Traits>* __sb);
      basic_ios&
      copyfmt(const basic_ios& __rhs);







      char_type
      fill() const
      {
 if (!_M_fill_init)
   {
     _M_fill = this->widen(' ');
     _M_fill_init = true;
   }
 return _M_fill;
      }
      char_type
      fill(char_type __ch)
      {
 char_type __old = this->fill();
 _M_fill = __ch;
 return __old;
      }
      locale
      imbue(const locale& __loc);
      char
      narrow(char_type __c, char __dfault) const;
      char_type
      widen(char __c) const;

    protected:







      basic_ios()
      : ios_base(), _M_tie(0), _M_fill(char_type()), _M_fill_init(false),
      _M_streambuf(0), _M_ctype(0), _M_num_put(0), _M_num_get(0)
      { }







      void
      init(basic_streambuf<_CharT, _Traits>* __sb);

      void
      _M_cache_locale(const locale& __loc);
    };

}




namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _CharT, typename _Traits>
    void
    basic_ios<_CharT, _Traits>::clear(iostate __state)
    {
      if (this->rdbuf())
 _M_streambuf_state = __state;
      else
   _M_streambuf_state = __state | badbit;
      if (this->exceptions() & this->rdstate())
 __throw_ios_failure(("basic_ios::clear"));
    }

  template<typename _CharT, typename _Traits>
    basic_streambuf<_CharT, _Traits>*
    basic_ios<_CharT, _Traits>::rdbuf(basic_streambuf<_CharT, _Traits>* __sb)
    {
      basic_streambuf<_CharT, _Traits>* __old = _M_streambuf;
      _M_streambuf = __sb;
      this->clear();
      return __old;
    }

  template<typename _CharT, typename _Traits>
    basic_ios<_CharT, _Traits>&
    basic_ios<_CharT, _Traits>::copyfmt(const basic_ios& __rhs)
    {


      if (this != &__rhs)
 {




   _Words* __words = (__rhs._M_word_size <= _S_local_word_size) ?
                      _M_local_word : new _Words[__rhs._M_word_size];


   _Callback_list* __cb = __rhs._M_callbacks;
   if (__cb)
     __cb->_M_add_reference();
   _M_call_callbacks(erase_event);
   if (_M_word != _M_local_word)
     {
       delete [] _M_word;
       _M_word = 0;
     }
   _M_dispose_callbacks();


   _M_callbacks = __cb;
   for (int __i = 0; __i < __rhs._M_word_size; ++__i)
     __words[__i] = __rhs._M_word[__i];
   _M_word = __words;
   _M_word_size = __rhs._M_word_size;

   this->flags(__rhs.flags());
   this->width(__rhs.width());
   this->precision(__rhs.precision());
   this->tie(__rhs.tie());
   this->fill(__rhs.fill());
   _M_ios_locale = __rhs.getloc();
   _M_cache_locale(_M_ios_locale);

   _M_call_callbacks(copyfmt_event);


   this->exceptions(__rhs.exceptions());
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    char
    basic_ios<_CharT, _Traits>::narrow(char_type __c, char __dfault) const
    { return __check_facet(_M_ctype).narrow(__c, __dfault); }

  template<typename _CharT, typename _Traits>
    _CharT
    basic_ios<_CharT, _Traits>::widen(char __c) const
    { return __check_facet(_M_ctype).widen(__c); }


  template<typename _CharT, typename _Traits>
    locale
    basic_ios<_CharT, _Traits>::imbue(const locale& __loc)
    {
      locale __old(this->getloc());
      ios_base::imbue(__loc);
      _M_cache_locale(__loc);
      if (this->rdbuf() != 0)
 this->rdbuf()->pubimbue(__loc);
      return __old;
    }

  template<typename _CharT, typename _Traits>
    void
    basic_ios<_CharT, _Traits>::init(basic_streambuf<_CharT, _Traits>* __sb)
    {

      ios_base::_M_init();


      _M_cache_locale(_M_ios_locale);
      _M_fill = _CharT();
      _M_fill_init = false;

      _M_tie = 0;
      _M_exception = goodbit;
      _M_streambuf = __sb;
      _M_streambuf_state = __sb ? goodbit : badbit;
    }

  template<typename _CharT, typename _Traits>
    void
    basic_ios<_CharT, _Traits>::_M_cache_locale(const locale& __loc)
    {
      if (__builtin_expect(has_facet<__ctype_type>(__loc), true))
 _M_ctype = &use_facet<__ctype_type>(__loc);
      else
 _M_ctype = 0;

      if (__builtin_expect(has_facet<__num_put_type>(__loc), true))
 _M_num_put = &use_facet<__num_put_type>(__loc);
      else
 _M_num_put = 0;

      if (__builtin_expect(has_facet<__num_get_type>(__loc), true))
 _M_num_get = &use_facet<__num_get_type>(__loc);
      else
 _M_num_get = 0;
    }





  extern template class basic_ios<char>;


  extern template class basic_ios<wchar_t>;



}


namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _CharT, typename _Traits>
    class basic_ostream : virtual public basic_ios<_CharT, _Traits>
    {
    public:

      typedef _CharT char_type;
      typedef typename _Traits::int_type int_type;
      typedef typename _Traits::pos_type pos_type;
      typedef typename _Traits::off_type off_type;
      typedef _Traits traits_type;


      typedef basic_streambuf<_CharT, _Traits> __streambuf_type;
      typedef basic_ios<_CharT, _Traits> __ios_type;
      typedef basic_ostream<_CharT, _Traits> __ostream_type;
      typedef num_put<_CharT, ostreambuf_iterator<_CharT, _Traits> >
             __num_put_type;
      typedef ctype<_CharT> __ctype_type;
      explicit
      basic_ostream(__streambuf_type* __sb)
      { this->init(__sb); }






      virtual
      ~basic_ostream() { }


      class sentry;
      friend class sentry;
      __ostream_type&
      operator<<(__ostream_type& (*__pf)(__ostream_type&))
      {



 return __pf(*this);
      }

      __ostream_type&
      operator<<(__ios_type& (*__pf)(__ios_type&))
      {



 __pf(*this);
 return *this;
      }

      __ostream_type&
      operator<<(ios_base& (*__pf) (ios_base&))
      {



 __pf(*this);
 return *this;
      }
      __ostream_type&
      operator<<(long __n)
      { return _M_insert(__n); }

      __ostream_type&
      operator<<(unsigned long __n)
      { return _M_insert(__n); }

      __ostream_type&
      operator<<(bool __n)
      { return _M_insert(__n); }

      __ostream_type&
      operator<<(short __n);

      __ostream_type&
      operator<<(unsigned short __n)
      {


 return _M_insert(static_cast<unsigned long>(__n));
      }

      __ostream_type&
      operator<<(int __n);

      __ostream_type&
      operator<<(unsigned int __n)
      {


 return _M_insert(static_cast<unsigned long>(__n));
      }


      __ostream_type&
      operator<<(long long __n)
      { return _M_insert(__n); }

      __ostream_type&
      operator<<(unsigned long long __n)
      { return _M_insert(__n); }


      __ostream_type&
      operator<<(double __f)
      { return _M_insert(__f); }

      __ostream_type&
      operator<<(float __f)
      {


 return _M_insert(static_cast<double>(__f));
      }

      __ostream_type&
      operator<<(long double __f)
      { return _M_insert(__f); }

      __ostream_type&
      operator<<(const void* __p)
      { return _M_insert(__p); }
      __ostream_type&
      operator<<(__streambuf_type* __sb);
      __ostream_type&
      put(char_type __c);


      void
      _M_write(const char_type* __s, streamsize __n)
      {
 const streamsize __put = this->rdbuf()->sputn(__s, __n);
 if (__put != __n)
   this->setstate(ios_base::badbit);
      }
      __ostream_type&
      write(const char_type* __s, streamsize __n);
      __ostream_type&
      flush();
      pos_type
      tellp();
      __ostream_type&
      seekp(pos_type);
       __ostream_type&
      seekp(off_type, ios_base::seekdir);

    protected:
      explicit
      basic_ostream() { }

      template<typename _ValueT>
        __ostream_type&
        _M_insert(_ValueT __v);
    };
  template <typename _CharT, typename _Traits>
    class basic_ostream<_CharT, _Traits>::sentry
    {

      bool _M_ok;
      basic_ostream<_CharT, _Traits>& _M_os;

    public:
      explicit
      sentry(basic_ostream<_CharT, _Traits>& __os);
      ~sentry()
      {

 if (_M_os.flags() & ios_base::unitbuf && !uncaught_exception())
   {

     if (_M_os.rdbuf() && _M_os.rdbuf()->pubsync() == -1)
       _M_os.setstate(ios_base::badbit);
   }
      }
      operator bool() const
      { return _M_ok; }
    };
  template<typename _CharT, typename _Traits>
    inline basic_ostream<_CharT, _Traits>&
    operator<<(basic_ostream<_CharT, _Traits>& __out, _CharT __c)
    { return __ostream_insert(__out, &__c, 1); }

  template<typename _CharT, typename _Traits>
    inline basic_ostream<_CharT, _Traits>&
    operator<<(basic_ostream<_CharT, _Traits>& __out, char __c)
    { return (__out << __out.widen(__c)); }


  template <class _Traits>
    inline basic_ostream<char, _Traits>&
    operator<<(basic_ostream<char, _Traits>& __out, char __c)
    { return __ostream_insert(__out, &__c, 1); }


  template<class _Traits>
    inline basic_ostream<char, _Traits>&
    operator<<(basic_ostream<char, _Traits>& __out, signed char __c)
    { return (__out << static_cast<char>(__c)); }

  template<class _Traits>
    inline basic_ostream<char, _Traits>&
    operator<<(basic_ostream<char, _Traits>& __out, unsigned char __c)
    { return (__out << static_cast<char>(__c)); }
  template<typename _CharT, typename _Traits>
    inline basic_ostream<_CharT, _Traits>&
    operator<<(basic_ostream<_CharT, _Traits>& __out, const _CharT* __s)
    {
      if (!__s)
 __out.setstate(ios_base::badbit);
      else
 __ostream_insert(__out, __s,
    static_cast<streamsize>(_Traits::length(__s)));
      return __out;
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits> &
    operator<<(basic_ostream<_CharT, _Traits>& __out, const char* __s);


  template<class _Traits>
    inline basic_ostream<char, _Traits>&
    operator<<(basic_ostream<char, _Traits>& __out, const char* __s)
    {
      if (!__s)
 __out.setstate(ios_base::badbit);
      else
 __ostream_insert(__out, __s,
    static_cast<streamsize>(_Traits::length(__s)));
      return __out;
    }


  template<class _Traits>
    inline basic_ostream<char, _Traits>&
    operator<<(basic_ostream<char, _Traits>& __out, const signed char* __s)
    { return (__out << reinterpret_cast<const char*>(__s)); }

  template<class _Traits>
    inline basic_ostream<char, _Traits> &
    operator<<(basic_ostream<char, _Traits>& __out, const unsigned char* __s)
    { return (__out << reinterpret_cast<const char*>(__s)); }
  template<typename _CharT, typename _Traits>
    inline basic_ostream<_CharT, _Traits>&
    endl(basic_ostream<_CharT, _Traits>& __os)
    { return flush(__os.put(__os.widen('\n'))); }







  template<typename _CharT, typename _Traits>
    inline basic_ostream<_CharT, _Traits>&
    ends(basic_ostream<_CharT, _Traits>& __os)
    { return __os.put(_CharT()); }






  template<typename _CharT, typename _Traits>
    inline basic_ostream<_CharT, _Traits>&
    flush(basic_ostream<_CharT, _Traits>& __os)
    { return __os.flush(); }

}











extern "C++" {

namespace __cxxabiv1
{
  class __class_type_info;
}
namespace std
{






  class type_info
  {
  public:




    virtual ~type_info();



    const char* name() const
    { return __name; }
    bool before(const type_info& __arg) const
    { return __name < __arg.__name; }

    bool operator==(const type_info& __arg) const
    { return __name == __arg.__name; }

    bool operator!=(const type_info& __arg) const
    { return !operator==(__arg); }


    virtual bool __is_pointer_p() const;


    virtual bool __is_function_p() const;







    virtual bool __do_catch(const type_info *__thr_type, void **__thr_obj,
       unsigned __outer) const;


    virtual bool __do_upcast(const __cxxabiv1::__class_type_info *__target,
        void **__obj_ptr) const;

  protected:
    const char *__name;

    explicit type_info(const char *__n): __name(__n) { }

  private:

    type_info& operator=(const type_info&);
    type_info(const type_info&);
  };






  class bad_cast : public exception
  {
  public:
    bad_cast() throw() { }



    virtual ~bad_cast() throw();


    virtual const char* what() const throw();
  };


  class bad_typeid : public exception
  {
  public:
    bad_typeid () throw() { }



    virtual ~bad_typeid() throw();


    virtual const char* what() const throw();
  };
}


}



namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _Facet>
    locale
    locale::combine(const locale& __other) const
    {
      _Impl* __tmp = new _Impl(*_M_impl, 1);
      if (true)
 {
   __tmp->_M_replace_facet(__other._M_impl, &_Facet::id);
 }
      if (false)
 {
   __tmp->_M_remove_reference();
                          ;
 }
      return locale(__tmp);
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    bool
    locale::operator()(const basic_string<_CharT, _Traits, _Alloc>& __s1,
                       const basic_string<_CharT, _Traits, _Alloc>& __s2) const
    {
      typedef std::collate<_CharT> __collate_type;
      const __collate_type& __collate = use_facet<__collate_type>(*this);
      return (__collate.compare(__s1.data(), __s1.data() + __s1.length(),
    __s2.data(), __s2.data() + __s2.length()) < 0);
    }
  template<typename _Facet>
    inline bool
    has_facet(const locale& __loc) throw()
    {
      const size_t __i = _Facet::id._M_id();
      const locale::facet** __facets = __loc._M_impl->_M_facets;
      return (__i < __loc._M_impl->_M_facets_size && __facets[__i]);
    }
  template<typename _Facet>
    inline const _Facet&
    use_facet(const locale& __loc)
    {
      const size_t __i = _Facet::id._M_id();
      const locale::facet** __facets = __loc._M_impl->_M_facets;
      if (!(__i < __loc._M_impl->_M_facets_size && __facets[__i]))
        __throw_bad_cast();
      return static_cast<const _Facet&>(*__facets[__i]);
    }




  template<typename _Facet>
    struct __use_cache
    {
      const _Facet*
      operator() (const locale& __loc) const;
    };


  template<typename _CharT>
    struct __use_cache<__numpunct_cache<_CharT> >
    {
      const __numpunct_cache<_CharT>*
      operator() (const locale& __loc) const
      {
 const size_t __i = numpunct<_CharT>::id._M_id();
 const locale::facet** __caches = __loc._M_impl->_M_caches;
 if (!__caches[__i])
   {
     __numpunct_cache<_CharT>* __tmp = __null;
     if (true)
       {
  __tmp = new __numpunct_cache<_CharT>;
  __tmp->_M_cache(__loc);
       }
     if (false)
       {
  delete __tmp;
                         ;
       }
     __loc._M_impl->_M_install_cache(__tmp, __i);
   }
 return static_cast<const __numpunct_cache<_CharT>*>(__caches[__i]);
      }
    };

  template<typename _CharT, bool _Intl>
    struct __use_cache<__moneypunct_cache<_CharT, _Intl> >
    {
      const __moneypunct_cache<_CharT, _Intl>*
      operator() (const locale& __loc) const
      {
 const size_t __i = moneypunct<_CharT, _Intl>::id._M_id();
 const locale::facet** __caches = __loc._M_impl->_M_caches;
 if (!__caches[__i])
   {
     __moneypunct_cache<_CharT, _Intl>* __tmp = __null;
     if (true)
       {
  __tmp = new __moneypunct_cache<_CharT, _Intl>;
  __tmp->_M_cache(__loc);
       }
     if (false)
       {
  delete __tmp;
                         ;
       }
     __loc._M_impl->_M_install_cache(__tmp, __i);
   }
 return static_cast<
   const __moneypunct_cache<_CharT, _Intl>*>(__caches[__i]);
      }
    };

  template<typename _CharT>
    void
    __numpunct_cache<_CharT>::_M_cache(const locale& __loc)
    {
      _M_allocated = true;

      const numpunct<_CharT>& __np = use_facet<numpunct<_CharT> >(__loc);

      _M_grouping_size = __np.grouping().size();
      char* __grouping = new char[_M_grouping_size];
      __np.grouping().copy(__grouping, _M_grouping_size);
      _M_grouping = __grouping;
      _M_use_grouping = (_M_grouping_size
    && static_cast<signed char>(__np.grouping()[0]) > 0);

      _M_truename_size = __np.truename().size();
      _CharT* __truename = new _CharT[_M_truename_size];
      __np.truename().copy(__truename, _M_truename_size);
      _M_truename = __truename;

      _M_falsename_size = __np.falsename().size();
      _CharT* __falsename = new _CharT[_M_falsename_size];
      __np.falsename().copy(__falsename, _M_falsename_size);
      _M_falsename = __falsename;

      _M_decimal_point = __np.decimal_point();
      _M_thousands_sep = __np.thousands_sep();

      const ctype<_CharT>& __ct = use_facet<ctype<_CharT> >(__loc);
      __ct.widen(__num_base::_S_atoms_out,
   __num_base::_S_atoms_out + __num_base::_S_oend, _M_atoms_out);
      __ct.widen(__num_base::_S_atoms_in,
   __num_base::_S_atoms_in + __num_base::_S_iend, _M_atoms_in);
    }

  template<typename _CharT, bool _Intl>
    void
    __moneypunct_cache<_CharT, _Intl>::_M_cache(const locale& __loc)
    {
      _M_allocated = true;

      const moneypunct<_CharT, _Intl>& __mp =
 use_facet<moneypunct<_CharT, _Intl> >(__loc);

      _M_grouping_size = __mp.grouping().size();
      char* __grouping = new char[_M_grouping_size];
      __mp.grouping().copy(__grouping, _M_grouping_size);
      _M_grouping = __grouping;
      _M_use_grouping = (_M_grouping_size
    && static_cast<signed char>(__mp.grouping()[0]) > 0);

      _M_decimal_point = __mp.decimal_point();
      _M_thousands_sep = __mp.thousands_sep();
      _M_frac_digits = __mp.frac_digits();

      _M_curr_symbol_size = __mp.curr_symbol().size();
      _CharT* __curr_symbol = new _CharT[_M_curr_symbol_size];
      __mp.curr_symbol().copy(__curr_symbol, _M_curr_symbol_size);
      _M_curr_symbol = __curr_symbol;

      _M_positive_sign_size = __mp.positive_sign().size();
      _CharT* __positive_sign = new _CharT[_M_positive_sign_size];
      __mp.positive_sign().copy(__positive_sign, _M_positive_sign_size);
      _M_positive_sign = __positive_sign;

      _M_negative_sign_size = __mp.negative_sign().size();
      _CharT* __negative_sign = new _CharT[_M_negative_sign_size];
      __mp.negative_sign().copy(__negative_sign, _M_negative_sign_size);
      _M_negative_sign = __negative_sign;

      _M_pos_format = __mp.pos_format();
      _M_neg_format = __mp.neg_format();

      const ctype<_CharT>& __ct = use_facet<ctype<_CharT> >(__loc);
      __ct.widen(money_base::_S_atoms,
   money_base::_S_atoms + money_base::_S_end, _M_atoms);
    }
  static bool
  __verify_grouping(const char* __grouping, size_t __grouping_size,
      const string& __grouping_tmp);



  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    _M_extract_float(_InIter __beg, _InIter __end, ios_base& __io,
       ios_base::iostate& __err, string& __xtrc) const
    {
      typedef char_traits<_CharT> __traits_type;
      typedef __numpunct_cache<_CharT> __cache_type;
      __use_cache<__cache_type> __uc;
      const locale& __loc = __io._M_getloc();
      const __cache_type* __lc = __uc(__loc);
      const _CharT* __lit = __lc->_M_atoms_in;
      char_type __c = char_type();


      bool __testeof = __beg == __end;


      if (!__testeof)
 {
   __c = *__beg;
   const bool __plus = __c == __lit[__num_base::_S_iplus];
   if ((__plus || __c == __lit[__num_base::_S_iminus])
       && !(__lc->_M_use_grouping && __c == __lc->_M_thousands_sep)
       && !(__c == __lc->_M_decimal_point))
     {
       __xtrc += __plus ? '+' : '-';
       if (++__beg != __end)
  __c = *__beg;
       else
  __testeof = true;
     }
 }


      bool __found_mantissa = false;
      int __sep_pos = 0;
      while (!__testeof)
 {
   if (__lc->_M_use_grouping && __c == __lc->_M_thousands_sep
       || __c == __lc->_M_decimal_point)
     break;
   else if (__c == __lit[__num_base::_S_izero])
     {
       if (!__found_mantissa)
  {
    __xtrc += '0';
    __found_mantissa = true;
  }
       ++__sep_pos;

       if (++__beg != __end)
  __c = *__beg;
       else
  __testeof = true;
     }
   else
     break;
 }


      bool __found_dec = false;
      bool __found_sci = false;
      string __found_grouping;
      if (__lc->_M_use_grouping)
 __found_grouping.reserve(32);
      const char_type* __lit_zero = __lit + __num_base::_S_izero;

      if (!__lc->_M_allocated)

 while (!__testeof)
   {
     const int __digit = _M_find(__lit_zero, 10, __c);
     if (__digit != -1)
       {
  __xtrc += '0' + __digit;
  __found_mantissa = true;
       }
     else if (__c == __lc->_M_decimal_point
       && !__found_dec && !__found_sci)
       {
  __xtrc += '.';
  __found_dec = true;
       }
     else if ((__c == __lit[__num_base::_S_ie]
        || __c == __lit[__num_base::_S_iE])
       && !__found_sci && __found_mantissa)
       {

  __xtrc += 'e';
  __found_sci = true;


  if (++__beg != __end)
    {
      __c = *__beg;
      const bool __plus = __c == __lit[__num_base::_S_iplus];
      if (__plus || __c == __lit[__num_base::_S_iminus])
        __xtrc += __plus ? '+' : '-';
      else
        continue;
    }
  else
    {
      __testeof = true;
      break;
    }
       }
     else
       break;

     if (++__beg != __end)
       __c = *__beg;
     else
       __testeof = true;
   }
      else
 while (!__testeof)
   {


     if (__lc->_M_use_grouping && __c == __lc->_M_thousands_sep)
       {
  if (!__found_dec && !__found_sci)
    {


      if (__sep_pos)
        {
   __found_grouping += static_cast<char>(__sep_pos);
   __sep_pos = 0;
        }
      else
        {


   __xtrc.clear();
   break;
        }
    }
  else
    break;
       }
     else if (__c == __lc->_M_decimal_point)
       {
  if (!__found_dec && !__found_sci)
    {



      if (__found_grouping.size())
        __found_grouping += static_cast<char>(__sep_pos);
      __xtrc += '.';
      __found_dec = true;
    }
  else
    break;
       }
     else
       {
  const char_type* __q =
    __traits_type::find(__lit_zero, 10, __c);
  if (__q)
    {
      __xtrc += '0' + (__q - __lit_zero);
      __found_mantissa = true;
      ++__sep_pos;
    }
  else if ((__c == __lit[__num_base::_S_ie]
     || __c == __lit[__num_base::_S_iE])
    && !__found_sci && __found_mantissa)
    {

      if (__found_grouping.size() && !__found_dec)
        __found_grouping += static_cast<char>(__sep_pos);
      __xtrc += 'e';
      __found_sci = true;


      if (++__beg != __end)
        {
   __c = *__beg;
   const bool __plus = __c == __lit[__num_base::_S_iplus];
   if ((__plus || __c == __lit[__num_base::_S_iminus])
       && !(__lc->_M_use_grouping
     && __c == __lc->_M_thousands_sep)
       && !(__c == __lc->_M_decimal_point))
        __xtrc += __plus ? '+' : '-';
   else
     continue;
        }
      else
        {
   __testeof = true;
   break;
        }
    }
  else
    break;
       }

     if (++__beg != __end)
       __c = *__beg;
     else
       __testeof = true;
   }



      if (__found_grouping.size())
        {

   if (!__found_dec && !__found_sci)
     __found_grouping += static_cast<char>(__sep_pos);

          if (!std::__verify_grouping(__lc->_M_grouping,
          __lc->_M_grouping_size,
          __found_grouping))
     __err |= ios_base::failbit;
        }


      if (__testeof)
        __err |= ios_base::eofbit;
      return __beg;
    }





  template<typename _CharT, typename _InIter>
    template<typename _ValueT>
      _InIter
      num_get<_CharT, _InIter>::
      _M_extract_int(_InIter __beg, _InIter __end, ios_base& __io,
       ios_base::iostate& __err, _ValueT& __v) const
      {
        typedef char_traits<_CharT> __traits_type;
 using __gnu_cxx::__add_unsigned;
 typedef typename __add_unsigned<_ValueT>::__type __unsigned_type;
 typedef __numpunct_cache<_CharT> __cache_type;
 __use_cache<__cache_type> __uc;
 const locale& __loc = __io._M_getloc();
 const __cache_type* __lc = __uc(__loc);
 const _CharT* __lit = __lc->_M_atoms_in;
 char_type __c = char_type();


 const ios_base::fmtflags __basefield = __io.flags()
                                        & ios_base::basefield;
 const bool __oct = __basefield == ios_base::oct;
 int __base = __oct ? 8 : (__basefield == ios_base::hex ? 16 : 10);


 bool __testeof = __beg == __end;


 bool __negative = false;
 if (!__testeof)
   {
     __c = *__beg;
     if (numeric_limits<_ValueT>::is_signed)
       __negative = __c == __lit[__num_base::_S_iminus];
     if ((__negative || __c == __lit[__num_base::_S_iplus])
  && !(__lc->_M_use_grouping && __c == __lc->_M_thousands_sep)
  && !(__c == __lc->_M_decimal_point))
       {
  if (++__beg != __end)
    __c = *__beg;
  else
    __testeof = true;
       }
   }



 bool __found_zero = false;
 int __sep_pos = 0;
 while (!__testeof)
   {
     if (__lc->_M_use_grouping && __c == __lc->_M_thousands_sep
  || __c == __lc->_M_decimal_point)
       break;
     else if (__c == __lit[__num_base::_S_izero]
       && (!__found_zero || __base == 10))
       {
  __found_zero = true;
  ++__sep_pos;
  if (__basefield == 0)
    __base = 8;
  if (__base == 8)
    __sep_pos = 0;
       }
     else if (__found_zero
       && (__c == __lit[__num_base::_S_ix]
    || __c == __lit[__num_base::_S_iX]))
       {
  if (__basefield == 0)
    __base = 16;
  if (__base == 16)
    {
      __found_zero = false;
      __sep_pos = 0;
    }
  else
    break;
       }
     else
       break;

     if (++__beg != __end)
       {
  __c = *__beg;
  if (!__found_zero)
    break;
       }
     else
       __testeof = true;
   }



 const size_t __len = (__base == 16 ? __num_base::_S_iend
         - __num_base::_S_izero : __base);


 string __found_grouping;
 if (__lc->_M_use_grouping)
   __found_grouping.reserve(32);
 bool __testfail = false;
 const __unsigned_type __max = __negative ?
   -numeric_limits<_ValueT>::min() : numeric_limits<_ValueT>::max();
 const __unsigned_type __smax = __max / __base;
 __unsigned_type __result = 0;
 int __digit = 0;
 const char_type* __lit_zero = __lit + __num_base::_S_izero;

 if (!__lc->_M_allocated)

   while (!__testeof)
     {
       __digit = _M_find(__lit_zero, __len, __c);
       if (__digit == -1)
  break;

       if (__result > __smax)
  __testfail = true;
       else
  {
    __result *= __base;
    __testfail |= __result > __max - __digit;
    __result += __digit;
    ++__sep_pos;
  }

       if (++__beg != __end)
  __c = *__beg;
       else
  __testeof = true;
     }
 else
   while (!__testeof)
     {


       if (__lc->_M_use_grouping && __c == __lc->_M_thousands_sep)
  {


    if (__sep_pos)
      {
        __found_grouping += static_cast<char>(__sep_pos);
        __sep_pos = 0;
      }
    else
      {
        __testfail = true;
        break;
      }
  }
       else if (__c == __lc->_M_decimal_point)
  break;
       else
  {
    const char_type* __q =
      __traits_type::find(__lit_zero, __len, __c);
    if (!__q)
      break;

    __digit = __q - __lit_zero;
    if (__digit > 15)
      __digit -= 6;
    if (__result > __smax)
      __testfail = true;
    else
      {
        __result *= __base;
        __testfail |= __result > __max - __digit;
        __result += __digit;
        ++__sep_pos;
      }
  }

       if (++__beg != __end)
  __c = *__beg;
       else
  __testeof = true;
     }



 if (__found_grouping.size())
   {

     __found_grouping += static_cast<char>(__sep_pos);

     if (!std::__verify_grouping(__lc->_M_grouping,
     __lc->_M_grouping_size,
     __found_grouping))
       __err |= ios_base::failbit;
   }

 if (!__testfail && (__sep_pos || __found_zero
       || __found_grouping.size()))
   __v = __negative ? -__result : __result;
 else
   __err |= ios_base::failbit;

 if (__testeof)
   __err |= ios_base::eofbit;
 return __beg;
      }



  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, bool& __v) const
    {
      if (!(__io.flags() & ios_base::boolalpha))
        {



   long __l = -1;
          __beg = _M_extract_int(__beg, __end, __io, __err, __l);
   if (__l == 0 || __l == 1)
     __v = __l;
   else
            __err |= ios_base::failbit;
        }
      else
        {

   typedef __numpunct_cache<_CharT> __cache_type;
   __use_cache<__cache_type> __uc;
   const locale& __loc = __io._M_getloc();
   const __cache_type* __lc = __uc(__loc);

   bool __testf = true;
   bool __testt = true;
   size_t __n;
   bool __testeof = __beg == __end;
          for (__n = 0; !__testeof; ++__n)
            {
       const char_type __c = *__beg;

       if (__testf)
  if (__n < __lc->_M_falsename_size)
    __testf = __c == __lc->_M_falsename[__n];
  else
    break;

       if (__testt)
  if (__n < __lc->_M_truename_size)
    __testt = __c == __lc->_M_truename[__n];
  else
    break;

       if (!__testf && !__testt)
  break;

       if (++__beg == __end)
  __testeof = true;
            }
   if (__testf && __n == __lc->_M_falsename_size)
     __v = 0;
   else if (__testt && __n == __lc->_M_truename_size)
     __v = 1;
   else
     __err |= ios_base::failbit;

          if (__testeof)
            __err |= ios_base::eofbit;
        }
      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, long& __v) const
    { return _M_extract_int(__beg, __end, __io, __err, __v); }

  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, unsigned short& __v) const
    { return _M_extract_int(__beg, __end, __io, __err, __v); }

  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, unsigned int& __v) const
    { return _M_extract_int(__beg, __end, __io, __err, __v); }

  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, unsigned long& __v) const
    { return _M_extract_int(__beg, __end, __io, __err, __v); }


  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, long long& __v) const
    { return _M_extract_int(__beg, __end, __io, __err, __v); }

  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, unsigned long long& __v) const
    { return _M_extract_int(__beg, __end, __io, __err, __v); }


  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
    ios_base::iostate& __err, float& __v) const
    {
      string __xtrc;
      __xtrc.reserve(32);
      __beg = _M_extract_float(__beg, __end, __io, __err, __xtrc);
      std::__convert_to_v(__xtrc.c_str(), __v, __err, _S_get_c_locale());
      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, double& __v) const
    {
      string __xtrc;
      __xtrc.reserve(32);
      __beg = _M_extract_float(__beg, __end, __io, __err, __xtrc);
      std::__convert_to_v(__xtrc.c_str(), __v, __err, _S_get_c_locale());
      return __beg;
    }
  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, long double& __v) const
    {
      string __xtrc;
      __xtrc.reserve(32);
      __beg = _M_extract_float(__beg, __end, __io, __err, __xtrc);
      std::__convert_to_v(__xtrc.c_str(), __v, __err, _S_get_c_locale());
      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    num_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, ios_base& __io,
           ios_base::iostate& __err, void*& __v) const
    {

      typedef ios_base::fmtflags fmtflags;
      const fmtflags __fmt = __io.flags();
      __io.flags(__fmt & ~ios_base::basefield | ios_base::hex);

      unsigned long __ul;
      __beg = _M_extract_int(__beg, __end, __io, __err, __ul);


      __io.flags(__fmt);

      if (!(__err & ios_base::failbit))
 __v = reinterpret_cast<void*>(__ul);
      return __beg;
    }



  template<typename _CharT, typename _OutIter>
    void
    num_put<_CharT, _OutIter>::
    _M_pad(_CharT __fill, streamsize __w, ios_base& __io,
    _CharT* __new, const _CharT* __cs, int& __len) const
    {


      __pad<_CharT, char_traits<_CharT> >::_S_pad(__io, __fill, __new, __cs,
        __w, __len, true);
      __len = static_cast<int>(__w);
    }



  template<typename _CharT, typename _ValueT>
    int
    __int_to_char(_CharT* __bufend, _ValueT __v, const _CharT* __lit,
    ios_base::fmtflags __flags, bool __dec)
    {
      _CharT* __buf = __bufend;
      if (__builtin_expect(__dec, true))
 {

   do
     {
       *--__buf = __lit[(__v % 10) + __num_base::_S_odigits];
       __v /= 10;
     }
   while (__v != 0);
 }
      else if ((__flags & ios_base::basefield) == ios_base::oct)
 {

   do
     {
       *--__buf = __lit[(__v & 0x7) + __num_base::_S_odigits];
       __v >>= 3;
     }
   while (__v != 0);
 }
      else
 {

   const bool __uppercase = __flags & ios_base::uppercase;
   const int __case_offset = __uppercase ? __num_base::_S_oudigits
                                         : __num_base::_S_odigits;
   do
     {
       *--__buf = __lit[(__v & 0xf) + __case_offset];
       __v >>= 4;
     }
   while (__v != 0);
 }
      return __bufend - __buf;
    }



  template<typename _CharT, typename _OutIter>
    void
    num_put<_CharT, _OutIter>::
    _M_group_int(const char* __grouping, size_t __grouping_size, _CharT __sep,
   ios_base&, _CharT* __new, _CharT* __cs, int& __len) const
    {
      _CharT* __p = std::__add_grouping(__new, __sep, __grouping,
     __grouping_size, __cs, __cs + __len);
      __len = __p - __new;
    }

  template<typename _CharT, typename _OutIter>
    template<typename _ValueT>
      _OutIter
      num_put<_CharT, _OutIter>::
      _M_insert_int(_OutIter __s, ios_base& __io, _CharT __fill,
      _ValueT __v) const
      {
 using __gnu_cxx::__add_unsigned;
 typedef typename __add_unsigned<_ValueT>::__type __unsigned_type;
 typedef __numpunct_cache<_CharT> __cache_type;
 __use_cache<__cache_type> __uc;
 const locale& __loc = __io._M_getloc();
 const __cache_type* __lc = __uc(__loc);
 const _CharT* __lit = __lc->_M_atoms_out;
 const ios_base::fmtflags __flags = __io.flags();


 const int __ilen = 5 * sizeof(_ValueT);
 _CharT* __cs = static_cast<_CharT*>(__builtin_alloca(sizeof(_CharT)
            * __ilen));



 const ios_base::fmtflags __basefield = __flags & ios_base::basefield;
 const bool __dec = (__basefield != ios_base::oct
       && __basefield != ios_base::hex);
 const __unsigned_type __u = (__v > 0 || !__dec) ? __v : -__v;
  int __len = __int_to_char(__cs + __ilen, __u, __lit, __flags, __dec);
 __cs += __ilen - __len;


 if (__lc->_M_use_grouping)
   {


     _CharT* __cs2 = static_cast<_CharT*>(__builtin_alloca(sizeof(_CharT)
          * (__len + 1)
          * 2));
     _M_group_int(__lc->_M_grouping, __lc->_M_grouping_size,
    __lc->_M_thousands_sep, __io, __cs2 + 2, __cs, __len);
     __cs = __cs2 + 2;
   }


 if (__builtin_expect(__dec, true))
   {

     if (__v >= 0)
       {
  if (__flags & ios_base::showpos
      && numeric_limits<_ValueT>::is_signed)
    *--__cs = __lit[__num_base::_S_oplus], ++__len;
       }
     else
       *--__cs = __lit[__num_base::_S_ominus], ++__len;
   }
 else if (__flags & ios_base::showbase && __v)
   {
     if (__basefield == ios_base::oct)
       *--__cs = __lit[__num_base::_S_odigits], ++__len;
     else
       {

  const bool __uppercase = __flags & ios_base::uppercase;
  *--__cs = __lit[__num_base::_S_ox + __uppercase];

  *--__cs = __lit[__num_base::_S_odigits];
  __len += 2;
       }
   }


 const streamsize __w = __io.width();
 if (__w > static_cast<streamsize>(__len))
   {
     _CharT* __cs3 = static_cast<_CharT*>(__builtin_alloca(sizeof(_CharT)
          * __w));
     _M_pad(__fill, __w, __io, __cs3, __cs, __len);
     __cs = __cs3;
   }
 __io.width(0);



 return std::__write(__s, __cs, __len);
      }

  template<typename _CharT, typename _OutIter>
    void
    num_put<_CharT, _OutIter>::
    _M_group_float(const char* __grouping, size_t __grouping_size,
     _CharT __sep, const _CharT* __p, _CharT* __new,
     _CharT* __cs, int& __len) const
    {



      const int __declen = __p ? __p - __cs : __len;
      _CharT* __p2 = std::__add_grouping(__new, __sep, __grouping,
      __grouping_size,
      __cs, __cs + __declen);


      int __newlen = __p2 - __new;
      if (__p)
 {
   char_traits<_CharT>::copy(__p2, __p, __len - __declen);
   __newlen += __len - __declen;
 }
      __len = __newlen;
    }
  template<typename _CharT, typename _OutIter>
    template<typename _ValueT>
      _OutIter
      num_put<_CharT, _OutIter>::
      _M_insert_float(_OutIter __s, ios_base& __io, _CharT __fill, char __mod,
         _ValueT __v) const
      {
 typedef __numpunct_cache<_CharT> __cache_type;
 __use_cache<__cache_type> __uc;
 const locale& __loc = __io._M_getloc();
 const __cache_type* __lc = __uc(__loc);


 const streamsize __prec = __io.precision() < 0 ? 6 : __io.precision();

 const int __max_digits = numeric_limits<_ValueT>::digits10;


 int __len;

 char __fbuf[16];
 __num_base::_S_format_float(__io, __fbuf, __mod);
 const bool __fixed = __io.flags() & ios_base::fixed;
 const int __max_exp = numeric_limits<_ValueT>::max_exponent10;







 const int __cs_size = __fixed ? __max_exp + __prec + 4
                               : __max_digits * 2 + __prec;
 char* __cs = static_cast<char*>(__builtin_alloca(__cs_size));
 __len = std::__convert_from_v(_S_get_c_locale(), __cs, 0, __fbuf,
          __prec, __v);




 const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);

 _CharT* __ws = static_cast<_CharT*>(__builtin_alloca(sizeof(_CharT)
            * __len));
 __ctype.widen(__cs, __cs + __len, __ws);


 _CharT* __wp = 0;
 const char* __p = char_traits<char>::find(__cs, __len, '.');
 if (__p)
   {
     __wp = __ws + (__p - __cs);
     *__wp = __lc->_M_decimal_point;
   }




 if (__lc->_M_use_grouping
     && (__wp || __len < 3 || (__cs[1] <= '9' && __cs[2] <= '9'
          && __cs[1] >= '0' && __cs[2] >= '0')))
   {


     _CharT* __ws2 = static_cast<_CharT*>(__builtin_alloca(sizeof(_CharT)
          * __len * 2));

     streamsize __off = 0;
     if (__cs[0] == '-' || __cs[0] == '+')
       {
  __off = 1;
  __ws2[0] = __ws[0];
  __len -= 1;
       }

     _M_group_float(__lc->_M_grouping, __lc->_M_grouping_size,
      __lc->_M_thousands_sep, __wp, __ws2 + __off,
      __ws + __off, __len);
     __len += __off;

     __ws = __ws2;
   }


 const streamsize __w = __io.width();
 if (__w > static_cast<streamsize>(__len))
   {
     _CharT* __ws3 = static_cast<_CharT*>(__builtin_alloca(sizeof(_CharT)
          * __w));
     _M_pad(__fill, __w, __io, __ws3, __ws, __len);
     __ws = __ws3;
   }
 __io.width(0);



 return std::__write(__s, __ws, __len);
      }

  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill, bool __v) const
    {
      const ios_base::fmtflags __flags = __io.flags();
      if ((__flags & ios_base::boolalpha) == 0)
        {
          const long __l = __v;
          __s = _M_insert_int(__s, __io, __fill, __l);
        }
      else
        {
   typedef __numpunct_cache<_CharT> __cache_type;
   __use_cache<__cache_type> __uc;
   const locale& __loc = __io._M_getloc();
   const __cache_type* __lc = __uc(__loc);

   const _CharT* __name = __v ? __lc->_M_truename
                              : __lc->_M_falsename;
   int __len = __v ? __lc->_M_truename_size
                   : __lc->_M_falsename_size;

   const streamsize __w = __io.width();
   if (__w > static_cast<streamsize>(__len))
     {
       _CharT* __cs
  = static_cast<_CharT*>(__builtin_alloca(sizeof(_CharT)
       * __w));
       _M_pad(__fill, __w, __io, __cs, __name, __len);
       __name = __cs;
     }
   __io.width(0);
   __s = std::__write(__s, __name, __len);
 }
      return __s;
    }

  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill, long __v) const
    { return _M_insert_int(__s, __io, __fill, __v); }

  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill,
           unsigned long __v) const
    { return _M_insert_int(__s, __io, __fill, __v); }


  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill, long long __v) const
    { return _M_insert_int(__s, __io, __fill, __v); }

  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill,
           unsigned long long __v) const
    { return _M_insert_int(__s, __io, __fill, __v); }


  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill, double __v) const
    { return _M_insert_float(__s, __io, __fill, char(), __v); }
  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill,
    long double __v) const
    { return _M_insert_float(__s, __io, __fill, 'L', __v); }

  template<typename _CharT, typename _OutIter>
    _OutIter
    num_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type __fill,
           const void* __v) const
    {
      const ios_base::fmtflags __flags = __io.flags();
      const ios_base::fmtflags __fmt = ~(ios_base::basefield
      | ios_base::uppercase
      | ios_base::internal);
      __io.flags(__flags & __fmt | (ios_base::hex | ios_base::showbase));

      __s = _M_insert_int(__s, __io, __fill,
     reinterpret_cast<unsigned long>(__v));
      __io.flags(__flags);
      return __s;
    }

  template<typename _CharT, typename _InIter>
    template<bool _Intl>
      _InIter
      money_get<_CharT, _InIter>::
      _M_extract(iter_type __beg, iter_type __end, ios_base& __io,
   ios_base::iostate& __err, string& __units) const
      {
 typedef char_traits<_CharT> __traits_type;
 typedef typename string_type::size_type size_type;
 typedef money_base::part part;
 typedef __moneypunct_cache<_CharT, _Intl> __cache_type;

 const locale& __loc = __io._M_getloc();
 const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);

 __use_cache<__cache_type> __uc;
 const __cache_type* __lc = __uc(__loc);
 const char_type* __lit = __lc->_M_atoms;


 bool __negative = false;

 size_type __sign_size = 0;

 const bool __mandatory_sign = (__lc->_M_positive_sign_size
           && __lc->_M_negative_sign_size);

 string __grouping_tmp;
 if (__lc->_M_use_grouping)
   __grouping_tmp.reserve(32);

 int __last_pos = 0;

 int __n = 0;

 bool __testvalid = true;

 bool __testdecfound = false;


 string __res;
 __res.reserve(32);

 const char_type* __lit_zero = __lit + money_base::_S_zero;
 const money_base::pattern __p = __lc->_M_neg_format;
 for (int __i = 0; __i < 4 && __testvalid; ++__i)
   {
     const part __which = static_cast<part>(__p.field[__i]);
     switch (__which)
       {
       case money_base::symbol:




  if (__io.flags() & ios_base::showbase || __sign_size > 1
      || __i == 0
      || (__i == 1 && (__mandatory_sign
         || (static_cast<part>(__p.field[0])
      == money_base::sign)
         || (static_cast<part>(__p.field[2])
      == money_base::space)))
      || (__i == 2 && ((static_cast<part>(__p.field[3])
          == money_base::value)
         || __mandatory_sign
         && (static_cast<part>(__p.field[3])
      == money_base::sign))))
    {
      const size_type __len = __lc->_M_curr_symbol_size;
      size_type __j = 0;
      for (; __beg != __end && __j < __len
      && *__beg == __lc->_M_curr_symbol[__j];
    ++__beg, ++__j);
      if (__j != __len
   && (__j || __io.flags() & ios_base::showbase))
        __testvalid = false;
    }
  break;
       case money_base::sign:

  if (__lc->_M_positive_sign_size && __beg != __end
      && *__beg == __lc->_M_positive_sign[0])
    {
      __sign_size = __lc->_M_positive_sign_size;
      ++__beg;
    }
  else if (__lc->_M_negative_sign_size && __beg != __end
    && *__beg == __lc->_M_negative_sign[0])
    {
      __negative = true;
      __sign_size = __lc->_M_negative_sign_size;
      ++__beg;
    }
  else if (__lc->_M_positive_sign_size
    && !__lc->_M_negative_sign_size)


    __negative = true;
  else if (__mandatory_sign)
    __testvalid = false;
  break;
       case money_base::value:


  for (; __beg != __end; ++__beg)
    {
      const char_type __c = *__beg;
      const char_type* __q = __traits_type::find(__lit_zero,
              10, __c);
      if (__q != 0)
        {
   __res += money_base::_S_atoms[__q - __lit];
   ++__n;
        }
      else if (__c == __lc->_M_decimal_point
        && !__testdecfound)
        {
   __last_pos = __n;
   __n = 0;
   __testdecfound = true;
        }
      else if (__lc->_M_use_grouping
        && __c == __lc->_M_thousands_sep
        && !__testdecfound)
        {
   if (__n)
     {

       __grouping_tmp += static_cast<char>(__n);
       __n = 0;
     }
   else
     {
       __testvalid = false;
       break;
     }
        }
      else
        break;
    }
  if (__res.empty())
    __testvalid = false;
  break;
       case money_base::space:

  if (__beg != __end && __ctype.is(ctype_base::space, *__beg))
    ++__beg;
  else
    __testvalid = false;
       case money_base::none:

  if (__i != 3)
    for (; __beg != __end
    && __ctype.is(ctype_base::space, *__beg); ++__beg);
  break;
       }
   }


 if (__sign_size > 1 && __testvalid)
   {
     const char_type* __sign = __negative ? __lc->_M_negative_sign
                                          : __lc->_M_positive_sign;
     size_type __i = 1;
     for (; __beg != __end && __i < __sign_size
     && *__beg == __sign[__i]; ++__beg, ++__i);

     if (__i != __sign_size)
       __testvalid = false;
   }

 if (__testvalid)
   {

     if (__res.size() > 1)
       {
  const size_type __first = __res.find_first_not_of('0');
  const bool __only_zeros = __first == string::npos;
  if (__first)
    __res.erase(0, __only_zeros ? __res.size() - 1 : __first);
       }


     if (__negative && __res[0] != '0')
       __res.insert(__res.begin(), '-');


     if (__grouping_tmp.size())
       {

  __grouping_tmp += static_cast<char>(__testdecfound ? __last_pos
                         : __n);
  if (!std::__verify_grouping(__lc->_M_grouping,
         __lc->_M_grouping_size,
         __grouping_tmp))
    __err |= ios_base::failbit;
       }


     if (__testdecfound && __lc->_M_frac_digits > 0
  && __n != __lc->_M_frac_digits)
       __testvalid = false;
   }


 if (!__testvalid)
   __err |= ios_base::failbit;
 else
   __units.swap(__res);


 if (__beg == __end)
   __err |= ios_base::eofbit;
 return __beg;
      }
  template<typename _CharT, typename _InIter>
    _InIter
    money_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, bool __intl, ios_base& __io,
    ios_base::iostate& __err, long double& __units) const
    {
      string __str;
      __beg = __intl ? _M_extract<true>(__beg, __end, __io, __err, __str)
              : _M_extract<false>(__beg, __end, __io, __err, __str);
      std::__convert_to_v(__str.c_str(), __units, __err, _S_get_c_locale());
      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    money_get<_CharT, _InIter>::
    do_get(iter_type __beg, iter_type __end, bool __intl, ios_base& __io,
    ios_base::iostate& __err, string_type& __digits) const
    {
      typedef typename string::size_type size_type;

      const locale& __loc = __io._M_getloc();
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);

      string __str;
      __beg = __intl ? _M_extract<true>(__beg, __end, __io, __err, __str)
              : _M_extract<false>(__beg, __end, __io, __err, __str);
      const size_type __len = __str.size();
      if (__len)
 {
   __digits.resize(__len);
   __ctype.widen(__str.data(), __str.data() + __len, &__digits[0]);
 }
      return __beg;
    }

  template<typename _CharT, typename _OutIter>
    template<bool _Intl>
      _OutIter
      money_put<_CharT, _OutIter>::
      _M_insert(iter_type __s, ios_base& __io, char_type __fill,
  const string_type& __digits) const
      {
 typedef typename string_type::size_type size_type;
 typedef money_base::part part;
 typedef __moneypunct_cache<_CharT, _Intl> __cache_type;

 const locale& __loc = __io._M_getloc();
 const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);

 __use_cache<__cache_type> __uc;
 const __cache_type* __lc = __uc(__loc);
 const char_type* __lit = __lc->_M_atoms;



 const char_type* __beg = __digits.data();

 money_base::pattern __p;
 const char_type* __sign;
 size_type __sign_size;
 if (!(*__beg == __lit[money_base::_S_minus]))
   {
     __p = __lc->_M_pos_format;
     __sign = __lc->_M_positive_sign;
     __sign_size = __lc->_M_positive_sign_size;
   }
 else
   {
     __p = __lc->_M_neg_format;
     __sign = __lc->_M_negative_sign;
     __sign_size = __lc->_M_negative_sign_size;
     if (__digits.size())
       ++__beg;
   }


 size_type __len = __ctype.scan_not(ctype_base::digit, __beg,
        __beg + __digits.size()) - __beg;
 if (__len)
   {



     string_type __value;
     __value.reserve(2 * __len);



     long __paddec = __len - __lc->_M_frac_digits;
     if (__paddec > 0)
         {
  if (__lc->_M_frac_digits < 0)
    __paddec = __len;
    if (__lc->_M_grouping_size)
      {
      __value.assign(2 * __paddec, char_type());
       _CharT* __vend =
        std::__add_grouping(&__value[0], __lc->_M_thousands_sep,
       __lc->_M_grouping,
       __lc->_M_grouping_size,
       __beg, __beg + __paddec);
      __value.erase(__vend - &__value[0]);
      }
    else
    __value.assign(__beg, __paddec);
       }


     if (__lc->_M_frac_digits > 0)
       {
  __value += __lc->_M_decimal_point;
  if (__paddec >= 0)
    __value.append(__beg + __paddec, __lc->_M_frac_digits);
  else
    {

      __value.append(-__paddec, __lit[money_base::_S_zero]);
      __value.append(__beg, __len);
    }
         }


     const ios_base::fmtflags __f = __io.flags()
                                    & ios_base::adjustfield;
     __len = __value.size() + __sign_size;
     __len += ((__io.flags() & ios_base::showbase)
        ? __lc->_M_curr_symbol_size : 0);

     string_type __res;
     __res.reserve(2 * __len);

     const size_type __width = static_cast<size_type>(__io.width());
     const bool __testipad = (__f == ios_base::internal
         && __len < __width);

     for (int __i = 0; __i < 4; ++__i)
       {
  const part __which = static_cast<part>(__p.field[__i]);
  switch (__which)
    {
    case money_base::symbol:
      if (__io.flags() & ios_base::showbase)
        __res.append(__lc->_M_curr_symbol,
       __lc->_M_curr_symbol_size);
      break;
    case money_base::sign:



      if (__sign_size)
        __res += __sign[0];
      break;
    case money_base::value:
      __res += __value;
      break;
    case money_base::space:



      if (__testipad)
        __res.append(__width - __len, __fill);
      else
        __res += __fill;
      break;
    case money_base::none:
      if (__testipad)
        __res.append(__width - __len, __fill);
      break;
    }
       }


     if (__sign_size > 1)
       __res.append(__sign + 1, __sign_size - 1);


     __len = __res.size();
     if (__width > __len)
       {
  if (__f == ios_base::left)

    __res.append(__width - __len, __fill);
  else

    __res.insert(0, __width - __len, __fill);
  __len = __width;
       }


     __s = std::__write(__s, __res.data(), __len);
   }
 __io.width(0);
 return __s;
      }
  template<typename _CharT, typename _OutIter>
    _OutIter
    money_put<_CharT, _OutIter>::
    do_put(iter_type __s, bool __intl, ios_base& __io, char_type __fill,
    long double __units) const
    {
      const locale __loc = __io.getloc();
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);
      const int __cs_size = numeric_limits<long double>::max_exponent10 + 3;
      char* __cs = static_cast<char*>(__builtin_alloca(__cs_size));
      int __len = std::__convert_from_v(_S_get_c_locale(), __cs, 0, "%.*Lf",
     0, __units);

      string_type __digits(__len, char_type());
      __ctype.widen(__cs, __cs + __len, &__digits[0]);
      return __intl ? _M_insert<true>(__s, __io, __fill, __digits)
             : _M_insert<false>(__s, __io, __fill, __digits);
    }

  template<typename _CharT, typename _OutIter>
    _OutIter
    money_put<_CharT, _OutIter>::
    do_put(iter_type __s, bool __intl, ios_base& __io, char_type __fill,
    const string_type& __digits) const
    { return __intl ? _M_insert<true>(__s, __io, __fill, __digits)
             : _M_insert<false>(__s, __io, __fill, __digits); }






  template<typename _CharT, typename _InIter>
    time_base::dateorder
    time_get<_CharT, _InIter>::do_date_order() const
    { return time_base::no_order; }



  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    _M_extract_via_format(iter_type __beg, iter_type __end, ios_base& __io,
     ios_base::iostate& __err, tm* __tm,
     const _CharT* __format) const
    {
      const locale& __loc = __io._M_getloc();
      const __timepunct<_CharT>& __tp = use_facet<__timepunct<_CharT> >(__loc);
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);
      const size_t __len = char_traits<_CharT>::length(__format);

      ios_base::iostate __tmperr = ios_base::goodbit;
      for (size_t __i = 0; __beg != __end && __i < __len && !__tmperr; ++__i)
 {
   if (__ctype.narrow(__format[__i], 0) == '%')
     {

       char __c = __ctype.narrow(__format[++__i], 0);
       int __mem = 0;
       if (__c == 'E' || __c == 'O')
  __c = __ctype.narrow(__format[++__i], 0);
       switch (__c)
  {
    const char* __cs;
    _CharT __wcs[10];
  case 'a':

    const char_type* __days1[7];
    __tp._M_days_abbreviated(__days1);
    __beg = _M_extract_name(__beg, __end, __tm->tm_wday, __days1,
       7, __io, __tmperr);
    break;
  case 'A':

    const char_type* __days2[7];
    __tp._M_days(__days2);
    __beg = _M_extract_name(__beg, __end, __tm->tm_wday, __days2,
       7, __io, __tmperr);
    break;
  case 'h':
  case 'b':

    const char_type* __months1[12];
    __tp._M_months_abbreviated(__months1);
    __beg = _M_extract_name(__beg, __end, __tm->tm_mon,
       __months1, 12, __io, __tmperr);
    break;
  case 'B':

    const char_type* __months2[12];
    __tp._M_months(__months2);
    __beg = _M_extract_name(__beg, __end, __tm->tm_mon,
       __months2, 12, __io, __tmperr);
    break;
  case 'c':

    const char_type* __dt[2];
    __tp._M_date_time_formats(__dt);
    __beg = _M_extract_via_format(__beg, __end, __io, __tmperr,
      __tm, __dt[0]);
    break;
  case 'd':

    __beg = _M_extract_num(__beg, __end, __tm->tm_mday, 1, 31, 2,
      __io, __tmperr);
    break;
  case 'e':


    if (__ctype.is(ctype_base::space, *__beg))
      __beg = _M_extract_num(++__beg, __end, __tm->tm_mday, 1, 9,
        1, __io, __tmperr);
    else
      __beg = _M_extract_num(__beg, __end, __tm->tm_mday, 10, 31,
        2, __io, __tmperr);
    break;
  case 'D':

    __cs = "%m/%d/%y";
    __ctype.widen(__cs, __cs + 9, __wcs);
    __beg = _M_extract_via_format(__beg, __end, __io, __tmperr,
      __tm, __wcs);
    break;
  case 'H':

    __beg = _M_extract_num(__beg, __end, __tm->tm_hour, 0, 23, 2,
      __io, __tmperr);
    break;
  case 'I':

    __beg = _M_extract_num(__beg, __end, __tm->tm_hour, 1, 12, 2,
      __io, __tmperr);
    break;
  case 'm':

    __beg = _M_extract_num(__beg, __end, __mem, 1, 12, 2,
      __io, __tmperr);
    if (!__tmperr)
      __tm->tm_mon = __mem - 1;
    break;
  case 'M':

    __beg = _M_extract_num(__beg, __end, __tm->tm_min, 0, 59, 2,
      __io, __tmperr);
    break;
  case 'n':
    if (__ctype.narrow(*__beg, 0) == '\n')
      ++__beg;
    else
      __tmperr |= ios_base::failbit;
    break;
  case 'R':

    __cs = "%H:%M";
    __ctype.widen(__cs, __cs + 6, __wcs);
    __beg = _M_extract_via_format(__beg, __end, __io, __tmperr,
      __tm, __wcs);
    break;
  case 'S':





    __beg = _M_extract_num(__beg, __end, __tm->tm_sec, 0, 61, 2,

      __io, __tmperr);
    break;
  case 't':
    if (__ctype.narrow(*__beg, 0) == '\t')
      ++__beg;
    else
      __tmperr |= ios_base::failbit;
    break;
  case 'T':

    __cs = "%H:%M:%S";
    __ctype.widen(__cs, __cs + 9, __wcs);
    __beg = _M_extract_via_format(__beg, __end, __io, __tmperr,
      __tm, __wcs);
    break;
  case 'x':

    const char_type* __dates[2];
    __tp._M_date_formats(__dates);
    __beg = _M_extract_via_format(__beg, __end, __io, __tmperr,
      __tm, __dates[0]);
    break;
  case 'X':

    const char_type* __times[2];
    __tp._M_time_formats(__times);
    __beg = _M_extract_via_format(__beg, __end, __io, __tmperr,
      __tm, __times[0]);
    break;
  case 'y':
  case 'C':

    __beg = _M_extract_num(__beg, __end, __tm->tm_year, 0, 99, 2,
      __io, __tmperr);
    break;
  case 'Y':

    __beg = _M_extract_num(__beg, __end, __mem, 0, 9999, 4,
      __io, __tmperr);
    if (!__tmperr)
      __tm->tm_year = __mem - 1900;
    break;
  case 'Z':

    if (__ctype.is(ctype_base::upper, *__beg))
      {
        int __tmp;
        __beg = _M_extract_name(__beg, __end, __tmp,
           __timepunct_cache<_CharT>::_S_timezones,
           14, __io, __tmperr);


        if (__beg != __end && !__tmperr && __tmp == 0
     && (*__beg == __ctype.widen('-')
         || *__beg == __ctype.widen('+')))
   {
     __beg = _M_extract_num(__beg, __end, __tmp, 0, 23, 2,
       __io, __tmperr);
     __beg = _M_extract_num(__beg, __end, __tmp, 0, 59, 2,
       __io, __tmperr);
   }
      }
    else
      __tmperr |= ios_base::failbit;
    break;
  default:

    __tmperr |= ios_base::failbit;
  }
     }
   else
     {

       if (__format[__i] == *__beg)
  ++__beg;
       else
  __tmperr |= ios_base::failbit;
     }
 }

      if (__tmperr)
 __err |= ios_base::failbit;

      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    _M_extract_num(iter_type __beg, iter_type __end, int& __member,
     int __min, int __max, size_t __len,
     ios_base& __io, ios_base::iostate& __err) const
    {
      const locale& __loc = __io._M_getloc();
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);


      int __mult = __len == 2 ? 10 : (__len == 4 ? 1000 : 1);

      ++__min;
      size_t __i = 0;
      int __value = 0;
      for (; __beg != __end && __i < __len; ++__beg, ++__i)
 {
   const char __c = __ctype.narrow(*__beg, '*');
   if (__c >= '0' && __c <= '9')
     {
       __value = __value * 10 + (__c - '0');
       const int __valuec = __value * __mult;
       if (__valuec > __max || __valuec + __mult < __min)
  break;
       __mult /= 10;
     }
   else
     break;
 }
      if (__i == __len)
 __member = __value;
      else
 __err |= ios_base::failbit;

      return __beg;
    }



  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    _M_extract_name(iter_type __beg, iter_type __end, int& __member,
      const _CharT** __names, size_t __indexlen,
      ios_base& __io, ios_base::iostate& __err) const
    {
      typedef char_traits<_CharT> __traits_type;
      const locale& __loc = __io._M_getloc();
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);

      int* __matches = static_cast<int*>(__builtin_alloca(sizeof(int)
         * __indexlen));
      size_t __nmatches = 0;
      size_t __pos = 0;
      bool __testvalid = true;
      const char_type* __name;





      if (__beg != __end)
 {
   const char_type __c = *__beg;
   for (size_t __i1 = 0; __i1 < __indexlen; ++__i1)
     if (__c == __names[__i1][0]
  || __c == __ctype.toupper(__names[__i1][0]))
       __matches[__nmatches++] = __i1;
 }

      while (__nmatches > 1)
 {

   size_t __minlen = __traits_type::length(__names[__matches[0]]);
   for (size_t __i2 = 1; __i2 < __nmatches; ++__i2)
     __minlen = std::min(__minlen,
         __traits_type::length(__names[__matches[__i2]]));
   ++__beg, ++__pos;
   if (__pos < __minlen && __beg != __end)
     for (size_t __i3 = 0; __i3 < __nmatches;)
       {
  __name = __names[__matches[__i3]];
  if (!(__name[__pos] == *__beg))
    __matches[__i3] = __matches[--__nmatches];
  else
    ++__i3;
       }
   else
     break;
 }

      if (__nmatches == 1)
 {

   ++__beg, ++__pos;
   __name = __names[__matches[0]];
   const size_t __len = __traits_type::length(__name);
   while (__pos < __len && __beg != __end && __name[__pos] == *__beg)
     ++__beg, ++__pos;

   if (__len == __pos)
     __member = __matches[0];
   else
     __testvalid = false;
 }
      else
 __testvalid = false;
      if (!__testvalid)
 __err |= ios_base::failbit;

      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    do_get_time(iter_type __beg, iter_type __end, ios_base& __io,
  ios_base::iostate& __err, tm* __tm) const
    {
      const locale& __loc = __io._M_getloc();
      const __timepunct<_CharT>& __tp = use_facet<__timepunct<_CharT> >(__loc);
      const char_type* __times[2];
      __tp._M_time_formats(__times);
      __beg = _M_extract_via_format(__beg, __end, __io, __err,
        __tm, __times[0]);
      if (__beg == __end)
 __err |= ios_base::eofbit;
      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    do_get_date(iter_type __beg, iter_type __end, ios_base& __io,
  ios_base::iostate& __err, tm* __tm) const
    {
      const locale& __loc = __io._M_getloc();
      const __timepunct<_CharT>& __tp = use_facet<__timepunct<_CharT> >(__loc);
      const char_type* __dates[2];
      __tp._M_date_formats(__dates);
      __beg = _M_extract_via_format(__beg, __end, __io, __err,
        __tm, __dates[0]);
      if (__beg == __end)
 __err |= ios_base::eofbit;
      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    do_get_weekday(iter_type __beg, iter_type __end, ios_base& __io,
     ios_base::iostate& __err, tm* __tm) const
    {
      typedef char_traits<_CharT> __traits_type;
      const locale& __loc = __io._M_getloc();
      const __timepunct<_CharT>& __tp = use_facet<__timepunct<_CharT> >(__loc);
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);
      const char_type* __days[7];
      __tp._M_days_abbreviated(__days);
      int __tmpwday;
      ios_base::iostate __tmperr = ios_base::goodbit;
      __beg = _M_extract_name(__beg, __end, __tmpwday, __days, 7,
         __io, __tmperr);







      if (!__tmperr && __beg != __end)
 {
   size_t __pos = __traits_type::length(__days[__tmpwday]);
   __tp._M_days(__days);
   const char_type* __name = __days[__tmpwday];
   if (__name[__pos] == *__beg)
     {

       const size_t __len = __traits_type::length(__name);
       while (__pos < __len && __beg != __end
       && __name[__pos] == *__beg)
  ++__beg, ++__pos;
       if (__len != __pos)
  __tmperr |= ios_base::failbit;
     }
 }
      if (!__tmperr)
 __tm->tm_wday = __tmpwday;
      else
 __err |= ios_base::failbit;

      if (__beg == __end)
 __err |= ios_base::eofbit;
      return __beg;
     }

  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    do_get_monthname(iter_type __beg, iter_type __end,
                     ios_base& __io, ios_base::iostate& __err, tm* __tm) const
    {
      typedef char_traits<_CharT> __traits_type;
      const locale& __loc = __io._M_getloc();
      const __timepunct<_CharT>& __tp = use_facet<__timepunct<_CharT> >(__loc);
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);
      const char_type* __months[12];
      __tp._M_months_abbreviated(__months);
      int __tmpmon;
      ios_base::iostate __tmperr = ios_base::goodbit;
      __beg = _M_extract_name(__beg, __end, __tmpmon, __months, 12,
         __io, __tmperr);







      if (!__tmperr && __beg != __end)
 {
   size_t __pos = __traits_type::length(__months[__tmpmon]);
   __tp._M_months(__months);
   const char_type* __name = __months[__tmpmon];
   if (__name[__pos] == *__beg)
     {

       const size_t __len = __traits_type::length(__name);
       while (__pos < __len && __beg != __end
       && __name[__pos] == *__beg)
  ++__beg, ++__pos;
       if (__len != __pos)
  __tmperr |= ios_base::failbit;
     }
 }
      if (!__tmperr)
 __tm->tm_mon = __tmpmon;
      else
 __err |= ios_base::failbit;

      if (__beg == __end)
 __err |= ios_base::eofbit;
      return __beg;
    }

  template<typename _CharT, typename _InIter>
    _InIter
    time_get<_CharT, _InIter>::
    do_get_year(iter_type __beg, iter_type __end, ios_base& __io,
  ios_base::iostate& __err, tm* __tm) const
    {
      const locale& __loc = __io._M_getloc();
      const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);

      size_t __i = 0;
      int __value = 0;
      for (; __beg != __end && __i < 4; ++__beg, ++__i)
 {
   const char __c = __ctype.narrow(*__beg, '*');
   if (__c >= '0' && __c <= '9')
     __value = __value * 10 + (__c - '0');
   else
     break;
 }
      if (__i == 2 || __i == 4)
 __tm->tm_year = __i == 2 ? __value : __value - 1900;
      else
 __err |= ios_base::failbit;

      if (__beg == __end)
 __err |= ios_base::eofbit;
      return __beg;
    }

  template<typename _CharT, typename _OutIter>
    _OutIter
    time_put<_CharT, _OutIter>::
    put(iter_type __s, ios_base& __io, char_type __fill, const tm* __tm,
 const _CharT* __beg, const _CharT* __end) const
    {
      const locale& __loc = __io._M_getloc();
      ctype<_CharT> const& __ctype = use_facet<ctype<_CharT> >(__loc);
      for (; __beg != __end; ++__beg)
 if (__ctype.narrow(*__beg, 0) != '%')
   {
     *__s = *__beg;
     ++__s;
   }
 else if (++__beg != __end)
   {
     char __format;
     char __mod = 0;
     const char __c = __ctype.narrow(*__beg, 0);
     if (__c != 'E' && __c != 'O')
       __format = __c;
     else if (++__beg != __end)
       {
  __mod = __c;
  __format = __ctype.narrow(*__beg, 0);
       }
     else
       break;
     __s = this->do_put(__s, __io, __fill, __tm, __format, __mod);
   }
 else
   break;
      return __s;
    }

  template<typename _CharT, typename _OutIter>
    _OutIter
    time_put<_CharT, _OutIter>::
    do_put(iter_type __s, ios_base& __io, char_type, const tm* __tm,
    char __format, char __mod) const
    {
      const locale& __loc = __io._M_getloc();
      ctype<_CharT> const& __ctype = use_facet<ctype<_CharT> >(__loc);
      __timepunct<_CharT> const& __tp = use_facet<__timepunct<_CharT> >(__loc);



      const size_t __maxlen = 128;
      char_type* __res =
       static_cast<char_type*>(__builtin_alloca(sizeof(char_type) * __maxlen));






      char_type __fmt[4];
      __fmt[0] = __ctype.widen('%');
      if (!__mod)
 {
   __fmt[1] = __format;
   __fmt[2] = char_type();
 }
      else
 {
   __fmt[1] = __mod;
   __fmt[2] = __format;
   __fmt[3] = char_type();
 }

      __tp._M_put(__res, __maxlen, __fmt, __tm);


      return std::__write(__s, __res, char_traits<char_type>::length(__res));
    }


  template<typename _CharT>
    int
    collate<_CharT>::_M_compare(const _CharT*, const _CharT*) const
    { return 0; }


  template<typename _CharT>
    size_t
    collate<_CharT>::_M_transform(_CharT*, const _CharT*, size_t) const
    { return 0; }

  template<typename _CharT>
    int
    collate<_CharT>::
    do_compare(const _CharT* __lo1, const _CharT* __hi1,
        const _CharT* __lo2, const _CharT* __hi2) const
    {


      const string_type __one(__lo1, __hi1);
      const string_type __two(__lo2, __hi2);

      const _CharT* __p = __one.c_str();
      const _CharT* __pend = __one.data() + __one.length();
      const _CharT* __q = __two.c_str();
      const _CharT* __qend = __two.data() + __two.length();




      for (;;)
 {
   const int __res = _M_compare(__p, __q);
   if (__res)
     return __res;

   __p += char_traits<_CharT>::length(__p);
   __q += char_traits<_CharT>::length(__q);
   if (__p == __pend && __q == __qend)
     return 0;
   else if (__p == __pend)
     return -1;
   else if (__q == __qend)
     return 1;

   __p++;
   __q++;
 }
    }

  template<typename _CharT>
    typename collate<_CharT>::string_type
    collate<_CharT>::
    do_transform(const _CharT* __lo, const _CharT* __hi) const
    {
      string_type __ret;


      const string_type __str(__lo, __hi);

      const _CharT* __p = __str.c_str();
      const _CharT* __pend = __str.data() + __str.length();

      size_t __len = (__hi - __lo) * 2;

      _CharT* __c = new _CharT[__len];

      if (true)
 {



   for (;;)
     {

       size_t __res = _M_transform(__c, __p, __len);


       if (__res >= __len)
  {
    __len = __res + 1;
    delete [] __c, __c = 0;
    __c = new _CharT[__len];
    __res = _M_transform(__c, __p, __len);
  }

       __ret.append(__c, __res);
       __p += char_traits<_CharT>::length(__p);
       if (__p == __pend)
  break;

       __p++;
       __ret.push_back(_CharT());
     }
 }
      if (false)
 {
   delete [] __c;
                          ;
 }

      delete [] __c;

      return __ret;
    }

  template<typename _CharT>
    long
    collate<_CharT>::
    do_hash(const _CharT* __lo, const _CharT* __hi) const
    {
      unsigned long __val = 0;
      for (; __lo < __hi; ++__lo)
 __val = *__lo + ((__val << 7) |
         (__val >> (numeric_limits<unsigned long>::digits - 7)));
      return static_cast<long>(__val);
    }
  template<typename _CharT, typename _Traits>
    void
    __pad<_CharT, _Traits>::_S_pad(ios_base& __io, _CharT __fill,
       _CharT* __news, const _CharT* __olds,
       const streamsize __newlen,
       const streamsize __oldlen, const bool __num)
    {
      const size_t __plen = static_cast<size_t>(__newlen - __oldlen);
      const ios_base::fmtflags __adjust = __io.flags() & ios_base::adjustfield;


      if (__adjust == ios_base::left)
 {
   _Traits::copy(__news, const_cast<_CharT*>(__olds), __oldlen);
   _Traits::assign(__news + __oldlen, __plen, __fill);
   return;
 }

      size_t __mod = 0;
      if (__adjust == ios_base::internal && __num)
 {



          const locale& __loc = __io._M_getloc();
   const ctype<_CharT>& __ctype = use_facet<ctype<_CharT> >(__loc);

   const bool __testsign = (__ctype.widen('-') == __olds[0]
       || __ctype.widen('+') == __olds[0]);
   const bool __testhex = (__ctype.widen('0') == __olds[0]
      && __oldlen > 1
      && (__ctype.widen('x') == __olds[1]
          || __ctype.widen('X') == __olds[1]));
   if (__testhex)
     {
       __news[0] = __olds[0];
       __news[1] = __olds[1];
       __mod = 2;
       __news += 2;
     }
   else if (__testsign)
     {
       __news[0] = __olds[0];
       __mod = 1;
       ++__news;
     }

 }
      _Traits::assign(__news, __plen, __fill);
      _Traits::copy(__news + __plen, const_cast<_CharT*>(__olds + __mod),
      __oldlen - __mod);
    }

  bool
  __verify_grouping(const char* __grouping, size_t __grouping_size,
      const string& __grouping_tmp)
  {
    const size_t __n = __grouping_tmp.size() - 1;
    const size_t __min = std::min(__n, size_t(__grouping_size - 1));
    size_t __i = __n;
    bool __test = true;




    for (size_t __j = 0; __j < __min && __test; --__i, ++__j)
      __test = __grouping_tmp[__i] == __grouping[__j];
    for (; __i && __test; --__i)
      __test = __grouping_tmp[__i] == __grouping[__min];



    if (static_cast<signed char>(__grouping[__min]) > 0)
      __test &= __grouping_tmp[0] <= __grouping[__min];
    return __test;
  }

  template<typename _CharT>
    _CharT*
    __add_grouping(_CharT* __s, _CharT __sep,
     const char* __gbeg, size_t __gsize,
     const _CharT* __first, const _CharT* __last)
    {
      size_t __idx = 0;
      size_t __ctr = 0;

      while (__last - __first > __gbeg[__idx]
      && static_cast<signed char>(__gbeg[__idx]) > 0)
 {
   __last -= __gbeg[__idx];
   __idx < __gsize - 1 ? ++__idx : ++__ctr;
 }

      while (__first != __last)
 *__s++ = *__first++;

      while (__ctr--)
 {
   *__s++ = __sep;
   for (char __i = __gbeg[__idx]; __i > 0; --__i)
     *__s++ = *__first++;
 }

      while (__idx--)
 {
   *__s++ = __sep;
   for (char __i = __gbeg[__idx]; __i > 0; --__i)
     *__s++ = *__first++;
 }

      return __s;
    }





  extern template class moneypunct<char, false>;
  extern template class moneypunct<char, true>;
  extern template class moneypunct_byname<char, false>;
  extern template class moneypunct_byname<char, true>;
  extern template class money_get<char>;
  extern template class money_put<char>;
  extern template class numpunct<char>;
  extern template class numpunct_byname<char>;
  extern template class num_get<char>;
  extern template class num_put<char>;
  extern template class __timepunct<char>;
  extern template class time_put<char>;
  extern template class time_put_byname<char>;
  extern template class time_get<char>;
  extern template class time_get_byname<char>;
  extern template class messages<char>;
  extern template class messages_byname<char>;
  extern template class ctype_byname<char>;
  extern template class codecvt_byname<char, char, mbstate_t>;
  extern template class collate<char>;
  extern template class collate_byname<char>;

  extern template
    const codecvt<char, char, mbstate_t>&
    use_facet<codecvt<char, char, mbstate_t> >(const locale&);

  extern template
    const collate<char>&
    use_facet<collate<char> >(const locale&);

  extern template
    const numpunct<char>&
    use_facet<numpunct<char> >(const locale&);

  extern template
    const num_put<char>&
    use_facet<num_put<char> >(const locale&);

  extern template
    const num_get<char>&
    use_facet<num_get<char> >(const locale&);

  extern template
    const moneypunct<char, true>&
    use_facet<moneypunct<char, true> >(const locale&);

  extern template
    const moneypunct<char, false>&
    use_facet<moneypunct<char, false> >(const locale&);

  extern template
    const money_put<char>&
    use_facet<money_put<char> >(const locale&);

  extern template
    const money_get<char>&
    use_facet<money_get<char> >(const locale&);

  extern template
    const __timepunct<char>&
    use_facet<__timepunct<char> >(const locale&);

  extern template
    const time_put<char>&
    use_facet<time_put<char> >(const locale&);

  extern template
    const time_get<char>&
    use_facet<time_get<char> >(const locale&);

  extern template
    const messages<char>&
    use_facet<messages<char> >(const locale&);

  extern template
    bool
    has_facet<ctype<char> >(const locale&);

  extern template
    bool
    has_facet<codecvt<char, char, mbstate_t> >(const locale&);

  extern template
    bool
    has_facet<collate<char> >(const locale&);

  extern template
    bool
    has_facet<numpunct<char> >(const locale&);

  extern template
    bool
    has_facet<num_put<char> >(const locale&);

  extern template
    bool
    has_facet<num_get<char> >(const locale&);

  extern template
    bool
    has_facet<moneypunct<char> >(const locale&);

  extern template
    bool
    has_facet<money_put<char> >(const locale&);

  extern template
    bool
    has_facet<money_get<char> >(const locale&);

  extern template
    bool
    has_facet<__timepunct<char> >(const locale&);

  extern template
    bool
    has_facet<time_put<char> >(const locale&);

  extern template
    bool
    has_facet<time_get<char> >(const locale&);

  extern template
    bool
    has_facet<messages<char> >(const locale&);


  extern template class moneypunct<wchar_t, false>;
  extern template class moneypunct<wchar_t, true>;
  extern template class moneypunct_byname<wchar_t, false>;
  extern template class moneypunct_byname<wchar_t, true>;
  extern template class money_get<wchar_t>;
  extern template class money_put<wchar_t>;
  extern template class numpunct<wchar_t>;
  extern template class numpunct_byname<wchar_t>;
  extern template class num_get<wchar_t>;
  extern template class num_put<wchar_t>;
  extern template class __timepunct<wchar_t>;
  extern template class time_put<wchar_t>;
  extern template class time_put_byname<wchar_t>;
  extern template class time_get<wchar_t>;
  extern template class time_get_byname<wchar_t>;
  extern template class messages<wchar_t>;
  extern template class messages_byname<wchar_t>;
  extern template class ctype_byname<wchar_t>;
  extern template class codecvt_byname<wchar_t, char, mbstate_t>;
  extern template class collate<wchar_t>;
  extern template class collate_byname<wchar_t>;

  extern template
    const codecvt<wchar_t, char, mbstate_t>&
    use_facet<codecvt<wchar_t, char, mbstate_t> >(locale const&);

  extern template
    const collate<wchar_t>&
    use_facet<collate<wchar_t> >(const locale&);

  extern template
    const numpunct<wchar_t>&
    use_facet<numpunct<wchar_t> >(const locale&);

  extern template
    const num_put<wchar_t>&
    use_facet<num_put<wchar_t> >(const locale&);

  extern template
    const num_get<wchar_t>&
    use_facet<num_get<wchar_t> >(const locale&);

  extern template
    const moneypunct<wchar_t, true>&
    use_facet<moneypunct<wchar_t, true> >(const locale&);

  extern template
    const moneypunct<wchar_t, false>&
    use_facet<moneypunct<wchar_t, false> >(const locale&);

  extern template
    const money_put<wchar_t>&
    use_facet<money_put<wchar_t> >(const locale&);

  extern template
    const money_get<wchar_t>&
    use_facet<money_get<wchar_t> >(const locale&);

  extern template
    const __timepunct<wchar_t>&
    use_facet<__timepunct<wchar_t> >(const locale&);

  extern template
    const time_put<wchar_t>&
    use_facet<time_put<wchar_t> >(const locale&);

  extern template
    const time_get<wchar_t>&
    use_facet<time_get<wchar_t> >(const locale&);

  extern template
    const messages<wchar_t>&
    use_facet<messages<wchar_t> >(const locale&);

 extern template
    bool
    has_facet<ctype<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<codecvt<wchar_t, char, mbstate_t> >(const locale&);

  extern template
    bool
    has_facet<collate<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<numpunct<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<num_put<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<num_get<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<moneypunct<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<money_put<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<money_get<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<__timepunct<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<time_put<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<time_get<wchar_t> >(const locale&);

  extern template
    bool
    has_facet<messages<wchar_t> >(const locale&);



}

namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>::sentry::
    sentry(basic_ostream<_CharT, _Traits>& __os)
    : _M_ok(false), _M_os(__os)
    {

      if (__os.tie() && __os.good())
 __os.tie()->flush();

      if (__os.good())
 _M_ok = true;
      else
 __os.setstate(ios_base::failbit);
    }

  template<typename _CharT, typename _Traits>
    template<typename _ValueT>
      basic_ostream<_CharT, _Traits>&
      basic_ostream<_CharT, _Traits>::
      _M_insert(_ValueT __v)
      {
 sentry __cerb(*this);
 if (__cerb)
   {
     ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
     if (true)
       {
  const __num_put_type& __np = __check_facet(this->_M_num_put);
  if (__np.put(*this, *this, this->fill(), __v).failed())
    __err |= ios_base::badbit;
       }
     if (false)
       { this->_M_setstate(ios_base::badbit); }
     if (__err)
       this->setstate(__err);
   }
 return *this;
      }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    operator<<(short __n)
    {


      const ios_base::fmtflags __fmt = this->flags() & ios_base::basefield;
      if (__fmt == ios_base::oct || __fmt == ios_base::hex)
 return _M_insert(static_cast<long>(static_cast<unsigned short>(__n)));
      else
 return _M_insert(static_cast<long>(__n));
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    operator<<(int __n)
    {


      const ios_base::fmtflags __fmt = this->flags() & ios_base::basefield;
      if (__fmt == ios_base::oct || __fmt == ios_base::hex)
 return _M_insert(static_cast<long>(static_cast<unsigned int>(__n)));
      else
 return _M_insert(static_cast<long>(__n));
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    operator<<(__streambuf_type* __sbin)
    {
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      sentry __cerb(*this);
      if (__cerb && __sbin)
 {
   if (true)
     {
       if (!__copy_streambufs(__sbin, this->rdbuf()))
  __err |= ios_base::failbit;
     }
   if (false)
     { this->_M_setstate(ios_base::failbit); }
 }
      else if (!__sbin)
 __err |= ios_base::badbit;
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    put(char_type __c)
    {






      sentry __cerb(*this);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       const int_type __put = this->rdbuf()->sputc(__c);
       if (traits_type::eq_int_type(__put, traits_type::eof()))
  __err |= ios_base::badbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    write(const _CharT* __s, streamsize __n)
    {







      sentry __cerb(*this);
      if (__cerb)
 {
   if (true)
     { _M_write(__s, __n); }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    flush()
    {



      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      if (true)
 {
   if (this->rdbuf() && this->rdbuf()->pubsync() == -1)
     __err |= ios_base::badbit;
 }
      if (false)
 { this->_M_setstate(ios_base::badbit); }
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    typename basic_ostream<_CharT, _Traits>::pos_type
    basic_ostream<_CharT, _Traits>::
    tellp()
    {
      pos_type __ret = pos_type(-1);
      if (true)
 {
   if (!this->fail())
     __ret = this->rdbuf()->pubseekoff(0, ios_base::cur, ios_base::out);
 }
      if (false)
 { this->_M_setstate(ios_base::badbit); }
      return __ret;
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    seekp(pos_type __pos)
    {
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      if (true)
 {
   if (!this->fail())
     {


       const pos_type __p = this->rdbuf()->pubseekpos(__pos,
            ios_base::out);


       if (__p == pos_type(off_type(-1)))
  __err |= ios_base::failbit;
     }
 }
      if (false)
 { this->_M_setstate(ios_base::badbit); }
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    basic_ostream<_CharT, _Traits>::
    seekp(off_type __off, ios_base::seekdir __dir)
    {
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      if (true)
 {
   if (!this->fail())
     {


       const pos_type __p = this->rdbuf()->pubseekoff(__off, __dir,
            ios_base::out);


       if (__p == pos_type(off_type(-1)))
  __err |= ios_base::failbit;
     }
 }
      if (false)
 { this->_M_setstate(ios_base::badbit); }
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_ostream<_CharT, _Traits>&
    operator<<(basic_ostream<_CharT, _Traits>& __out, const char* __s)
    {
      if (!__s)
 __out.setstate(ios_base::badbit);
      else
 {


   const size_t __clen = char_traits<char>::length(__s);
   _CharT* __ws = 0;
   if (true)
     {
       __ws = new _CharT[__clen];
       for (size_t __i = 0; __i < __clen; ++__i)
  __ws[__i] = __out.widen(__s[__i]);
     }
   if (false)
     {
       delete [] __ws;
       __out._M_setstate(ios_base::badbit);
       return __out;
     }

   if (true)
     {
       __ostream_insert(__out, __ws, __clen);
       delete [] __ws;
     }
   if (false)
     {
       delete [] __ws;
                              ;
     }
 }
      return __out;
    }





  extern template class basic_ostream<char>;
  extern template ostream& endl(ostream&);
  extern template ostream& ends(ostream&);
  extern template ostream& flush(ostream&);
  extern template ostream& operator<<(ostream&, char);
  extern template ostream& operator<<(ostream&, unsigned char);
  extern template ostream& operator<<(ostream&, signed char);
  extern template ostream& operator<<(ostream&, const char*);
  extern template ostream& operator<<(ostream&, const unsigned char*);
  extern template ostream& operator<<(ostream&, const signed char*);

  extern template ostream& ostream::_M_insert(long);
  extern template ostream& ostream::_M_insert(unsigned long);
  extern template ostream& ostream::_M_insert(bool);

  extern template ostream& ostream::_M_insert(long long);
  extern template ostream& ostream::_M_insert(unsigned long long);

  extern template ostream& ostream::_M_insert(double);
  extern template ostream& ostream::_M_insert(long double);
  extern template ostream& ostream::_M_insert(const void*);


  extern template class basic_ostream<wchar_t>;
  extern template wostream& endl(wostream&);
  extern template wostream& ends(wostream&);
  extern template wostream& flush(wostream&);
  extern template wostream& operator<<(wostream&, wchar_t);
  extern template wostream& operator<<(wostream&, char);
  extern template wostream& operator<<(wostream&, const wchar_t*);
  extern template wostream& operator<<(wostream&, const char*);

  extern template wostream& wostream::_M_insert(long);
  extern template wostream& wostream::_M_insert(unsigned long);
  extern template wostream& wostream::_M_insert(bool);

  extern template wostream& wostream::_M_insert(long long);
  extern template wostream& wostream::_M_insert(unsigned long long);

  extern template wostream& wostream::_M_insert(double);
  extern template wostream& wostream::_M_insert(long double);
  extern template wostream& wostream::_M_insert(const void*);



}




namespace std __attribute__ ((__visibility__ ("default"))) {
  template<typename _CharT, typename _Traits>
    class basic_istream : virtual public basic_ios<_CharT, _Traits>
    {
    public:

      typedef _CharT char_type;
      typedef typename _Traits::int_type int_type;
      typedef typename _Traits::pos_type pos_type;
      typedef typename _Traits::off_type off_type;
      typedef _Traits traits_type;


      typedef basic_streambuf<_CharT, _Traits> __streambuf_type;
      typedef basic_ios<_CharT, _Traits> __ios_type;
      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef num_get<_CharT, istreambuf_iterator<_CharT, _Traits> >
        __num_get_type;
      typedef ctype<_CharT> __ctype_type;

      template<typename _CharT2, typename _Traits2>
        friend basic_istream<_CharT2, _Traits2>&
        operator>>(basic_istream<_CharT2, _Traits2>&, _CharT2&);

      template<typename _CharT2, typename _Traits2>
        friend basic_istream<_CharT2, _Traits2>&
        operator>>(basic_istream<_CharT2, _Traits2>&, _CharT2*);

    protected:







      streamsize _M_gcount;

    public:
      explicit
      basic_istream(__streambuf_type* __sb): _M_gcount(streamsize(0))
      { this->init(__sb); }






      virtual
      ~basic_istream()
      { _M_gcount = streamsize(0); }


      class sentry;
      friend class sentry;
      __istream_type&
      operator>>(__istream_type& (*__pf)(__istream_type&))
      { return __pf(*this); }

      __istream_type&
      operator>>(__ios_type& (*__pf)(__ios_type&))
      {
 __pf(*this);
 return *this;
      }

      __istream_type&
      operator>>(ios_base& (*__pf)(ios_base&))
      {
 __pf(*this);
 return *this;
      }
      __istream_type&
      operator>>(bool& __n)
      { return _M_extract(__n); }

      __istream_type&
      operator>>(short& __n);

      __istream_type&
      operator>>(unsigned short& __n)
      { return _M_extract(__n); }

      __istream_type&
      operator>>(int& __n);

      __istream_type&
      operator>>(unsigned int& __n)
      { return _M_extract(__n); }

      __istream_type&
      operator>>(long& __n)
      { return _M_extract(__n); }

      __istream_type&
      operator>>(unsigned long& __n)
      { return _M_extract(__n); }


      __istream_type&
      operator>>(long long& __n)
      { return _M_extract(__n); }

      __istream_type&
      operator>>(unsigned long long& __n)
      { return _M_extract(__n); }


      __istream_type&
      operator>>(float& __f)
      { return _M_extract(__f); }

      __istream_type&
      operator>>(double& __f)
      { return _M_extract(__f); }

      __istream_type&
      operator>>(long double& __f)
      { return _M_extract(__f); }

      __istream_type&
      operator>>(void*& __p)
      { return _M_extract(__p); }
      __istream_type&
      operator>>(__streambuf_type* __sb);
      streamsize
      gcount() const
      { return _M_gcount; }
      int_type
      get();
      __istream_type&
      get(char_type& __c);
      __istream_type&
      get(char_type* __s, streamsize __n, char_type __delim);
      __istream_type&
      get(char_type* __s, streamsize __n)
      { return this->get(__s, __n, this->widen('\n')); }
      __istream_type&
      get(__streambuf_type& __sb, char_type __delim);
      __istream_type&
      get(__streambuf_type& __sb)
      { return this->get(__sb, this->widen('\n')); }
      __istream_type&
      getline(char_type* __s, streamsize __n, char_type __delim);
      __istream_type&
      getline(char_type* __s, streamsize __n)
      { return this->getline(__s, __n, this->widen('\n')); }
      __istream_type&
      ignore();

      __istream_type&
      ignore(streamsize __n);

      __istream_type&
      ignore(streamsize __n, int_type __delim);
      int_type
      peek();
      __istream_type&
      read(char_type* __s, streamsize __n);
      streamsize
      readsome(char_type* __s, streamsize __n);
      __istream_type&
      putback(char_type __c);
      __istream_type&
      unget();
      int
      sync();
      pos_type
      tellg();
      __istream_type&
      seekg(pos_type);
      __istream_type&
      seekg(off_type, ios_base::seekdir);


    protected:
      explicit
      basic_istream(): _M_gcount(streamsize(0)) { }

      template<typename _ValueT>
        __istream_type&
        _M_extract(_ValueT& __v);
    };


  template<>
    basic_istream<char>&
    basic_istream<char>::
    getline(char_type* __s, streamsize __n, char_type __delim);

  template<>
    basic_istream<char>&
    basic_istream<char>::
    ignore(streamsize __n);

  template<>
    basic_istream<char>&
    basic_istream<char>::
    ignore(streamsize __n, int_type __delim);


  template<>
    basic_istream<wchar_t>&
    basic_istream<wchar_t>::
    getline(char_type* __s, streamsize __n, char_type __delim);

  template<>
    basic_istream<wchar_t>&
    basic_istream<wchar_t>::
    ignore(streamsize __n);

  template<>
    basic_istream<wchar_t>&
    basic_istream<wchar_t>::
    ignore(streamsize __n, int_type __delim);
  template<typename _CharT, typename _Traits>
    class basic_istream<_CharT, _Traits>::sentry
    {
    public:

      typedef _Traits traits_type;
      typedef basic_streambuf<_CharT, _Traits> __streambuf_type;
      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef typename __istream_type::__ctype_type __ctype_type;
      typedef typename _Traits::int_type __int_type;
      explicit
      sentry(basic_istream<_CharT, _Traits>& __is, bool __noskipws = false);
      operator bool() const
      { return _M_ok; }

    private:
      bool _M_ok;
    };
  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    operator>>(basic_istream<_CharT, _Traits>& __in, _CharT& __c);

  template<class _Traits>
    inline basic_istream<char, _Traits>&
    operator>>(basic_istream<char, _Traits>& __in, unsigned char& __c)
    { return (__in >> reinterpret_cast<char&>(__c)); }

  template<class _Traits>
    inline basic_istream<char, _Traits>&
    operator>>(basic_istream<char, _Traits>& __in, signed char& __c)
    { return (__in >> reinterpret_cast<char&>(__c)); }
  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    operator>>(basic_istream<_CharT, _Traits>& __in, _CharT* __s);


  template<>
    basic_istream<char>&
    operator>>(basic_istream<char>& __in, char* __s);

  template<class _Traits>
    inline basic_istream<char, _Traits>&
    operator>>(basic_istream<char, _Traits>& __in, unsigned char* __s)
    { return (__in >> reinterpret_cast<char*>(__s)); }

  template<class _Traits>
    inline basic_istream<char, _Traits>&
    operator>>(basic_istream<char, _Traits>& __in, signed char* __s)
    { return (__in >> reinterpret_cast<char*>(__s)); }
  template<typename _CharT, typename _Traits>
    class basic_iostream
    : public basic_istream<_CharT, _Traits>,
      public basic_ostream<_CharT, _Traits>
    {
    public:



      typedef _CharT char_type;
      typedef typename _Traits::int_type int_type;
      typedef typename _Traits::pos_type pos_type;
      typedef typename _Traits::off_type off_type;
      typedef _Traits traits_type;


      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef basic_ostream<_CharT, _Traits> __ostream_type;







      explicit
      basic_iostream(basic_streambuf<_CharT, _Traits>* __sb)
      : __istream_type(), __ostream_type()
      { this->init(__sb); }




      virtual
      ~basic_iostream() { }

    protected:
      explicit
      basic_iostream() : __istream_type(), __ostream_type()
      { }
    };
  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    ws(basic_istream<_CharT, _Traits>& __is);

}







namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>::sentry::
    sentry(basic_istream<_CharT, _Traits>& __in, bool __noskip) : _M_ok(false)
    {
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      if (__in.good())
 {
   if (__in.tie())
     __in.tie()->flush();
   if (!__noskip && (__in.flags() & ios_base::skipws))
     {
       const __int_type __eof = traits_type::eof();
       __streambuf_type* __sb = __in.rdbuf();
       __int_type __c = __sb->sgetc();

       const __ctype_type& __ct = __check_facet(__in._M_ctype);
       while (!traits_type::eq_int_type(__c, __eof)
       && __ct.is(ctype_base::space,
    traits_type::to_char_type(__c)))
  __c = __sb->snextc();




       if (traits_type::eq_int_type(__c, __eof))
  __err |= ios_base::eofbit;
     }
 }

      if (__in.good() && __err == ios_base::goodbit)
 _M_ok = true;
      else
 {
   __err |= ios_base::failbit;
   __in.setstate(__err);
 }
    }

  template<typename _CharT, typename _Traits>
    template<typename _ValueT>
      basic_istream<_CharT, _Traits>&
      basic_istream<_CharT, _Traits>::
      _M_extract(_ValueT& __v)
      {
 sentry __cerb(*this, false);
 if (__cerb)
   {
     ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
     if (true)
       {
  const __num_get_type& __ng = __check_facet(this->_M_num_get);
  __ng.get(*this, 0, *this, __err, __v);
       }
     if (false)
       { this->_M_setstate(ios_base::badbit); }
     if (__err)
       this->setstate(__err);
   }
 return *this;
      }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    operator>>(short& __n)
    {


      long __l;
      _M_extract(__l);
      if (!this->fail())
 {
   if (numeric_limits<short>::min() <= __l
       && __l <= numeric_limits<short>::max())
     __n = __l;
   else
     this->setstate(ios_base::failbit);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    operator>>(int& __n)
    {


      long __l;
      _M_extract(__l);
      if (!this->fail())
 {
   if (numeric_limits<int>::min() <= __l
       && __l <= numeric_limits<int>::max())
     __n = __l;
   else
     this->setstate(ios_base::failbit);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    operator>>(__streambuf_type* __sbout)
    {
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      sentry __cerb(*this, false);
      if (__cerb && __sbout)
 {
   if (true)
     {
       bool __ineof;
       if (!__copy_streambufs_eof(this->rdbuf(), __sbout, __ineof))
  __err |= ios_base::failbit;
       if (__ineof)
  __err |= ios_base::eofbit;
     }
   if (false)
     { this->_M_setstate(ios_base::failbit); }
 }
      else if (!__sbout)
 __err |= ios_base::failbit;
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    typename basic_istream<_CharT, _Traits>::int_type
    basic_istream<_CharT, _Traits>::
    get(void)
    {
      const int_type __eof = traits_type::eof();
      int_type __c = __eof;
      _M_gcount = 0;
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      sentry __cerb(*this, true);
      if (__cerb)
 {
   if (true)
     {
       __c = this->rdbuf()->sbumpc();

       if (!traits_type::eq_int_type(__c, __eof))
  _M_gcount = 1;
       else
  __err |= ios_base::eofbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
 }
      if (!_M_gcount)
 __err |= ios_base::failbit;
      if (__err)
 this->setstate(__err);
      return __c;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    get(char_type& __c)
    {
      _M_gcount = 0;
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      sentry __cerb(*this, true);
      if (__cerb)
 {
   if (true)
     {
       const int_type __cb = this->rdbuf()->sbumpc();

       if (!traits_type::eq_int_type(__cb, traits_type::eof()))
  {
    _M_gcount = 1;
    __c = traits_type::to_char_type(__cb);
  }
       else
  __err |= ios_base::eofbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
 }
      if (!_M_gcount)
 __err |= ios_base::failbit;
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    get(char_type* __s, streamsize __n, char_type __delim)
    {
      _M_gcount = 0;
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      sentry __cerb(*this, true);
      if (__cerb)
 {
   if (true)
     {
       const int_type __idelim = traits_type::to_int_type(__delim);
       const int_type __eof = traits_type::eof();
       __streambuf_type* __sb = this->rdbuf();
       int_type __c = __sb->sgetc();

       while (_M_gcount + 1 < __n
       && !traits_type::eq_int_type(__c, __eof)
       && !traits_type::eq_int_type(__c, __idelim))
  {
    *__s++ = traits_type::to_char_type(__c);
    ++_M_gcount;
    __c = __sb->snextc();
  }
       if (traits_type::eq_int_type(__c, __eof))
  __err |= ios_base::eofbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
 }


      if (__n > 0)
 *__s = char_type();
      if (!_M_gcount)
 __err |= ios_base::failbit;
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    get(__streambuf_type& __sb, char_type __delim)
    {
      _M_gcount = 0;
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      sentry __cerb(*this, true);
      if (__cerb)
 {
   if (true)
     {
       const int_type __idelim = traits_type::to_int_type(__delim);
       const int_type __eof = traits_type::eof();
       __streambuf_type* __this_sb = this->rdbuf();
       int_type __c = __this_sb->sgetc();
       char_type __c2 = traits_type::to_char_type(__c);

       while (!traits_type::eq_int_type(__c, __eof)
       && !traits_type::eq_int_type(__c, __idelim)
       && !traits_type::eq_int_type(__sb.sputc(__c2), __eof))
  {
    ++_M_gcount;
    __c = __this_sb->snextc();
    __c2 = traits_type::to_char_type(__c);
  }
       if (traits_type::eq_int_type(__c, __eof))
  __err |= ios_base::eofbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
 }
      if (!_M_gcount)
 __err |= ios_base::failbit;
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    getline(char_type* __s, streamsize __n, char_type __delim)
    {
      _M_gcount = 0;
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      sentry __cerb(*this, true);
      if (__cerb)
        {
          if (true)
            {
              const int_type __idelim = traits_type::to_int_type(__delim);
              const int_type __eof = traits_type::eof();
              __streambuf_type* __sb = this->rdbuf();
              int_type __c = __sb->sgetc();

              while (_M_gcount + 1 < __n
                     && !traits_type::eq_int_type(__c, __eof)
                     && !traits_type::eq_int_type(__c, __idelim))
                {
                  *__s++ = traits_type::to_char_type(__c);
                  __c = __sb->snextc();
                  ++_M_gcount;
                }
              if (traits_type::eq_int_type(__c, __eof))
                __err |= ios_base::eofbit;
              else
                {
                  if (traits_type::eq_int_type(__c, __idelim))
                    {
                      __sb->sbumpc();
                      ++_M_gcount;
                    }
                  else
                    __err |= ios_base::failbit;
                }
            }
          if (false)
            { this->_M_setstate(ios_base::badbit); }
        }


      if (__n > 0)
 *__s = char_type();
      if (!_M_gcount)
        __err |= ios_base::failbit;
      if (__err)
        this->setstate(__err);
      return *this;
    }




  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    ignore(void)
    {
      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       const int_type __eof = traits_type::eof();
       __streambuf_type* __sb = this->rdbuf();

       if (traits_type::eq_int_type(__sb->sbumpc(), __eof))
  __err |= ios_base::eofbit;
       else
  _M_gcount = 1;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    ignore(streamsize __n)
    {
      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb && __n > 0)
        {
          ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
          if (true)
            {
              const int_type __eof = traits_type::eof();
              __streambuf_type* __sb = this->rdbuf();
              int_type __c = __sb->sgetc();
       bool __large_ignore = false;
       while (true)
  {
    while (_M_gcount < __n
    && !traits_type::eq_int_type(__c, __eof))
      {
        ++_M_gcount;
        __c = __sb->snextc();
      }
    if (__n == numeric_limits<streamsize>::max()
        && !traits_type::eq_int_type(__c, __eof))
      {
        _M_gcount = numeric_limits<streamsize>::min();
        __large_ignore = true;
      }
    else
      break;
  }

       if (__large_ignore)
  _M_gcount = numeric_limits<streamsize>::max();

       if (traits_type::eq_int_type(__c, __eof))
                __err |= ios_base::eofbit;
            }
          if (false)
            { this->_M_setstate(ios_base::badbit); }
          if (__err)
            this->setstate(__err);
        }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    ignore(streamsize __n, int_type __delim)
    {
      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb && __n > 0)
        {
          ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
          if (true)
            {
              const int_type __eof = traits_type::eof();
              __streambuf_type* __sb = this->rdbuf();
              int_type __c = __sb->sgetc();


       bool __large_ignore = false;
       while (true)
  {
    while (_M_gcount < __n
    && !traits_type::eq_int_type(__c, __eof)
    && !traits_type::eq_int_type(__c, __delim))
      {
        ++_M_gcount;
        __c = __sb->snextc();
      }
    if (__n == numeric_limits<streamsize>::max()
        && !traits_type::eq_int_type(__c, __eof)
        && !traits_type::eq_int_type(__c, __delim))
      {
        _M_gcount = numeric_limits<streamsize>::min();
        __large_ignore = true;
      }
    else
      break;
  }

       if (__large_ignore)
  _M_gcount = numeric_limits<streamsize>::max();

              if (traits_type::eq_int_type(__c, __eof))
                __err |= ios_base::eofbit;
       else if (traits_type::eq_int_type(__c, __delim))
  {
    if (_M_gcount < numeric_limits<streamsize>::max())
      ++_M_gcount;
    __sb->sbumpc();
  }
            }
          if (false)
            { this->_M_setstate(ios_base::badbit); }
          if (__err)
            this->setstate(__err);
        }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    typename basic_istream<_CharT, _Traits>::int_type
    basic_istream<_CharT, _Traits>::
    peek(void)
    {
      int_type __c = traits_type::eof();
      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       __c = this->rdbuf()->sgetc();
       if (traits_type::eq_int_type(__c, traits_type::eof()))
  __err |= ios_base::eofbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return __c;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    read(char_type* __s, streamsize __n)
    {
      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       _M_gcount = this->rdbuf()->sgetn(__s, __n);
       if (_M_gcount != __n)
  __err |= (ios_base::eofbit | ios_base::failbit);
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    streamsize
    basic_istream<_CharT, _Traits>::
    readsome(char_type* __s, streamsize __n)
    {
      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {

       const streamsize __num = this->rdbuf()->in_avail();
       if (__num > 0)
  _M_gcount = this->rdbuf()->sgetn(__s, std::min(__num, __n));
       else if (__num == -1)
  __err |= ios_base::eofbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return _M_gcount;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    putback(char_type __c)
    {


      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       const int_type __eof = traits_type::eof();
       __streambuf_type* __sb = this->rdbuf();
       if (!__sb
    || traits_type::eq_int_type(__sb->sputbackc(__c), __eof))
  __err |= ios_base::badbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    unget(void)
    {


      _M_gcount = 0;
      sentry __cerb(*this, true);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       const int_type __eof = traits_type::eof();
       __streambuf_type* __sb = this->rdbuf();
       if (!__sb
    || traits_type::eq_int_type(__sb->sungetc(), __eof))
  __err |= ios_base::badbit;
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return *this;
    }

  template<typename _CharT, typename _Traits>
    int
    basic_istream<_CharT, _Traits>::
    sync(void)
    {


      int __ret = -1;
      sentry __cerb(*this, true);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       __streambuf_type* __sb = this->rdbuf();
       if (__sb)
  {
    if (__sb->pubsync() == -1)
      __err |= ios_base::badbit;
    else
      __ret = 0;
  }
     }
   if (false)
     { this->_M_setstate(ios_base::badbit); }
   if (__err)
     this->setstate(__err);
 }
      return __ret;
    }

  template<typename _CharT, typename _Traits>
    typename basic_istream<_CharT, _Traits>::pos_type
    basic_istream<_CharT, _Traits>::
    tellg(void)
    {


      pos_type __ret = pos_type(-1);
      if (true)
 {
   if (!this->fail())
     __ret = this->rdbuf()->pubseekoff(0, ios_base::cur,
           ios_base::in);
 }
      if (false)
 { this->_M_setstate(ios_base::badbit); }
      return __ret;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    seekg(pos_type __pos)
    {


      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      if (true)
 {
   if (!this->fail())
     {

       const pos_type __p = this->rdbuf()->pubseekpos(__pos,
            ios_base::in);


       if (__p == pos_type(off_type(-1)))
  __err |= ios_base::failbit;
     }
 }
      if (false)
 { this->_M_setstate(ios_base::badbit); }
      if (__err)
 this->setstate(__err);
      return *this;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    basic_istream<_CharT, _Traits>::
    seekg(off_type __off, ios_base::seekdir __dir)
    {


      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      if (true)
 {
   if (!this->fail())
     {

       const pos_type __p = this->rdbuf()->pubseekoff(__off, __dir,
            ios_base::in);


       if (__p == pos_type(off_type(-1)))
  __err |= ios_base::failbit;
     }
 }
      if (false)
 { this->_M_setstate(ios_base::badbit); }
      if (__err)
 this->setstate(__err);
      return *this;
    }


  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    operator>>(basic_istream<_CharT, _Traits>& __in, _CharT& __c)
    {
      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef typename __istream_type::int_type __int_type;

      typename __istream_type::sentry __cerb(__in, false);
      if (__cerb)
 {
   ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
   if (true)
     {
       const __int_type __cb = __in.rdbuf()->sbumpc();
       if (!_Traits::eq_int_type(__cb, _Traits::eof()))
  __c = _Traits::to_char_type(__cb);
       else
  __err |= (ios_base::eofbit | ios_base::failbit);
     }
   if (false)
     { __in._M_setstate(ios_base::badbit); }
   if (__err)
     __in.setstate(__err);
 }
      return __in;
    }

  template<typename _CharT, typename _Traits>
    basic_istream<_CharT, _Traits>&
    operator>>(basic_istream<_CharT, _Traits>& __in, _CharT* __s)
    {
      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef typename __istream_type::__streambuf_type __streambuf_type;
      typedef typename _Traits::int_type int_type;
      typedef _CharT char_type;
      typedef ctype<_CharT> __ctype_type;

      streamsize __extracted = 0;
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      typename __istream_type::sentry __cerb(__in, false);
      if (__cerb)
 {
   if (true)
     {

       streamsize __num = __in.width();
       if (__num <= 0)
  __num = numeric_limits<streamsize>::max();

       const __ctype_type& __ct = use_facet<__ctype_type>(__in.getloc());

       const int_type __eof = _Traits::eof();
       __streambuf_type* __sb = __in.rdbuf();
       int_type __c = __sb->sgetc();

       while (__extracted < __num - 1
       && !_Traits::eq_int_type(__c, __eof)
       && !__ct.is(ctype_base::space,
     _Traits::to_char_type(__c)))
  {
    *__s++ = _Traits::to_char_type(__c);
    ++__extracted;
    __c = __sb->snextc();
  }
       if (_Traits::eq_int_type(__c, __eof))
  __err |= ios_base::eofbit;



       *__s = char_type();
       __in.width(0);
     }
   if (false)
     { __in._M_setstate(ios_base::badbit); }
 }
      if (!__extracted)
 __err |= ios_base::failbit;
      if (__err)
 __in.setstate(__err);
      return __in;
    }


  template<typename _CharT, typename _Traits>
    basic_istream<_CharT,_Traits>&
    ws(basic_istream<_CharT,_Traits>& __in)
    {
      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef typename __istream_type::__streambuf_type __streambuf_type;
      typedef typename __istream_type::__ctype_type __ctype_type;
      typedef typename __istream_type::int_type __int_type;

      const __ctype_type& __ct = use_facet<__ctype_type>(__in.getloc());
      const __int_type __eof = _Traits::eof();
      __streambuf_type* __sb = __in.rdbuf();
      __int_type __c = __sb->sgetc();

      while (!_Traits::eq_int_type(__c, __eof)
      && __ct.is(ctype_base::space, _Traits::to_char_type(__c)))
 __c = __sb->snextc();

       if (_Traits::eq_int_type(__c, __eof))
  __in.setstate(ios_base::eofbit);
      return __in;
    }


  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_istream<_CharT, _Traits>&
    operator>>(basic_istream<_CharT, _Traits>& __in,
        basic_string<_CharT, _Traits, _Alloc>& __str)
    {
      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef typename __istream_type::int_type __int_type;
      typedef typename __istream_type::__streambuf_type __streambuf_type;
      typedef typename __istream_type::__ctype_type __ctype_type;
      typedef basic_string<_CharT, _Traits, _Alloc> __string_type;
      typedef typename __string_type::size_type __size_type;

      __size_type __extracted = 0;
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      typename __istream_type::sentry __cerb(__in, false);
      if (__cerb)
 {
   if (true)
     {

       __str.erase();
       _CharT __buf[128];
       __size_type __len = 0;
       const streamsize __w = __in.width();
       const __size_type __n = __w > 0 ? static_cast<__size_type>(__w)
                                : __str.max_size();
       const __ctype_type& __ct = use_facet<__ctype_type>(__in.getloc());
       const __int_type __eof = _Traits::eof();
       __streambuf_type* __sb = __in.rdbuf();
       __int_type __c = __sb->sgetc();

       while (__extracted < __n
       && !_Traits::eq_int_type(__c, __eof)
       && !__ct.is(ctype_base::space, _Traits::to_char_type(__c)))
  {
    if (__len == sizeof(__buf) / sizeof(_CharT))
      {
        __str.append(__buf, sizeof(__buf) / sizeof(_CharT));
        __len = 0;
      }
    __buf[__len++] = _Traits::to_char_type(__c);
    ++__extracted;
    __c = __sb->snextc();
  }
       __str.append(__buf, __len);

       if (_Traits::eq_int_type(__c, __eof))
  __err |= ios_base::eofbit;
       __in.width(0);
     }
   if (false)
     {



       __in._M_setstate(ios_base::badbit);
     }
 }

      if (!__extracted)
 __err |= ios_base::failbit;
      if (__err)
 __in.setstate(__err);
      return __in;
    }

  template<typename _CharT, typename _Traits, typename _Alloc>
    basic_istream<_CharT, _Traits>&
    getline(basic_istream<_CharT, _Traits>& __in,
     basic_string<_CharT, _Traits, _Alloc>& __str, _CharT __delim)
    {
      typedef basic_istream<_CharT, _Traits> __istream_type;
      typedef typename __istream_type::int_type __int_type;
      typedef typename __istream_type::__streambuf_type __streambuf_type;
      typedef typename __istream_type::__ctype_type __ctype_type;
      typedef basic_string<_CharT, _Traits, _Alloc> __string_type;
      typedef typename __string_type::size_type __size_type;

      __size_type __extracted = 0;
      const __size_type __n = __str.max_size();
      ios_base::iostate __err = ios_base::iostate(ios_base::goodbit);
      typename __istream_type::sentry __cerb(__in, true);
      if (__cerb)
 {
   if (true)
     {
       __str.erase();
       const __int_type __idelim = _Traits::to_int_type(__delim);
       const __int_type __eof = _Traits::eof();
       __streambuf_type* __sb = __in.rdbuf();
       __int_type __c = __sb->sgetc();

       while (__extracted < __n
       && !_Traits::eq_int_type(__c, __eof)
       && !_Traits::eq_int_type(__c, __idelim))
  {
    __str += _Traits::to_char_type(__c);
    ++__extracted;
    __c = __sb->snextc();
  }

       if (_Traits::eq_int_type(__c, __eof))
  __err |= ios_base::eofbit;
       else if (_Traits::eq_int_type(__c, __idelim))
  {
    ++__extracted;
    __sb->sbumpc();
  }
       else
  __err |= ios_base::failbit;
     }
   if (false)
     {



       __in._M_setstate(ios_base::badbit);
     }
 }
      if (!__extracted)
 __err |= ios_base::failbit;
      if (__err)
 __in.setstate(__err);
      return __in;
    }





  extern template class basic_istream<char>;
  extern template istream& ws(istream&);
  extern template istream& operator>>(istream&, char&);
  extern template istream& operator>>(istream&, char*);
  extern template istream& operator>>(istream&, unsigned char&);
  extern template istream& operator>>(istream&, signed char&);
  extern template istream& operator>>(istream&, unsigned char*);
  extern template istream& operator>>(istream&, signed char*);

  extern template istream& istream::_M_extract(unsigned short&);
  extern template istream& istream::_M_extract(unsigned int&);
  extern template istream& istream::_M_extract(long&);
  extern template istream& istream::_M_extract(unsigned long&);
  extern template istream& istream::_M_extract(bool&);

  extern template istream& istream::_M_extract(long long&);
  extern template istream& istream::_M_extract(unsigned long long&);

  extern template istream& istream::_M_extract(float&);
  extern template istream& istream::_M_extract(double&);
  extern template istream& istream::_M_extract(long double&);
  extern template istream& istream::_M_extract(void*&);

  extern template class basic_iostream<char>;


  extern template class basic_istream<wchar_t>;
  extern template wistream& ws(wistream&);
  extern template wistream& operator>>(wistream&, wchar_t&);
  extern template wistream& operator>>(wistream&, wchar_t*);

  extern template wistream& wistream::_M_extract(unsigned short&);
  extern template wistream& wistream::_M_extract(unsigned int&);
  extern template wistream& wistream::_M_extract(long&);
  extern template wistream& wistream::_M_extract(unsigned long&);
  extern template wistream& wistream::_M_extract(bool&);

  extern template wistream& wistream::_M_extract(long long&);
  extern template wistream& wistream::_M_extract(unsigned long long&);

  extern template wistream& wistream::_M_extract(float&);
  extern template wistream& wistream::_M_extract(double&);
  extern template wistream& wistream::_M_extract(long double&);
  extern template wistream& wistream::_M_extract(void*&);

  extern template class basic_iostream<wchar_t>;



}



namespace std __attribute__ ((__visibility__ ("default"))) {


  template<typename _Tp, typename _CharT = char,
           typename _Traits = char_traits<_CharT>, typename _Dist = ptrdiff_t>
    class istream_iterator
    : public iterator<input_iterator_tag, _Tp, _Dist, const _Tp*, const _Tp&>
    {
    public:
      typedef _CharT char_type;
      typedef _Traits traits_type;
      typedef basic_istream<_CharT, _Traits> istream_type;

    private:
      istream_type* _M_stream;
      _Tp _M_value;
      bool _M_ok;

    public:

      istream_iterator()
      : _M_stream(0), _M_value(), _M_ok(false) {}


      istream_iterator(istream_type& __s)
      : _M_stream(&__s)
      { _M_read(); }

      istream_iterator(const istream_iterator& __obj)
      : _M_stream(__obj._M_stream), _M_value(__obj._M_value),
        _M_ok(__obj._M_ok)
      { }

      const _Tp&
      operator*() const
      {


                        ;
 return _M_value;
      }

      const _Tp*
      operator->() const { return &(operator*()); }

      istream_iterator&
      operator++()
      {


                        ;
 _M_read();
 return *this;
      }

      istream_iterator
      operator++(int)
      {


                        ;
 istream_iterator __tmp = *this;
 _M_read();
 return __tmp;
      }

      bool
      _M_equal(const istream_iterator& __x) const
      { return (_M_ok == __x._M_ok) && (!_M_ok || _M_stream == __x._M_stream); }

    private:
      void
      _M_read()
      {
 _M_ok = (_M_stream && *_M_stream) ? true : false;
 if (_M_ok)
   {
     *_M_stream >> _M_value;
     _M_ok = *_M_stream ? true : false;
   }
      }
    };


  template<typename _Tp, typename _CharT, typename _Traits, typename _Dist>
    inline bool
    operator==(const istream_iterator<_Tp, _CharT, _Traits, _Dist>& __x,
        const istream_iterator<_Tp, _CharT, _Traits, _Dist>& __y)
    { return __x._M_equal(__y); }


  template <class _Tp, class _CharT, class _Traits, class _Dist>
    inline bool
    operator!=(const istream_iterator<_Tp, _CharT, _Traits, _Dist>& __x,
        const istream_iterator<_Tp, _CharT, _Traits, _Dist>& __y)
    { return !__x._M_equal(__y); }
  template<typename _Tp, typename _CharT = char,
           typename _Traits = char_traits<_CharT> >
    class ostream_iterator
    : public iterator<output_iterator_tag, void, void, void, void>
    {
    public:


      typedef _CharT char_type;
      typedef _Traits traits_type;
      typedef basic_ostream<_CharT, _Traits> ostream_type;


    private:
      ostream_type* _M_stream;
      const _CharT* _M_string;

    public:

      ostream_iterator(ostream_type& __s) : _M_stream(&__s), _M_string(0) {}
      ostream_iterator(ostream_type& __s, const _CharT* __c)
      : _M_stream(&__s), _M_string(__c) { }


      ostream_iterator(const ostream_iterator& __obj)
      : _M_stream(__obj._M_stream), _M_string(__obj._M_string) { }



      ostream_iterator&
      operator=(const _Tp& __value)
      {


                        ;
 *_M_stream << __value;
 if (_M_string) *_M_stream << _M_string;
 return *this;
      }

      ostream_iterator&
      operator*()
      { return *this; }

      ostream_iterator&
      operator++()
      { return *this; }

      ostream_iterator&
      operator++(int)
      { return *this; }
    };

}






namespace llvm {

template<typename KeyT, typename ValueT,
         typename KeyInfoT = DenseMapInfo<KeyT>,
         typename ValueInfoT = DenseMapInfo<ValueT>, bool IsConst = false>
class DenseMapIterator;

template<typename KeyT, typename ValueT,
         typename KeyInfoT = DenseMapInfo<KeyT>,
         typename ValueInfoT = DenseMapInfo<ValueT> >
class DenseMap {
  typedef std::pair<KeyT, ValueT> BucketT;
  unsigned NumBuckets;
  BucketT *Buckets;

  unsigned NumEntries;
  unsigned NumTombstones;
public:
  typedef KeyT key_type;
  typedef ValueT mapped_type;
  typedef BucketT value_type;

  DenseMap(const DenseMap &other) {
    NumBuckets = 0;
    CopyFrom(other);
  }

  explicit DenseMap(unsigned NumInitBuckets = 0) {
    init(NumInitBuckets);
  }

  template<typename InputIt>
  DenseMap(const InputIt &I, const InputIt &E) {
    init(NextPowerOf2(std::distance(I, E)));
    insert(I, E);
  }

  ~DenseMap() {
    const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
    for (BucketT *P = Buckets, *E = Buckets+NumBuckets; P != E; ++P) {
      if (!KeyInfoT::isEqual(P->first, EmptyKey) &&
          !KeyInfoT::isEqual(P->first, TombstoneKey))
        P->second.~ValueT();
      P->first.~KeyT();
    }

    if (NumBuckets)
      memset((void*)Buckets, 0x5a, sizeof(BucketT)*NumBuckets);

    operator delete(Buckets);
  }

  typedef DenseMapIterator<KeyT, ValueT, KeyInfoT> iterator;
  typedef DenseMapIterator<KeyT, ValueT,
                           KeyInfoT, ValueInfoT, true> const_iterator;
  inline iterator begin() {

    return empty() ? end() : iterator(Buckets, Buckets+NumBuckets);
  }
  inline iterator end() {
    return iterator(Buckets+NumBuckets, Buckets+NumBuckets);
  }
  inline const_iterator begin() const {
    return empty() ? end() : const_iterator(Buckets, Buckets+NumBuckets);
  }
  inline const_iterator end() const {
    return const_iterator(Buckets+NumBuckets, Buckets+NumBuckets);
  }

  bool empty() const { return NumEntries == 0; }
  unsigned size() const { return NumEntries; }


  void resize(size_t Size) {
    if (Size > NumBuckets)
      grow(Size);
  }

  void clear() {
    if (NumEntries == 0 && NumTombstones == 0) return;



    if (NumEntries * 4 < NumBuckets && NumBuckets > 64) {
      shrink_and_clear();
      return;
    }

    const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
    for (BucketT *P = Buckets, *E = Buckets+NumBuckets; P != E; ++P) {
      if (!KeyInfoT::isEqual(P->first, EmptyKey)) {
        if (!KeyInfoT::isEqual(P->first, TombstoneKey)) {
          P->second.~ValueT();
          --NumEntries;
        }
        P->first = EmptyKey;
      }
    }
    ((NumEntries == 0 && "Node count imbalance!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/DenseMap.h", 127, "NumEntries == 0 && \"Node count imbalance!\""));
    NumTombstones = 0;
  }


  bool count(const KeyT &Val) const {
    BucketT *TheBucket;
    return LookupBucketFor(Val, TheBucket);
  }

  iterator find(const KeyT &Val) {
    BucketT *TheBucket;
    if (LookupBucketFor(Val, TheBucket))
      return iterator(TheBucket, Buckets+NumBuckets);
    return end();
  }
  const_iterator find(const KeyT &Val) const {
    BucketT *TheBucket;
    if (LookupBucketFor(Val, TheBucket))
      return const_iterator(TheBucket, Buckets+NumBuckets);
    return end();
  }



  ValueT lookup(const KeyT &Val) const {
    BucketT *TheBucket;
    if (LookupBucketFor(Val, TheBucket))
      return TheBucket->second;
    return ValueT();
  }




  std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
    BucketT *TheBucket;
    if (LookupBucketFor(KV.first, TheBucket))
      return std::make_pair(iterator(TheBucket, Buckets+NumBuckets),
                            false);


    TheBucket = InsertIntoBucket(KV.first, KV.second, TheBucket);
    return std::make_pair(iterator(TheBucket, Buckets+NumBuckets),
                          true);
  }


  template<typename InputIt>
  void insert(InputIt I, InputIt E) {
    for (; I != E; ++I)
      insert(*I);
  }


  bool erase(const KeyT &Val) {
    BucketT *TheBucket;
    if (!LookupBucketFor(Val, TheBucket))
      return false;

    TheBucket->second.~ValueT();
    TheBucket->first = getTombstoneKey();
    --NumEntries;
    ++NumTombstones;
    return true;
  }
  void erase(iterator I) {
    BucketT *TheBucket = &*I;
    TheBucket->second.~ValueT();
    TheBucket->first = getTombstoneKey();
    --NumEntries;
    ++NumTombstones;
  }

  void swap(DenseMap& RHS) {
    std::swap(NumBuckets, RHS.NumBuckets);
    std::swap(Buckets, RHS.Buckets);
    std::swap(NumEntries, RHS.NumEntries);
    std::swap(NumTombstones, RHS.NumTombstones);
  }

  value_type& FindAndConstruct(const KeyT &Key) {
    BucketT *TheBucket;
    if (LookupBucketFor(Key, TheBucket))
      return *TheBucket;

    return *InsertIntoBucket(Key, ValueT(), TheBucket);
  }

  ValueT &operator[](const KeyT &Key) {
    return FindAndConstruct(Key).second;
  }

  DenseMap& operator=(const DenseMap& other) {
    CopyFrom(other);
    return *this;
  }




  bool isPointerIntoBucketsArray(const void *Ptr) const {
    return Ptr >= Buckets && Ptr < Buckets+NumBuckets;
  }




  const void *getPointerIntoBucketsArray() const { return Buckets; }

private:
  void CopyFrom(const DenseMap& other) {
    if (NumBuckets != 0 &&
        (!isPodLike<KeyInfoT>::value || !isPodLike<ValueInfoT>::value)) {
      const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
      for (BucketT *P = Buckets, *E = Buckets+NumBuckets; P != E; ++P) {
        if (!KeyInfoT::isEqual(P->first, EmptyKey) &&
            !KeyInfoT::isEqual(P->first, TombstoneKey))
          P->second.~ValueT();
        P->first.~KeyT();
      }
    }

    NumEntries = other.NumEntries;
    NumTombstones = other.NumTombstones;

    if (NumBuckets) {

      memset((void*)Buckets, 0x5a, sizeof(BucketT)*NumBuckets);

      operator delete(Buckets);
    }

    NumBuckets = other.NumBuckets;

    if (NumBuckets == 0) {
      Buckets = 0;
      return;
    }

    Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT) * NumBuckets));

    if (isPodLike<KeyInfoT>::value && isPodLike<ValueInfoT>::value)
      memcpy(Buckets, other.Buckets, NumBuckets * sizeof(BucketT));
    else
      for (size_t i = 0; i < NumBuckets; ++i) {
        new (&Buckets[i].first) KeyT(other.Buckets[i].first);
        if (!KeyInfoT::isEqual(Buckets[i].first, getEmptyKey()) &&
            !KeyInfoT::isEqual(Buckets[i].first, getTombstoneKey()))
          new (&Buckets[i].second) ValueT(other.Buckets[i].second);
      }
  }

  BucketT *InsertIntoBucket(const KeyT &Key, const ValueT &Value,
                            BucketT *TheBucket) {
    ++NumEntries;
    if (NumEntries*4 >= NumBuckets*3) {
      this->grow(NumBuckets * 2);
      LookupBucketFor(Key, TheBucket);
    }
    if (NumBuckets-(NumEntries+NumTombstones) < NumBuckets/8) {
      this->grow(NumBuckets);
      LookupBucketFor(Key, TheBucket);
    }


    if (!KeyInfoT::isEqual(TheBucket->first, getEmptyKey()))
      --NumTombstones;

    TheBucket->first = Key;
    new (&TheBucket->second) ValueT(Value);
    return TheBucket;
  }

  static unsigned getHashValue(const KeyT &Val) {
    return KeyInfoT::getHashValue(Val);
  }
  static const KeyT getEmptyKey() {
    return KeyInfoT::getEmptyKey();
  }
  static const KeyT getTombstoneKey() {
    return KeyInfoT::getTombstoneKey();
  }





  bool LookupBucketFor(const KeyT &Val, BucketT *&FoundBucket) const {
    unsigned BucketNo = getHashValue(Val);
    unsigned ProbeAmt = 1;
    BucketT *BucketsPtr = Buckets;

    if (NumBuckets == 0) {
      FoundBucket = 0;
      return false;
    }


    BucketT *FoundTombstone = 0;
    const KeyT EmptyKey = getEmptyKey();
    const KeyT TombstoneKey = getTombstoneKey();
    ((!KeyInfoT::isEqual(Val, EmptyKey) && !KeyInfoT::isEqual(Val, TombstoneKey) && "Empty/Tombstone value shouldn't be inserted into map!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/DenseMap.h", 340, "!KeyInfoT::isEqual(Val, EmptyKey) && !KeyInfoT::isEqual(Val, TombstoneKey) && \"Empty/Tombstone value shouldn't be inserted into map!\""));



    while (1) {
      BucketT *ThisBucket = BucketsPtr + (BucketNo & (NumBuckets-1));

      if (KeyInfoT::isEqual(ThisBucket->first, Val)) {
        FoundBucket = ThisBucket;
        return true;
      }



      if (KeyInfoT::isEqual(ThisBucket->first, EmptyKey)) {


        if (FoundTombstone) ThisBucket = FoundTombstone;
        FoundBucket = FoundTombstone ? FoundTombstone : ThisBucket;
        return false;
      }



      if (KeyInfoT::isEqual(ThisBucket->first, TombstoneKey) && !FoundTombstone)
        FoundTombstone = ThisBucket;



      BucketNo += ProbeAmt++;
    }
  }

  void init(unsigned InitBuckets) {
    NumEntries = 0;
    NumTombstones = 0;
    NumBuckets = InitBuckets;

    if (InitBuckets == 0) {
      Buckets = 0;
      return;
    }

    ((InitBuckets && (InitBuckets & (InitBuckets-1)) == 0 && "# initial buckets must be a power of two!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/DenseMap.h", 382, "InitBuckets && (InitBuckets & (InitBuckets-1)) == 0 && \"# initial buckets must be a power of two!\""));

    Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT)*InitBuckets));

    const KeyT EmptyKey = getEmptyKey();
    for (unsigned i = 0; i != InitBuckets; ++i)
      new (&Buckets[i].first) KeyT(EmptyKey);
  }

  void grow(unsigned AtLeast) {
    unsigned OldNumBuckets = NumBuckets;
    BucketT *OldBuckets = Buckets;

    if (NumBuckets < 64)
      NumBuckets = 64;


    while (NumBuckets < AtLeast)
      NumBuckets <<= 1;
    NumTombstones = 0;
    Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT)*NumBuckets));


    const KeyT EmptyKey = getEmptyKey();
    for (unsigned i = 0, e = NumBuckets; i != e; ++i)
      new (&Buckets[i].first) KeyT(EmptyKey);


    const KeyT TombstoneKey = getTombstoneKey();
    for (BucketT *B = OldBuckets, *E = OldBuckets+OldNumBuckets; B != E; ++B) {
      if (!KeyInfoT::isEqual(B->first, EmptyKey) &&
          !KeyInfoT::isEqual(B->first, TombstoneKey)) {

        BucketT *DestBucket;
        bool FoundVal = LookupBucketFor(B->first, DestBucket);
        (void)FoundVal;
        ((!FoundVal && "Key already in new map?") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/DenseMap.h", 417, "!FoundVal && \"Key already in new map?\""));
        DestBucket->first = B->first;
        new (&DestBucket->second) ValueT(B->second);


        B->second.~ValueT();
      }
      B->first.~KeyT();
    }


    if (OldNumBuckets)
      memset((void*)OldBuckets, 0x5a, sizeof(BucketT)*OldNumBuckets);


    operator delete(OldBuckets);
  }

  void shrink_and_clear() {
    unsigned OldNumBuckets = NumBuckets;
    BucketT *OldBuckets = Buckets;


    NumBuckets = NumEntries > 32 ? 1 << (Log2_32_Ceil(NumEntries) + 1)
                                 : 64;
    NumTombstones = 0;
    Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT)*NumBuckets));


    const KeyT EmptyKey = getEmptyKey();
    for (unsigned i = 0, e = NumBuckets; i != e; ++i)
      new (&Buckets[i].first) KeyT(EmptyKey);


    const KeyT TombstoneKey = getTombstoneKey();
    for (BucketT *B = OldBuckets, *E = OldBuckets+OldNumBuckets; B != E; ++B) {
      if (!KeyInfoT::isEqual(B->first, EmptyKey) &&
          !KeyInfoT::isEqual(B->first, TombstoneKey)) {

        B->second.~ValueT();
      }
      B->first.~KeyT();
    }


    memset((void*)OldBuckets, 0x5a, sizeof(BucketT)*OldNumBuckets);


    operator delete(OldBuckets);

    NumEntries = 0;
  }

public:




  size_t getMemorySize() const {
    return NumBuckets * sizeof(BucketT);
  }
};

template<typename KeyT, typename ValueT,
         typename KeyInfoT, typename ValueInfoT, bool IsConst>
class DenseMapIterator {
  typedef std::pair<KeyT, ValueT> Bucket;
  typedef DenseMapIterator<KeyT, ValueT,
                           KeyInfoT, ValueInfoT, true> ConstIterator;
  friend class DenseMapIterator<KeyT, ValueT, KeyInfoT, ValueInfoT, true>;
public:
  typedef ptrdiff_t difference_type;
  typedef typename conditional<IsConst, const Bucket, Bucket>::type value_type;
  typedef value_type *pointer;
  typedef value_type &reference;
  typedef std::forward_iterator_tag iterator_category;
private:
  pointer Ptr, End;
public:
  DenseMapIterator() : Ptr(0), End(0) {}

  DenseMapIterator(pointer Pos, pointer E) : Ptr(Pos), End(E) {
    AdvancePastEmptyBuckets();
  }




  DenseMapIterator(const DenseMapIterator<KeyT, ValueT,
                                          KeyInfoT, ValueInfoT, false>& I)
    : Ptr(I.Ptr), End(I.End) {}

  reference operator*() const {
    return *Ptr;
  }
  pointer operator->() const {
    return Ptr;
  }

  bool operator==(const ConstIterator &RHS) const {
    return Ptr == RHS.operator->();
  }
  bool operator!=(const ConstIterator &RHS) const {
    return Ptr != RHS.operator->();
  }

  inline DenseMapIterator& operator++() {
    ++Ptr;
    AdvancePastEmptyBuckets();
    return *this;
  }
  DenseMapIterator operator++(int) {
    DenseMapIterator tmp = *this; ++*this; return tmp;
  }

private:
  void AdvancePastEmptyBuckets() {
    const KeyT Empty = KeyInfoT::getEmptyKey();
    const KeyT Tombstone = KeyInfoT::getTombstoneKey();

    while (Ptr != End &&
           (KeyInfoT::isEqual(Ptr->first, Empty) ||
            KeyInfoT::isEqual(Ptr->first, Tombstone)))
      ++Ptr;
  }
};

template<typename KeyT, typename ValueT, typename KeyInfoT, typename ValueInfoT>
static inline size_t
capacity_in_bytes(const DenseMap<KeyT, ValueT, KeyInfoT, ValueInfoT> &X) {
  return X.getMemorySize();
}

}


namespace llvm {


class MCRegisterClass {
public:
  typedef const unsigned* iterator;
  typedef const unsigned* const_iterator;
private:
  unsigned ID;
  const char *Name;
  const unsigned RegSize, Alignment;
  const int CopyCost;
  const bool Allocatable;
  const iterator RegsBegin, RegsEnd;
  const unsigned char *const RegSet;
  const unsigned RegSetSize;
public:
  MCRegisterClass(unsigned id, const char *name,
                  unsigned RS, unsigned Al, int CC, bool Allocable,
                  iterator RB, iterator RE, const unsigned char *Bits,
                  unsigned NumBytes)
    : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
      Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE), RegSet(Bits),
      RegSetSize(NumBytes) {
    for (iterator i = RegsBegin; i != RegsEnd; ++i)
       ((contains(*i) && "Bit field corrupted.") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCRegisterInfo.h", 47, "contains(*i) && \"Bit field corrupted.\""));
  }



  unsigned getID() const { return ID; }



  const char *getName() const { return Name; }



  iterator begin() const { return RegsBegin; }
  iterator end() const { return RegsEnd; }



  unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }



  unsigned getRegister(unsigned i) const {
    ((i < getNumRegs() && "Register number out of range!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCRegisterInfo.h", 70, "i < getNumRegs() && \"Register number out of range!\""));
    return RegsBegin[i];
  }



  bool contains(unsigned Reg) const {
    unsigned InByte = Reg % 8;
    unsigned Byte = Reg / 8;
    if (Byte >= RegSetSize)
      return false;
    return (RegSet[Byte] & (1 << InByte)) != 0;
  }


  bool contains(unsigned Reg1, unsigned Reg2) const {
    return contains(Reg1) && contains(Reg2);
  }



  unsigned getSize() const { return RegSize; }



  unsigned getAlignment() const { return Alignment; }




  int getCopyCost() const { return CopyCost; }



  bool isAllocatable() const { return Allocatable; }
};
struct MCRegisterDesc {
  const char *Name;
  const unsigned *Overlaps;
  const unsigned *SubRegs;
  const unsigned *SuperRegs;
};
class MCRegisterInfo {
public:
  typedef const MCRegisterClass *regclass_iterator;
private:
  const MCRegisterDesc *Desc;
  unsigned NumRegs;
  unsigned RAReg;
  const MCRegisterClass *Classes;
  unsigned NumClasses;
  DenseMap<unsigned, int> L2DwarfRegs;
  DenseMap<unsigned, int> EHL2DwarfRegs;
  DenseMap<unsigned, unsigned> Dwarf2LRegs;
  DenseMap<unsigned, unsigned> EHDwarf2LRegs;
  DenseMap<unsigned, int> L2SEHRegs;

public:


  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
                          const MCRegisterClass *C, unsigned NC) {
    Desc = D;
    NumRegs = NR;
    RAReg = RA;
    Classes = C;
    NumClasses = NC;
  }




  void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
    if (isEH)
      EHL2DwarfRegs[LLVMReg] = DwarfReg;
    else
      L2DwarfRegs[LLVMReg] = DwarfReg;
  }




  void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
    if (isEH)
      EHDwarf2LRegs[DwarfReg] = LLVMReg;
    else
      Dwarf2LRegs[DwarfReg] = LLVMReg;
  }






  void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
    L2SEHRegs[LLVMReg] = SEHReg;
  }



  unsigned getRARegister() const {
    return RAReg;
  }

  const MCRegisterDesc &operator[](unsigned RegNo) const {
    ((RegNo < NumRegs && "Attempting to access record for invalid register number!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCRegisterInfo.h", 200, "RegNo < NumRegs && \"Attempting to access record for invalid register number!\""));

    return Desc[RegNo];
  }




  const MCRegisterDesc &get(unsigned RegNo) const {
    return operator[](RegNo);
  }





  const unsigned *getAliasSet(unsigned RegNo) const {

    return get(RegNo).Overlaps + 1;
  }






  const unsigned *getOverlaps(unsigned RegNo) const {
    return get(RegNo).Overlaps;
  }






  const unsigned *getSubRegisters(unsigned RegNo) const {
    return get(RegNo).SubRegs;
  }






  const unsigned *getSuperRegisters(unsigned RegNo) const {
    return get(RegNo).SuperRegs;
  }



  const char *getName(unsigned RegNo) const {
    return get(RegNo).Name;
  }



  unsigned getNumRegs() const {
    return NumRegs;
  }





  int getDwarfRegNum(unsigned RegNum, bool isEH) const {
    const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
    const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
    if (I == M.end()) return -1;
    return I->second;
  }



  int getLLVMRegNum(unsigned RegNum, bool isEH) const {
    const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
    const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
    if (I == M.end()) {
      ((0 && "Invalid RegNum") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCRegisterInfo.h", 276, "0 && \"Invalid RegNum\""));
      return -1;
    }
    return I->second;
  }



  int getSEHRegNum(unsigned RegNum) const {
    const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
    if (I == L2SEHRegs.end()) return (int)RegNum;
    return I->second;
  }

  regclass_iterator regclass_begin() const { return Classes; }
  regclass_iterator regclass_end() const { return Classes+NumClasses; }

  unsigned getNumRegClasses() const {
    return (unsigned)(regclass_end()-regclass_begin());
  }



  const MCRegisterClass getRegClass(unsigned i) const {
    ((i < getNumRegClasses() && "Register Class ID out of range") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCRegisterInfo.h", 300, "i < getNumRegClasses() && \"Register Class ID out of range\""));
    return Classes[i];
  }
};

}


namespace llvm {

class BlockAddress;
class ConstantFP;
class ConstantInt;
class GlobalValue;
class MachineBasicBlock;
class MachineInstr;
class MachineRegisterInfo;
class MDNode;
class TargetMachine;
class TargetRegisterInfo;
class raw_ostream;
class MCSymbol;



class MachineOperand {
public:
  enum MachineOperandType {
    MO_Register,
    MO_Immediate,
    MO_CImmediate,
    MO_FPImmediate,
    MO_MachineBasicBlock,
    MO_FrameIndex,
    MO_ConstantPoolIndex,
    MO_JumpTableIndex,
    MO_ExternalSymbol,
    MO_GlobalAddress,
    MO_BlockAddress,
    MO_Metadata,
    MO_MCSymbol
  };

private:


  unsigned char OpKind;



  unsigned char SubReg;


  unsigned char TargetFlags;






  bool IsDef : 1;



  bool IsImp : 1;



  bool IsKill : 1;



  bool IsDead : 1;
  bool IsUndef : 1;




  bool IsEarlyClobber : 1;



  bool IsDebug : 1;





  union {
    unsigned RegNo;
    unsigned OffsetLo;
  } SmallContents;



  MachineInstr *ParentMI;


  union {
    MachineBasicBlock *MBB;
    const ConstantFP *CFP;
    const ConstantInt *CI;
    int64_t ImmVal;
    const MDNode *MD;
    MCSymbol *Sym;

    struct {

      MachineOperand **Prev;
      MachineOperand *Next;
    } Reg;



    struct {
      union {
        int Index;
        const char *SymbolName;
        const GlobalValue *GV;
        const BlockAddress *BA;
      } Val;

      int OffsetHi;
    } OffsetedInfo;
  } Contents;

  explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {
    TargetFlags = 0;
  }
public:


  MachineOperandType getType() const { return (MachineOperandType)OpKind; }

  unsigned char getTargetFlags() const { return TargetFlags; }
  void setTargetFlags(unsigned char F) { TargetFlags = F; }
  void addTargetFlag(unsigned char F) { TargetFlags |= F; }




  MachineInstr *getParent() { return ParentMI; }
  const MachineInstr *getParent() const { return ParentMI; }
  void clearParent() { ParentMI = 0; }

  void print(raw_ostream &os, const TargetMachine *TM = 0) const;






  bool isReg() const { return OpKind == MO_Register; }

  bool isImm() const { return OpKind == MO_Immediate; }

  bool isCImm() const { return OpKind == MO_CImmediate; }

  bool isFPImm() const { return OpKind == MO_FPImmediate; }

  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }

  bool isFI() const { return OpKind == MO_FrameIndex; }

  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }

  bool isJTI() const { return OpKind == MO_JumpTableIndex; }

  bool isGlobal() const { return OpKind == MO_GlobalAddress; }

  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }

  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }

  bool isMetadata() const { return OpKind == MO_Metadata; }
  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }






  unsigned getReg() const {
    ((isReg() && "This is not a register operand!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 222, "isReg() && \"This is not a register operand!\""));
    return SmallContents.RegNo;
  }

  unsigned getSubReg() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 227, "isReg() && \"Wrong MachineOperand accessor\""));
    return (unsigned)SubReg;
  }

  bool isUse() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 232, "isReg() && \"Wrong MachineOperand accessor\""));
    return !IsDef;
  }

  bool isDef() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 237, "isReg() && \"Wrong MachineOperand accessor\""));
    return IsDef;
  }

  bool isImplicit() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 242, "isReg() && \"Wrong MachineOperand accessor\""));
    return IsImp;
  }

  bool isDead() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 247, "isReg() && \"Wrong MachineOperand accessor\""));
    return IsDead;
  }

  bool isKill() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 252, "isReg() && \"Wrong MachineOperand accessor\""));
    return IsKill;
  }

  bool isUndef() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 257, "isReg() && \"Wrong MachineOperand accessor\""));
    return IsUndef;
  }

  bool isEarlyClobber() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 262, "isReg() && \"Wrong MachineOperand accessor\""));
    return IsEarlyClobber;
  }

  bool isDebug() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 267, "isReg() && \"Wrong MachineOperand accessor\""));
    return IsDebug;
  }





  bool readsReg() const {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 276, "isReg() && \"Wrong MachineOperand accessor\""));
    return !isUndef() && (isUse() || getSubReg());
  }



  MachineOperand *getNextOperandForReg() const {
    ((isReg() && "This is not a register operand!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 283, "isReg() && \"This is not a register operand!\""));
    return Contents.Reg.Next;
  }







  void setReg(unsigned Reg);

  void setSubReg(unsigned subReg) {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 296, "isReg() && \"Wrong MachineOperand accessor\""));
    SubReg = (unsigned char)subReg;
  }






  void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);





  void substPhysReg(unsigned Reg, const TargetRegisterInfo&);

  void setIsUse(bool Val = true) {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 314, "isReg() && \"Wrong MachineOperand accessor\""));
    (((Val || !isDebug()) && "Marking a debug operation as def") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 315, "(Val || !isDebug()) && \"Marking a debug operation as def\""));
    IsDef = !Val;
  }

  void setIsDef(bool Val = true) {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 320, "isReg() && \"Wrong MachineOperand accessor\""));
    (((!Val || !isDebug()) && "Marking a debug operation as def") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 321, "(!Val || !isDebug()) && \"Marking a debug operation as def\""));
    IsDef = Val;
  }

  void setImplicit(bool Val = true) {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 326, "isReg() && \"Wrong MachineOperand accessor\""));
    IsImp = Val;
  }

  void setIsKill(bool Val = true) {
    ((isReg() && !IsDef && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 331, "isReg() && !IsDef && \"Wrong MachineOperand accessor\""));
    (((!Val || !isDebug()) && "Marking a debug operation as kill") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 332, "(!Val || !isDebug()) && \"Marking a debug operation as kill\""));
    IsKill = Val;
  }

  void setIsDead(bool Val = true) {
    ((isReg() && IsDef && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 337, "isReg() && IsDef && \"Wrong MachineOperand accessor\""));
    IsDead = Val;
  }

  void setIsUndef(bool Val = true) {
    ((isReg() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 342, "isReg() && \"Wrong MachineOperand accessor\""));
    IsUndef = Val;
  }

  void setIsEarlyClobber(bool Val = true) {
    ((isReg() && IsDef && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 347, "isReg() && IsDef && \"Wrong MachineOperand accessor\""));
    IsEarlyClobber = Val;
  }

  void setIsDebug(bool Val = true) {
    ((isReg() && IsDef && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 352, "isReg() && IsDef && \"Wrong MachineOperand accessor\""));
    IsDebug = Val;
  }





  int64_t getImm() const {
    ((isImm() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 361, "isImm() && \"Wrong MachineOperand accessor\""));
    return Contents.ImmVal;
  }

  const ConstantInt *getCImm() const {
    ((isCImm() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 366, "isCImm() && \"Wrong MachineOperand accessor\""));
    return Contents.CI;
  }

  const ConstantFP *getFPImm() const {
    ((isFPImm() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 371, "isFPImm() && \"Wrong MachineOperand accessor\""));
    return Contents.CFP;
  }

  MachineBasicBlock *getMBB() const {
    ((isMBB() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 376, "isMBB() && \"Wrong MachineOperand accessor\""));
    return Contents.MBB;
  }

  int getIndex() const {
    (((isFI() || isCPI() || isJTI()) && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 382, "(isFI() || isCPI() || isJTI()) && \"Wrong MachineOperand accessor\""));

    return Contents.OffsetedInfo.Val.Index;
  }

  const GlobalValue *getGlobal() const {
    ((isGlobal() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 387, "isGlobal() && \"Wrong MachineOperand accessor\""));
    return Contents.OffsetedInfo.Val.GV;
  }

  const BlockAddress *getBlockAddress() const {
    ((isBlockAddress() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 392, "isBlockAddress() && \"Wrong MachineOperand accessor\""));
    return Contents.OffsetedInfo.Val.BA;
  }

  MCSymbol *getMCSymbol() const {
    ((isMCSymbol() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 397, "isMCSymbol() && \"Wrong MachineOperand accessor\""));
    return Contents.Sym;
  }



  int64_t getOffset() const {
    (((isGlobal() || isSymbol() || isCPI() || isBlockAddress()) && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 405, "(isGlobal() || isSymbol() || isCPI() || isBlockAddress()) && \"Wrong MachineOperand accessor\""));

    return (int64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
           SmallContents.OffsetLo;
  }

  const char *getSymbolName() const {
    ((isSymbol() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 411, "isSymbol() && \"Wrong MachineOperand accessor\""));
    return Contents.OffsetedInfo.Val.SymbolName;
  }

  const MDNode *getMetadata() const {
    ((isMetadata() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 416, "isMetadata() && \"Wrong MachineOperand accessor\""));
    return Contents.MD;
  }





  void setImm(int64_t immVal) {
    ((isImm() && "Wrong MachineOperand mutator") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 425, "isImm() && \"Wrong MachineOperand mutator\""));
    Contents.ImmVal = immVal;
  }

  void setOffset(int64_t Offset) {
    (((isGlobal() || isSymbol() || isCPI() || isBlockAddress()) && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 431, "(isGlobal() || isSymbol() || isCPI() || isBlockAddress()) && \"Wrong MachineOperand accessor\""));

    SmallContents.OffsetLo = unsigned(Offset);
    Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
  }

  void setIndex(int Idx) {
    (((isFI() || isCPI() || isJTI()) && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 438, "(isFI() || isCPI() || isJTI()) && \"Wrong MachineOperand accessor\""));

    Contents.OffsetedInfo.Val.Index = Idx;
  }

  void setMBB(MachineBasicBlock *MBB) {
    ((isMBB() && "Wrong MachineOperand accessor") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 443, "isMBB() && \"Wrong MachineOperand accessor\""));
    Contents.MBB = MBB;
  }







  bool isIdenticalTo(const MachineOperand &Other) const;




  void ChangeToImmediate(int64_t ImmVal);




  void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
                        bool isKill = false, bool isDead = false,
                        bool isUndef = false, bool isDebug = false);





  static MachineOperand CreateImm(int64_t Val) {
    MachineOperand Op(MachineOperand::MO_Immediate);
    Op.setImm(Val);
    return Op;
  }

  static MachineOperand CreateCImm(const ConstantInt *CI) {
    MachineOperand Op(MachineOperand::MO_CImmediate);
    Op.Contents.CI = CI;
    return Op;
  }

  static MachineOperand CreateFPImm(const ConstantFP *CFP) {
    MachineOperand Op(MachineOperand::MO_FPImmediate);
    Op.Contents.CFP = CFP;
    return Op;
  }

  static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
                                  bool isKill = false, bool isDead = false,
                                  bool isUndef = false,
                                  bool isEarlyClobber = false,
                                  unsigned SubReg = 0,
                                  bool isDebug = false) {
    MachineOperand Op(MachineOperand::MO_Register);
    Op.IsDef = isDef;
    Op.IsImp = isImp;
    Op.IsKill = isKill;
    Op.IsDead = isDead;
    Op.IsUndef = isUndef;
    Op.IsEarlyClobber = isEarlyClobber;
    Op.IsDebug = isDebug;
    Op.SmallContents.RegNo = Reg;
    Op.Contents.Reg.Prev = 0;
    Op.Contents.Reg.Next = 0;
    Op.SubReg = SubReg;
    return Op;
  }
  static MachineOperand CreateMBB(MachineBasicBlock *MBB,
                                  unsigned char TargetFlags = 0) {
    MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
    Op.setMBB(MBB);
    Op.setTargetFlags(TargetFlags);
    return Op;
  }
  static MachineOperand CreateFI(int Idx) {
    MachineOperand Op(MachineOperand::MO_FrameIndex);
    Op.setIndex(Idx);
    return Op;
  }
  static MachineOperand CreateCPI(unsigned Idx, int Offset,
                                  unsigned char TargetFlags = 0) {
    MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
    Op.setIndex(Idx);
    Op.setOffset(Offset);
    Op.setTargetFlags(TargetFlags);
    return Op;
  }
  static MachineOperand CreateJTI(unsigned Idx,
                                  unsigned char TargetFlags = 0) {
    MachineOperand Op(MachineOperand::MO_JumpTableIndex);
    Op.setIndex(Idx);
    Op.setTargetFlags(TargetFlags);
    return Op;
  }
  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
                                 unsigned char TargetFlags = 0) {
    MachineOperand Op(MachineOperand::MO_GlobalAddress);
    Op.Contents.OffsetedInfo.Val.GV = GV;
    Op.setOffset(Offset);
    Op.setTargetFlags(TargetFlags);
    return Op;
  }
  static MachineOperand CreateES(const char *SymName,
                                 unsigned char TargetFlags = 0) {
    MachineOperand Op(MachineOperand::MO_ExternalSymbol);
    Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
    Op.setOffset(0);
    Op.setTargetFlags(TargetFlags);
    return Op;
  }
  static MachineOperand CreateBA(const BlockAddress *BA,
                                 unsigned char TargetFlags = 0) {
    MachineOperand Op(MachineOperand::MO_BlockAddress);
    Op.Contents.OffsetedInfo.Val.BA = BA;
    Op.setOffset(0);
    Op.setTargetFlags(TargetFlags);
    return Op;
  }
  static MachineOperand CreateMetadata(const MDNode *Meta) {
    MachineOperand Op(MachineOperand::MO_Metadata);
    Op.Contents.MD = Meta;
    return Op;
  }

  static MachineOperand CreateMCSymbol(MCSymbol *Sym) {
    MachineOperand Op(MachineOperand::MO_MCSymbol);
    Op.Contents.Sym = Sym;
    return Op;
  }

  friend class MachineInstr;
  friend class MachineRegisterInfo;
private:







  bool isOnRegUseList() const {
    ((isReg() && "Can only add reg operand to use lists") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineOperand.h", 583, "isReg() && \"Can only add reg operand to use lists\""));
    return Contents.Reg.Prev != 0;
  }




  void AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo);



  void RemoveRegOperandFromRegInfo();
};

inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
  MO.print(OS, 0);
  return OS;
}

}
namespace llvm {





namespace MCOI {

  enum OperandConstraint {
    TIED_TO = 0,
    EARLY_CLOBBER
  };




  enum OperandFlags {
    LookupPtrRegClass = 0,
    Predicate,
    OptionalDef
  };


  enum OperandType {
    OPERAND_UNKNOWN,
    OPERAND_IMMEDIATE,
    OPERAND_REGISTER,
    OPERAND_MEMORY,
    OPERAND_PCREL
  };
}




class MCOperandInfo {
public:




  short RegClass;


  unsigned short Flags;



  unsigned Constraints;


  MCOI::OperandType OperandType;




  bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}



  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }



  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
};
namespace MCID {
  enum {
    Variadic = 0,
    HasOptionalDef,
    Pseudo,
    Return,
    Call,
    Barrier,
    Terminator,
    Branch,
    IndirectBranch,
    Compare,
    MoveImm,
    Bitcast,
    DelaySlot,
    FoldableAsLoad,
    MayLoad,
    MayStore,
    Predicable,
    NotDuplicable,
    UnmodeledSideEffects,
    Commutable,
    ConvertibleTo3Addr,
    UsesCustomInserter,
    HasPostISelHook,
    Rematerializable,
    CheapAsAMove,
    ExtraSrcRegAllocReq,
    ExtraDefRegAllocReq
  };
}






class MCInstrDesc {
public:
  unsigned short Opcode;
  unsigned short NumOperands;
  unsigned short NumDefs;
  unsigned short SchedClass;
  unsigned short Size;
  const char * Name;
  unsigned Flags;
  uint64_t TSFlags;
  const unsigned *ImplicitUses;
  const unsigned *ImplicitDefs;
  const MCOperandInfo *OpInfo;



  int getOperandConstraint(unsigned OpNum,
                           MCOI::OperandConstraint Constraint) const {
    if (OpNum < NumOperands &&
        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
      unsigned Pos = 16 + Constraint * 4;
      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
    }
    return -1;
  }


  unsigned getOpcode() const {
    return Opcode;
  }



  const char *getName() const {
    return Name;
  }






  unsigned getNumOperands() const {
    return NumOperands;
  }





  unsigned getNumDefs() const {
    return NumDefs;
  }





  bool isVariadic() const {
    return Flags & (1 << MCID::Variadic);
  }



  bool hasOptionalDef() const {
    return Flags & (1 << MCID::HasOptionalDef);
  }
  const unsigned *getImplicitUses() const {
    return ImplicitUses;
  }



  unsigned getNumImplicitUses() const {
    if (ImplicitUses == 0) return 0;
    unsigned i = 0;
    for (; ImplicitUses[i]; ++i) ;
    return i;
  }
  const unsigned *getImplicitDefs() const {
    return ImplicitDefs;
  }



  unsigned getNumImplicitDefs() const {
    if (ImplicitDefs == 0) return 0;
    unsigned i = 0;
    for (; ImplicitDefs[i]; ++i) ;
    return i;
  }



  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
    if (const unsigned *ImpUses = ImplicitUses)
      for (; *ImpUses; ++ImpUses)
        if (*ImpUses == Reg) return true;
    return false;
  }



  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
    if (const unsigned *ImpDefs = ImplicitDefs)
      for (; *ImpDefs; ++ImpDefs)
        if (*ImpDefs == Reg) return true;
    return false;
  }






  unsigned getSchedClass() const {
    return SchedClass;
  }



  unsigned getSize() const {
    return Size;
  }




  bool isPseudo() const {
    return Flags & (1 << MCID::Pseudo);
  }

  bool isReturn() const {
    return Flags & (1 << MCID::Return);
  }

  bool isCall() const {
    return Flags & (1 << MCID::Call);
  }




  bool isBarrier() const {
    return Flags & (1 << MCID::Barrier);
  }




  int findFirstPredOperandIdx() const {
    if (isPredicable()) {
      for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
        if (OpInfo[i].isPredicate())
          return i;
    }
    return -1;
  }







  bool isTerminator() const {
    return Flags & (1 << MCID::Terminator);
  }





  bool isBranch() const {
    return Flags & (1 << MCID::Branch);
  }



  bool isIndirectBranch() const {
    return Flags & (1 << MCID::IndirectBranch);
  }





  bool isConditionalBranch() const {
    return isBranch() & !isBarrier() & !isIndirectBranch();
  }





  bool isUnconditionalBranch() const {
    return isBranch() & isBarrier() & !isIndirectBranch();
  }





  bool isPredicable() const {
    return Flags & (1 << MCID::Predicable);
  }


  bool isCompare() const {
    return Flags & (1 << MCID::Compare);
  }



  bool isMoveImmediate() const {
    return Flags & (1 << MCID::MoveImm);
  }



  bool isBitcast() const {
    return Flags & (1 << MCID::Bitcast);
  }




  bool isNotDuplicable() const {
    return Flags & (1 << MCID::NotDuplicable);
  }



  bool hasDelaySlot() const {
    return Flags & (1 << MCID::DelaySlot);
  }
  bool canFoldAsLoad() const {
    return Flags & (1 << MCID::FoldableAsLoad);
  }
  bool mayLoad() const {
    return Flags & (1 << MCID::MayLoad);
  }






  bool mayStore() const {
    return Flags & (1 << MCID::MayStore);
  }
  bool hasUnmodeledSideEffects() const {
    return Flags & (1 << MCID::UnmodeledSideEffects);
  }
  bool isCommutable() const {
    return Flags & (1 << MCID::Commutable);
  }
  bool isConvertibleTo3Addr() const {
    return Flags & (1 << MCID::ConvertibleTo3Addr);
  }
  bool usesCustomInsertionHook() const {
    return Flags & (1 << MCID::UsesCustomInserter);
  }





  bool hasPostISelHook() const {
    return Flags & (1 << MCID::HasPostISelHook);
  }





  bool isRematerializable() const {
    return Flags & (1 << MCID::Rematerializable);
  }







  bool isAsCheapAsAMove() const {
    return Flags & (1 << MCID::CheapAsAMove);
  }







  bool hasExtraSrcRegAllocReq() const {
    return Flags & (1 << MCID::ExtraSrcRegAllocReq);
  }







  bool hasExtraDefRegAllocReq() const {
    return Flags & (1 << MCID::ExtraDefRegAllocReq);
  }
};

}
namespace llvm {






namespace TargetOpcode {
  enum {
    PHI = 0,
    INLINEASM = 1,
    PROLOG_LABEL = 2,
    EH_LABEL = 3,
    GC_LABEL = 4,




    KILL = 5,





    EXTRACT_SUBREG = 6,







    INSERT_SUBREG = 7,


    IMPLICIT_DEF = 8,





    SUBREG_TO_REG = 9,







    COPY_TO_REGCLASS = 10,


    DBG_VALUE = 11,
    REG_SEQUENCE = 12,



    COPY = 13
  };
}
}




namespace llvm {

template<typename NodeTy, typename Traits> class iplist;
template<typename NodeTy> class ilist_iterator;




template<typename NodeTy>
struct ilist_nextprev_traits {
  static NodeTy *getPrev(NodeTy *N) { return N->getPrev(); }
  static NodeTy *getNext(NodeTy *N) { return N->getNext(); }
  static const NodeTy *getPrev(const NodeTy *N) { return N->getPrev(); }
  static const NodeTy *getNext(const NodeTy *N) { return N->getNext(); }

  static void setPrev(NodeTy *N, NodeTy *Prev) { N->setPrev(Prev); }
  static void setNext(NodeTy *N, NodeTy *Next) { N->setNext(Next); }
};

template<typename NodeTy>
struct ilist_traits;







template<typename NodeTy>
struct ilist_sentinel_traits {

  static NodeTy *createSentinel() { return new NodeTy(); }


  static void destroySentinel(NodeTy *N) { delete N; }




  static NodeTy *provideInitialHead() { return 0; }




  static NodeTy *ensureHead(NodeTy *&Head) {
    if (!Head) {
      Head = ilist_traits<NodeTy>::createSentinel();
      ilist_traits<NodeTy>::noteHead(Head, Head);
      ilist_traits<NodeTy>::setNext(Head, 0);
      return Head;
    }
    return ilist_traits<NodeTy>::getPrev(Head);
  }


  static void noteHead(NodeTy *NewHead, NodeTy *Sentinel) {
    ilist_traits<NodeTy>::setPrev(NewHead, Sentinel);
  }
};




template<typename NodeTy>
struct ilist_node_traits {
  static NodeTy *createNode(const NodeTy &V) { return new NodeTy(V); }
  static void deleteNode(NodeTy *V) { delete V; }

  void addNodeToList(NodeTy *) {}
  void removeNodeFromList(NodeTy *) {}
  void transferNodesFromList(ilist_node_traits & ,
                             ilist_iterator<NodeTy> ,
                             ilist_iterator<NodeTy> ) {}
};





template<typename NodeTy>
struct ilist_default_traits : public ilist_nextprev_traits<NodeTy>,
                              public ilist_sentinel_traits<NodeTy>,
                              public ilist_node_traits<NodeTy> {
};



template<typename NodeTy>
struct ilist_traits : public ilist_default_traits<NodeTy> {};


template<typename Ty>
struct ilist_traits<const Ty> : public ilist_traits<Ty> {};




template<typename NodeTy>
class ilist_iterator
  : public std::iterator<std::bidirectional_iterator_tag, NodeTy, ptrdiff_t> {

public:
  typedef ilist_traits<NodeTy> Traits;
  typedef std::iterator<std::bidirectional_iterator_tag,
                        NodeTy, ptrdiff_t> super;

  typedef typename super::value_type value_type;
  typedef typename super::difference_type difference_type;
  typedef typename super::pointer pointer;
  typedef typename super::reference reference;
private:
  pointer NodePtr;





  void operator[](difference_type) const;
  void operator+(difference_type) const;
  void operator-(difference_type) const;
  void operator+=(difference_type) const;
  void operator-=(difference_type) const;
  template<class T> void operator<(T) const;
  template<class T> void operator<=(T) const;
  template<class T> void operator>(T) const;
  template<class T> void operator>=(T) const;
  template<class T> void operator-(T) const;
public:

  ilist_iterator(pointer NP) : NodePtr(NP) {}
  ilist_iterator(reference NR) : NodePtr(&NR) {}
  ilist_iterator() : NodePtr(0) {}



  template<class node_ty>
  ilist_iterator(const ilist_iterator<node_ty> &RHS)
    : NodePtr(RHS.getNodePtrUnchecked()) {}



  template<class node_ty>
  const ilist_iterator &operator=(const ilist_iterator<node_ty> &RHS) {
    NodePtr = RHS.getNodePtrUnchecked();
    return *this;
  }


  operator pointer() const {
    return NodePtr;
  }

  reference operator*() const {
    return *NodePtr;
  }
  pointer operator->() const { return &operator*(); }


  bool operator==(const ilist_iterator &RHS) const {
    return NodePtr == RHS.NodePtr;
  }
  bool operator!=(const ilist_iterator &RHS) const {
    return NodePtr != RHS.NodePtr;
  }


  ilist_iterator &operator--() {
    NodePtr = Traits::getPrev(NodePtr);
    ((NodePtr && "--'d off the beginning of an ilist!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 214, "NodePtr && \"--'d off the beginning of an ilist!\""));
    return *this;
  }
  ilist_iterator &operator++() {
    NodePtr = Traits::getNext(NodePtr);
    return *this;
  }
  ilist_iterator operator--(int) {
    ilist_iterator tmp = *this;
    --*this;
    return tmp;
  }
  ilist_iterator operator++(int) {
    ilist_iterator tmp = *this;
    ++*this;
    return tmp;
  }


  pointer getNodePtrUnchecked() const { return NodePtr; }
};



template<typename T>
void operator-(int, ilist_iterator<T>);
template<typename T>
void operator-(ilist_iterator<T>,int);

template<typename T>
void operator+(int, ilist_iterator<T>);
template<typename T>
void operator+(ilist_iterator<T>,int);



template<typename T>
bool operator!=(const T* LHS, const ilist_iterator<const T> &RHS) {
  return LHS != RHS.getNodePtrUnchecked();
}
template<typename T>
bool operator==(const T* LHS, const ilist_iterator<const T> &RHS) {
  return LHS == RHS.getNodePtrUnchecked();
}
template<typename T>
bool operator!=(T* LHS, const ilist_iterator<T> &RHS) {
  return LHS != RHS.getNodePtrUnchecked();
}
template<typename T>
bool operator==(T* LHS, const ilist_iterator<T> &RHS) {
  return LHS == RHS.getNodePtrUnchecked();
}





template<typename From> struct simplify_type;

template<typename NodeTy> struct simplify_type<ilist_iterator<NodeTy> > {
  typedef NodeTy* SimpleType;

  static SimpleType getSimplifiedValue(const ilist_iterator<NodeTy> &Node) {
    return &*Node;
  }
};
template<typename NodeTy> struct simplify_type<const ilist_iterator<NodeTy> > {
  typedef NodeTy* SimpleType;

  static SimpleType getSimplifiedValue(const ilist_iterator<NodeTy> &Node) {
    return &*Node;
  }
};
template<typename NodeTy, typename Traits=ilist_traits<NodeTy> >
class iplist : public Traits {
  mutable NodeTy *Head;





  NodeTy *getTail() { return this->ensureHead(Head); }
  const NodeTy *getTail() const { return this->ensureHead(Head); }
  void setTail(NodeTy *N) const { this->noteHead(Head, N); }



  void CreateLazySentinel() const {
    this->ensureHead(Head);
  }

  static bool op_less(NodeTy &L, NodeTy &R) { return L < R; }
  static bool op_equal(NodeTy &L, NodeTy &R) { return L == R; }



  iplist(const iplist &);
  void operator=(const iplist &);

public:
  typedef NodeTy *pointer;
  typedef const NodeTy *const_pointer;
  typedef NodeTy &reference;
  typedef const NodeTy &const_reference;
  typedef NodeTy value_type;
  typedef ilist_iterator<NodeTy> iterator;
  typedef ilist_iterator<const NodeTy> const_iterator;
  typedef size_t size_type;
  typedef ptrdiff_t difference_type;
  typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
  typedef std::reverse_iterator<iterator> reverse_iterator;

  iplist() : Head(this->provideInitialHead()) {}
  ~iplist() {
    if (!Head) return;
    clear();
    Traits::destroySentinel(getTail());
  }


  iterator begin() {
    CreateLazySentinel();
    return iterator(Head);
  }
  const_iterator begin() const {
    CreateLazySentinel();
    return const_iterator(Head);
  }
  iterator end() {
    CreateLazySentinel();
    return iterator(getTail());
  }
  const_iterator end() const {
    CreateLazySentinel();
    return const_iterator(getTail());
  }


  reverse_iterator rbegin() { return reverse_iterator(end()); }
  const_reverse_iterator rbegin() const{ return const_reverse_iterator(end()); }
  reverse_iterator rend() { return reverse_iterator(begin()); }
  const_reverse_iterator rend() const { return const_reverse_iterator(begin());}



  size_type max_size() const { return size_type(-1); }
  bool empty() const { return Head == 0 || Head == getTail(); }


  reference front() {
    ((!empty() && "Called front() on empty list!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 388, "!empty() && \"Called front() on empty list!\""));
    return *Head;
  }
  const_reference front() const {
    ((!empty() && "Called front() on empty list!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 392, "!empty() && \"Called front() on empty list!\""));
    return *Head;
  }
  reference back() {
    ((!empty() && "Called back() on empty list!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 396, "!empty() && \"Called back() on empty list!\""));
    return *this->getPrev(getTail());
  }
  const_reference back() const {
    ((!empty() && "Called back() on empty list!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 400, "!empty() && \"Called back() on empty list!\""));
    return *this->getPrev(getTail());
  }

  void swap(iplist &RHS) {
    ((0 && "Swap does not use list traits callback correctly yet!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 405, "0 && \"Swap does not use list traits callback correctly yet!\""));
    std::swap(Head, RHS.Head);
  }

  iterator insert(iterator where, NodeTy *New) {
    NodeTy *CurNode = where.getNodePtrUnchecked();
    NodeTy *PrevNode = this->getPrev(CurNode);
    this->setNext(New, CurNode);
    this->setPrev(New, PrevNode);

    if (CurNode != Head)
      this->setNext(PrevNode, New);
    else
      Head = New;
    this->setPrev(CurNode, New);

    this->addNodeToList(New);
    return New;
  }

  iterator insertAfter(iterator where, NodeTy *New) {
    if (empty())
      return insert(begin(), New);
    else
      return insert(++where, New);
  }

  NodeTy *remove(iterator &IT) {
    ((IT != end() && "Cannot remove end of list!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 433, "IT != end() && \"Cannot remove end of list!\""));
    NodeTy *Node = &*IT;
    NodeTy *NextNode = this->getNext(Node);
    NodeTy *PrevNode = this->getPrev(Node);

    if (Node != Head)
      this->setNext(PrevNode, NextNode);
    else
      Head = NextNode;
    this->setPrev(NextNode, PrevNode);
    IT = NextNode;
    this->removeNodeFromList(Node);






    this->setNext(Node, 0);
    this->setPrev(Node, 0);
    return Node;
  }

  NodeTy *remove(const iterator &IT) {
    iterator MutIt = IT;
    return remove(MutIt);
  }


  iterator erase(iterator where) {
    this->deleteNode(remove(where));
    return where;
  }


private:



  void transfer(iterator position, iplist &L2, iterator first, iterator last) {
    ((first != last && "Should be checked by callers") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 473, "first != last && \"Should be checked by callers\""));

    if (position != last) {


      NodeTy *ThisSentinel = getTail();
      setTail(0);
      NodeTy *L2Sentinel = L2.getTail();
      L2.setTail(0);


      NodeTy *First = &*first, *Prev = this->getPrev(First);
      NodeTy *Next = last.getNodePtrUnchecked(), *Last = this->getPrev(Next);
      if (Prev)
        this->setNext(Prev, Next);
      else
        L2.Head = Next;
      this->setPrev(Next, Prev);


      NodeTy *PosNext = position.getNodePtrUnchecked();
      NodeTy *PosPrev = this->getPrev(PosNext);


      if (PosPrev)
        this->setNext(PosPrev, First);
      else
        Head = First;
      this->setPrev(First, PosPrev);


      this->setNext(Last, PosNext);
      this->setPrev(PosNext, Last);

      this->transferNodesFromList(L2, First, PosNext);


      L2.setTail(L2Sentinel);
      setTail(ThisSentinel);
    }
  }

public:





  size_type size() const {
    if (Head == 0) return 0;
    return std::distance(begin(), end());
  }

  iterator erase(iterator first, iterator last) {
    while (first != last)
      first = erase(first);
    return last;
  }

  void clear() { if (Head) erase(begin(), end()); }


  void push_front(NodeTy *val) { insert(begin(), val); }
  void push_back(NodeTy *val) { insert(end(), val); }
  void pop_front() {
    ((!empty() && "pop_front() on empty list!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 538, "!empty() && \"pop_front() on empty list!\""));
    erase(begin());
  }
  void pop_back() {
    ((!empty() && "pop_back() on empty list!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ilist.h", 542, "!empty() && \"pop_back() on empty list!\""));
    iterator t = end(); erase(--t);
  }


  template<class InIt> void insert(iterator where, InIt first, InIt last) {
    for (; first != last; ++first) insert(where, *first);
  }


  void splice(iterator where, iplist &L2) {
    if (!L2.empty())
      transfer(where, L2, L2.begin(), L2.end());
  }
  void splice(iterator where, iplist &L2, iterator first) {
    iterator last = first; ++last;
    if (where == first || where == last) return;
    transfer(where, L2, first, last);
  }
  void splice(iterator where, iplist &L2, iterator first, iterator last) {
    if (first != last) transfer(where, L2, first, last);
  }
  void erase(const NodeTy &val) {
    for (iterator I = begin(), E = end(); I != E; ) {
      iterator next = I; ++next;
      if (*I == val) erase(I);
      I = next;
    }
  }
  template<class Pr1> void erase_if(Pr1 pred) {
    for (iterator I = begin(), E = end(); I != E; ) {
      iterator next = I; ++next;
      if (pred(*I)) erase(I);
      I = next;
    }
  }

  template<class Pr2> void unique(Pr2 pred) {
    if (empty()) return;
    for (iterator I = begin(), E = end(), Next = begin(); ++Next != E;) {
      if (pred(*I))
        erase(Next);
      else
        I = Next;
      Next = I;
    }
  }
  void unique() { unique(op_equal); }

  template<class Pr3> void merge(iplist &right, Pr3 pred) {
    iterator first1 = begin(), last1 = end();
    iterator first2 = right.begin(), last2 = right.end();
    while (first1 != last1 && first2 != last2)
      if (pred(*first2, *first1)) {
        iterator next = first2;
        transfer(first1, right, first2, ++next);
        first2 = next;
      } else {
        ++first1;
      }
    if (first2 != last2) transfer(last1, right, first2, last2);
  }
  void merge(iplist &right) { return merge(right, op_less); }

  template<class Pr3> void sort(Pr3 pred);
  void sort() { sort(op_less); }
};


template<typename NodeTy>
struct ilist : public iplist<NodeTy> {
  typedef typename iplist<NodeTy>::size_type size_type;
  typedef typename iplist<NodeTy>::iterator iterator;

  ilist() {}
  ilist(const ilist &right) {
    insert(this->begin(), right.begin(), right.end());
  }
  explicit ilist(size_type count) {
    insert(this->begin(), count, NodeTy());
  }
  ilist(size_type count, const NodeTy &val) {
    insert(this->begin(), count, val);
  }
  template<class InIt> ilist(InIt first, InIt last) {
    insert(this->begin(), first, last);
  }


  using iplist<NodeTy>::insert;
  using iplist<NodeTy>::push_front;
  using iplist<NodeTy>::push_back;


  iterator insert(iterator where, const NodeTy &val) {
    return insert(where, this->createNode(val));
  }



  void push_front(const NodeTy &val) { insert(this->begin(), val); }
  void push_back(const NodeTy &val) { insert(this->end(), val); }


  template<class InIt> void insert(iterator where, InIt first, InIt last) {
    for (; first != last; ++first) insert(where, *first);
  }
  void insert(iterator where, size_type count, const NodeTy &val) {
    for (; count != 0; --count) insert(where, val);
  }


  void assign(size_type count, const NodeTy &val) {
    iterator I = this->begin();
    for (; I != this->end() && count != 0; ++I, --count)
      *I = val;
    if (count != 0)
      insert(this->end(), val, val);
    else
      erase(I, this->end());
  }
  template<class InIt> void assign(InIt first1, InIt last1) {
    iterator first2 = this->begin(), last2 = this->end();
    for ( ; first1 != last1 && first2 != last2; ++first1, ++first2)
      *first1 = *first2;
    if (first2 == last2)
      erase(first1, last1);
    else
      insert(last1, first2, last2);
  }



  void resize(size_type newsize, NodeTy val) {
    iterator i = this->begin();
    size_type len = 0;
    for ( ; i != this->end() && len < newsize; ++i, ++len) ;

    if (len == newsize)
      erase(i, this->end());
    else
      insert(this->end(), newsize - len, val);
  }
  void resize(size_type newsize) { resize(newsize, NodeTy()); }
};

}

namespace std {

  template<class Ty>
  void swap(llvm::iplist<Ty> &Left, llvm::iplist<Ty> &Right) {
    Left.swap(Right);
  }
}
namespace llvm {

template<typename NodeTy>
struct ilist_traits;



template<typename NodeTy>
class ilist_half_node {
  friend struct ilist_traits<NodeTy>;
  NodeTy *Prev;
protected:
  NodeTy *getPrev() { return Prev; }
  const NodeTy *getPrev() const { return Prev; }
  void setPrev(NodeTy *P) { Prev = P; }
  ilist_half_node() : Prev(0) {}
};

template<typename NodeTy>
struct ilist_nextprev_traits;




template<typename NodeTy>
class ilist_node : private ilist_half_node<NodeTy> {
  friend struct ilist_nextprev_traits<NodeTy>;
  friend struct ilist_traits<NodeTy>;
  NodeTy *Next;
  NodeTy *getNext() { return Next; }
  const NodeTy *getNext() const { return Next; }
  void setNext(NodeTy *N) { Next = N; }
protected:
  ilist_node() : Next(0) {}

public:




  NodeTy *getPrevNode() {
    NodeTy *Prev = this->getPrev();


    if (!Prev->getNext())
      return 0;

    return Prev;
  }


  const NodeTy *getPrevNode() const {
    const NodeTy *Prev = this->getPrev();


    if (!Prev->getNext())
      return 0;

    return Prev;
  }


  NodeTy *getNextNode() {
    NodeTy *Next = getNext();


    if (!Next->getNext())
      return 0;

    return Next;
  }


  const NodeTy *getNextNode() const {
    const NodeTy *Next = getNext();


    if (!Next->getNext())
      return 0;

    return Next;
  }


};

}



namespace llvm {





template<class Ty>
struct less_ptr : public std::binary_function<Ty, Ty, bool> {
  bool operator()(const Ty* left, const Ty* right) const {
    return *left < *right;
  }
};

template<class Ty>
struct greater_ptr : public std::binary_function<Ty, Ty, bool> {
  bool operator()(const Ty* left, const Ty* right) const {
    return *right < *left;
  }
};






template <class T>
static inline void deleter(T *Ptr) {
  delete Ptr;
}
template <class RootIt, class UnaryFunc>
class mapped_iterator {
  RootIt current;
  UnaryFunc Fn;
public:
  typedef typename std::iterator_traits<RootIt>::iterator_category
          iterator_category;
  typedef typename std::iterator_traits<RootIt>::difference_type
          difference_type;
  typedef typename UnaryFunc::result_type value_type;

  typedef void pointer;

  typedef void reference;

  typedef RootIt iterator_type;
  typedef mapped_iterator<RootIt, UnaryFunc> _Self;

  inline const RootIt &getCurrent() const { return current; }
  inline const UnaryFunc &getFunc() const { return Fn; }

  inline explicit mapped_iterator(const RootIt &I, UnaryFunc F)
    : current(I), Fn(F) {}
  inline mapped_iterator(const mapped_iterator &It)
    : current(It.current), Fn(It.Fn) {}

  inline value_type operator*() const {
    return Fn(*current);
  }

  _Self& operator++() { ++current; return *this; }
  _Self& operator--() { --current; return *this; }
  _Self operator++(int) { _Self __tmp = *this; ++current; return __tmp; }
  _Self operator--(int) { _Self __tmp = *this; --current; return __tmp; }
  _Self operator+ (difference_type n) const {
    return _Self(current + n, Fn);
  }
  _Self& operator+= (difference_type n) { current += n; return *this; }
  _Self operator- (difference_type n) const {
    return _Self(current - n, Fn);
  }
  _Self& operator-= (difference_type n) { current -= n; return *this; }
  reference operator[](difference_type n) const { return *(*this + n); }

  inline bool operator!=(const _Self &X) const { return !operator==(X); }
  inline bool operator==(const _Self &X) const { return current == X.current; }
  inline bool operator< (const _Self &X) const { return current < X.current; }

  inline difference_type operator-(const _Self &X) const {
    return current - X.current;
  }
};

template <class _Iterator, class Func>
inline mapped_iterator<_Iterator, Func>
operator+(typename mapped_iterator<_Iterator, Func>::difference_type N,
          const mapped_iterator<_Iterator, Func>& X) {
  return mapped_iterator<_Iterator, Func>(X.getCurrent() - N, X.getFunc());
}





template <class ItTy, class FuncTy>
inline mapped_iterator<ItTy, FuncTy> map_iterator(const ItTy &I, FuncTy F) {
  return mapped_iterator<ItTy, FuncTy>(I, F);
}
template <typename ItTy, typename Dist>
inline ItTy next(ItTy it, Dist n)
{
  std::advance(it, n);
  return it;
}

template <typename ItTy>
inline ItTy next(ItTy it)
{
  return ++it;
}

template <typename ItTy, typename Dist>
inline ItTy prior(ItTy it, Dist n)
{
  std::advance(it, -n);
  return it;
}

template <typename ItTy>
inline ItTy prior(ItTy it)
{
  return --it;
}
template <typename T1, typename T2>
struct tier {
  typedef T1 &first_type;
  typedef T2 &second_type;

  first_type first;
  second_type second;

  tier(first_type f, second_type s) : first(f), second(s) { }
  tier& operator=(const std::pair<T1, T2>& p) {
    first = p.first;
    second = p.second;
    return *this;
  }
};

template <typename T1, typename T2>
inline tier<T1, T2> tie(T1& f, T2& s) {
  return tier<T1, T2>(f, s);
}
template<class T, std::size_t N>
inline T *array_endof(T (&x)[N]) {
  return x+N;
}


template<class T, std::size_t N>
inline size_t array_lengthof(T (&)[N]) {
  return N;
}



template<typename T>
static inline int array_pod_sort_comparator(const void *P1, const void *P2) {
  if (*reinterpret_cast<const T*>(P1) < *reinterpret_cast<const T*>(P2))
    return -1;
  if (*reinterpret_cast<const T*>(P2) < *reinterpret_cast<const T*>(P1))
    return 1;
  return 0;
}



template<typename T>
static int (*get_array_pad_sort_comparator(const T &))
             (const void*, const void*) {
  return array_pod_sort_comparator<T>;
}
template<class IteratorTy>
static inline void array_pod_sort(IteratorTy Start, IteratorTy End) {

  if (Start == End) return;
  qsort(&*Start, End-Start, sizeof(*Start),
        get_array_pad_sort_comparator(*Start));
}

template<class IteratorTy>
static inline void array_pod_sort(IteratorTy Start, IteratorTy End,
                                  int (*Compare)(const void*, const void*)) {

  if (Start == End) return;
  qsort(&*Start, End-Start, sizeof(*Start), Compare);
}







template<typename Container>
void DeleteContainerPointers(Container &C) {
  for (typename Container::iterator I = C.begin(), E = C.end(); I != E; ++I)
    delete *I;
  C.clear();
}



template<typename Container>
void DeleteContainerSeconds(Container &C) {
  for (typename Container::iterator I = C.begin(), E = C.end(); I != E; ++I)
    delete I->second;
  C.clear();
}

}


namespace llvm {
  class MDNode;
  class LLVMContext;




  class DebugLoc {
    friend struct DenseMapInfo<DebugLoc>;



    static DebugLoc getEmptyKey() {
      DebugLoc DL;
      DL.LineCol = 1;
      return DL;
    }



    static DebugLoc getTombstoneKey() {
      DebugLoc DL;
      DL.LineCol = 2;
      return DL;
    }




    unsigned LineCol;



    int ScopeIdx;
  public:
    DebugLoc() : LineCol(0), ScopeIdx(0) {}



    static DebugLoc get(unsigned Line, unsigned Col,
                        MDNode *Scope, MDNode *InlinedAt = 0);


    static DebugLoc getFromDILocation(MDNode *N);


    static DebugLoc getFromDILexicalBlock(MDNode *N);


    bool isUnknown() const { return ScopeIdx == 0; }

    unsigned getLine() const {
      return (LineCol << 8) >> 8;
    }

    unsigned getCol() const {
      return LineCol >> 24;
    }



    MDNode *getScope(const LLVMContext &Ctx) const;



    MDNode *getInlinedAt(const LLVMContext &Ctx) const;


    void getScopeAndInlinedAt(MDNode *&Scope, MDNode *&IA,
                              const LLVMContext &Ctx) const;




    MDNode *getAsMDNode(const LLVMContext &Ctx) const;

    bool operator==(const DebugLoc &DL) const {
      return LineCol == DL.LineCol && ScopeIdx == DL.ScopeIdx;
    }
    bool operator!=(const DebugLoc &DL) const { return !(*this == DL); }

    void dump(const LLVMContext &Ctx) const;
  };

  template <>
  struct DenseMapInfo<DebugLoc> {
    static DebugLoc getEmptyKey();
    static DebugLoc getTombstoneKey();
    static unsigned getHashValue(const DebugLoc &Key);
    static bool isEqual(const DebugLoc &LHS, const DebugLoc &RHS);
  };
}






namespace std __attribute__ ((__visibility__ ("default"))) {






  template<typename _Tp, typename _Alloc>
    struct _Vector_base
    {
      typedef typename _Alloc::template rebind<_Tp>::other _Tp_alloc_type;

      struct _Vector_impl
      : public _Tp_alloc_type
      {
 _Tp* _M_start;
 _Tp* _M_finish;
 _Tp* _M_end_of_storage;
 _Vector_impl(_Tp_alloc_type const& __a)
 : _Tp_alloc_type(__a), _M_start(0), _M_finish(0), _M_end_of_storage(0)
 { }
      };

    public:
      typedef _Alloc allocator_type;

      _Tp_alloc_type&
      _M_get_Tp_allocator()
      { return *static_cast<_Tp_alloc_type*>(&this->_M_impl); }

      const _Tp_alloc_type&
      _M_get_Tp_allocator() const
      { return *static_cast<const _Tp_alloc_type*>(&this->_M_impl); }

      allocator_type
      get_allocator() const
      { return allocator_type(_M_get_Tp_allocator()); }

      _Vector_base(const allocator_type& __a)
      : _M_impl(__a)
      { }

      _Vector_base(size_t __n, const allocator_type& __a)
      : _M_impl(__a)
      {
 this->_M_impl._M_start = this->_M_allocate(__n);
 this->_M_impl._M_finish = this->_M_impl._M_start;
 this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;
      }

      ~_Vector_base()
      { _M_deallocate(this->_M_impl._M_start, this->_M_impl._M_end_of_storage
        - this->_M_impl._M_start); }

    public:
      _Vector_impl _M_impl;

      _Tp*
      _M_allocate(size_t __n)
      { return _M_impl.allocate(__n); }

      void
      _M_deallocate(_Tp* __p, size_t __n)
      {
 if (__p)
   _M_impl.deallocate(__p, __n);
      }
    };
  template<typename _Tp, typename _Alloc = std::allocator<_Tp> >
    class vector : protected _Vector_base<_Tp, _Alloc>
    {

      typedef typename _Alloc::value_type _Alloc_value_type;



      typedef _Vector_base<_Tp, _Alloc> _Base;
      typedef vector<_Tp, _Alloc> vector_type;
      typedef typename _Base::_Tp_alloc_type _Tp_alloc_type;

    public:
      typedef _Tp value_type;
      typedef typename _Tp_alloc_type::pointer pointer;
      typedef typename _Tp_alloc_type::const_pointer const_pointer;
      typedef typename _Tp_alloc_type::reference reference;
      typedef typename _Tp_alloc_type::const_reference const_reference;
      typedef __gnu_cxx::__normal_iterator<pointer, vector_type> iterator;
      typedef __gnu_cxx::__normal_iterator<const_pointer, vector_type>
      const_iterator;
      typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
      typedef std::reverse_iterator<iterator> reverse_iterator;
      typedef size_t size_type;
      typedef ptrdiff_t difference_type;
      typedef _Alloc allocator_type;

    protected:
      using _Base::_M_allocate;
      using _Base::_M_deallocate;
      using _Base::_M_impl;
      using _Base::_M_get_Tp_allocator;

    public:





      explicit
      vector(const allocator_type& __a = allocator_type())
      : _Base(__a)
      { }
      explicit
      vector(size_type __n, const value_type& __value = value_type(),
      const allocator_type& __a = allocator_type())
      : _Base(__n, __a)
      {
 std::__uninitialized_fill_n_a(this->_M_impl._M_start, __n, __value,
          _M_get_Tp_allocator());
 this->_M_impl._M_finish = this->_M_impl._M_start + __n;
      }
      vector(const vector& __x)
      : _Base(__x.size(), __x._M_get_Tp_allocator())
      { this->_M_impl._M_finish =
   std::__uninitialized_copy_a(__x.begin(), __x.end(),
          this->_M_impl._M_start,
          _M_get_Tp_allocator());
      }
      template<typename _InputIterator>
        vector(_InputIterator __first, _InputIterator __last,
        const allocator_type& __a = allocator_type())
 : _Base(__a)
        {

   typedef typename std::__is_integer<_InputIterator>::__type _Integral;
   _M_initialize_dispatch(__first, __last, _Integral());
 }







      ~vector()
      { std::_Destroy(this->_M_impl._M_start, this->_M_impl._M_finish,
        _M_get_Tp_allocator()); }
      vector&
      operator=(const vector& __x);
      void
      assign(size_type __n, const value_type& __val)
      { _M_fill_assign(__n, __val); }
      template<typename _InputIterator>
        void
        assign(_InputIterator __first, _InputIterator __last)
        {

   typedef typename std::__is_integer<_InputIterator>::__type _Integral;
   _M_assign_dispatch(__first, __last, _Integral());
 }


      using _Base::get_allocator;







      iterator
      begin()
      { return iterator(this->_M_impl._M_start); }






      const_iterator
      begin() const
      { return const_iterator(this->_M_impl._M_start); }






      iterator
      end()
      { return iterator(this->_M_impl._M_finish); }






      const_iterator
      end() const
      { return const_iterator(this->_M_impl._M_finish); }






      reverse_iterator
      rbegin()
      { return reverse_iterator(end()); }






      const_reverse_iterator
      rbegin() const
      { return const_reverse_iterator(end()); }






      reverse_iterator
      rend()
      { return reverse_iterator(begin()); }






      const_reverse_iterator
      rend() const
      { return const_reverse_iterator(begin()); }



      size_type
      size() const
      { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }


      size_type
      max_size() const
      { return _M_get_Tp_allocator().max_size(); }
      void
      resize(size_type __new_size, value_type __x = value_type())
      {
 if (__new_size < size())
   _M_erase_at_end(this->_M_impl._M_start + __new_size);
 else
   insert(end(), __new_size - size(), __x);
      }





      size_type
      capacity() const
      { return size_type(this->_M_impl._M_end_of_storage
    - this->_M_impl._M_start); }





      bool
      empty() const
      { return begin() == end(); }
      void
      reserve(size_type __n);
      reference
      operator[](size_type __n)
      { return *(this->_M_impl._M_start + __n); }
      const_reference
      operator[](size_type __n) const
      { return *(this->_M_impl._M_start + __n); }

    protected:

      void
      _M_range_check(size_type __n) const
      {
 if (__n >= this->size())
   __throw_out_of_range(("vector::_M_range_check"));
      }

    public:
      reference
      at(size_type __n)
      {
 _M_range_check(__n);
 return (*this)[__n];
      }
      const_reference
      at(size_type __n) const
      {
 _M_range_check(__n);
 return (*this)[__n];
      }





      reference
      front()
      { return *begin(); }





      const_reference
      front() const
      { return *begin(); }





      reference
      back()
      { return *(end() - 1); }





      const_reference
      back() const
      { return *(end() - 1); }
      pointer
      data()
      { return pointer(this->_M_impl._M_start); }

      const_pointer
      data() const
      { return const_pointer(this->_M_impl._M_start); }
      void
      push_back(const value_type& __x)
      {
 if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage)
   {
     this->_M_impl.construct(this->_M_impl._M_finish, __x);
     ++this->_M_impl._M_finish;
   }
 else
   _M_insert_aux(end(), __x);
      }
      void
      pop_back()
      {
 --this->_M_impl._M_finish;
 this->_M_impl.destroy(this->_M_impl._M_finish);
      }
      iterator
      insert(iterator __position, const value_type& __x);
      void
      insert(iterator __position, size_type __n, const value_type& __x)
      { _M_fill_insert(__position, __n, __x); }
      template<typename _InputIterator>
        void
        insert(iterator __position, _InputIterator __first,
        _InputIterator __last)
        {

   typedef typename std::__is_integer<_InputIterator>::__type _Integral;
   _M_insert_dispatch(__position, __first, __last, _Integral());
 }
      iterator
      erase(iterator __position);
      iterator
      erase(iterator __first, iterator __last);
      void
      swap(vector& __x)
      {
 std::swap(this->_M_impl._M_start, __x._M_impl._M_start);
 std::swap(this->_M_impl._M_finish, __x._M_impl._M_finish);
 std::swap(this->_M_impl._M_end_of_storage,
    __x._M_impl._M_end_of_storage);



 std::__alloc_swap<_Tp_alloc_type>::_S_do_it(_M_get_Tp_allocator(),
          __x._M_get_Tp_allocator());
      }







      void
      clear()
      { _M_erase_at_end(this->_M_impl._M_start); }

    protected:






      template<typename _ForwardIterator>
        pointer
        _M_allocate_and_copy(size_type __n,
        _ForwardIterator __first, _ForwardIterator __last)
        {
   pointer __result = this->_M_allocate(__n);
   if (true)
     {
       std::__uninitialized_copy_a(__first, __last, __result,
       _M_get_Tp_allocator());
       return __result;
     }
   if (false)
     {
       _M_deallocate(__result, __n);
                              ;
     }
 }





      template<typename _Integer>
        void
        _M_initialize_dispatch(_Integer __n, _Integer __value, __true_type)
        {
   this->_M_impl._M_start = _M_allocate(__n);
   this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;
   std::__uninitialized_fill_n_a(this->_M_impl._M_start, __n, __value,
     _M_get_Tp_allocator());
   this->_M_impl._M_finish = this->_M_impl._M_end_of_storage;
 }


      template<typename _InputIterator>
        void
        _M_initialize_dispatch(_InputIterator __first, _InputIterator __last,
          __false_type)
        {
   typedef typename std::iterator_traits<_InputIterator>::
     iterator_category _IterCategory;
   _M_range_initialize(__first, __last, _IterCategory());
 }


      template<typename _InputIterator>
        void
        _M_range_initialize(_InputIterator __first,
       _InputIterator __last, std::input_iterator_tag)
        {
   for (; __first != __last; ++__first)
     push_back(*__first);
 }


      template<typename _ForwardIterator>
        void
        _M_range_initialize(_ForwardIterator __first,
       _ForwardIterator __last, std::forward_iterator_tag)
        {
   const size_type __n = std::distance(__first, __last);
   this->_M_impl._M_start = this->_M_allocate(__n);
   this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;
   this->_M_impl._M_finish =
     std::__uninitialized_copy_a(__first, __last,
     this->_M_impl._M_start,
     _M_get_Tp_allocator());
 }






      template<typename _Integer>
        void
        _M_assign_dispatch(_Integer __n, _Integer __val, __true_type)
        {
   _M_fill_assign(static_cast<size_type>(__n),
    static_cast<value_type>(__val));
 }


      template<typename _InputIterator>
        void
        _M_assign_dispatch(_InputIterator __first, _InputIterator __last,
      __false_type)
        {
   typedef typename std::iterator_traits<_InputIterator>::
     iterator_category _IterCategory;
   _M_assign_aux(__first, __last, _IterCategory());
 }


      template<typename _InputIterator>
        void
        _M_assign_aux(_InputIterator __first, _InputIterator __last,
        std::input_iterator_tag);


      template<typename _ForwardIterator>
        void
        _M_assign_aux(_ForwardIterator __first, _ForwardIterator __last,
        std::forward_iterator_tag);



      void
      _M_fill_assign(size_type __n, const value_type& __val);





      template<typename _Integer>
        void
        _M_insert_dispatch(iterator __pos, _Integer __n, _Integer __val,
      __true_type)
        {
   _M_fill_insert(__pos, static_cast<size_type>(__n),
    static_cast<value_type>(__val));
 }


      template<typename _InputIterator>
        void
        _M_insert_dispatch(iterator __pos, _InputIterator __first,
      _InputIterator __last, __false_type)
        {
   typedef typename std::iterator_traits<_InputIterator>::
     iterator_category _IterCategory;
   _M_range_insert(__pos, __first, __last, _IterCategory());
 }


      template<typename _InputIterator>
        void
        _M_range_insert(iterator __pos, _InputIterator __first,
   _InputIterator __last, std::input_iterator_tag);


      template<typename _ForwardIterator>
        void
        _M_range_insert(iterator __pos, _ForwardIterator __first,
   _ForwardIterator __last, std::forward_iterator_tag);



      void
      _M_fill_insert(iterator __pos, size_type __n, const value_type& __x);


      void
      _M_insert_aux(iterator __position, const value_type& __x);





      void
      _M_erase_at_end(pointer __pos)
      {
 std::_Destroy(__pos, this->_M_impl._M_finish, _M_get_Tp_allocator());
 this->_M_impl._M_finish = __pos;
      }
    };
  template<typename _Tp, typename _Alloc>
    inline bool
    operator==(const vector<_Tp, _Alloc>& __x, const vector<_Tp, _Alloc>& __y)
    { return (__x.size() == __y.size()
       && std::equal(__x.begin(), __x.end(), __y.begin())); }
  template<typename _Tp, typename _Alloc>
    inline bool
    operator<(const vector<_Tp, _Alloc>& __x, const vector<_Tp, _Alloc>& __y)
    { return std::lexicographical_compare(__x.begin(), __x.end(),
       __y.begin(), __y.end()); }


  template<typename _Tp, typename _Alloc>
    inline bool
    operator!=(const vector<_Tp, _Alloc>& __x, const vector<_Tp, _Alloc>& __y)
    { return !(__x == __y); }


  template<typename _Tp, typename _Alloc>
    inline bool
    operator>(const vector<_Tp, _Alloc>& __x, const vector<_Tp, _Alloc>& __y)
    { return __y < __x; }


  template<typename _Tp, typename _Alloc>
    inline bool
    operator<=(const vector<_Tp, _Alloc>& __x, const vector<_Tp, _Alloc>& __y)
    { return !(__y < __x); }


  template<typename _Tp, typename _Alloc>
    inline bool
    operator>=(const vector<_Tp, _Alloc>& __x, const vector<_Tp, _Alloc>& __y)
    { return !(__x < __y); }


  template<typename _Tp, typename _Alloc>
    inline void
    swap(vector<_Tp, _Alloc>& __x, vector<_Tp, _Alloc>& __y)
    { __x.swap(__y); }

}
namespace std __attribute__ ((__visibility__ ("default"))) {

  typedef unsigned long _Bit_type;
  enum { _S_word_bit = int(8 * sizeof(_Bit_type)) };

  struct _Bit_reference
  {
    _Bit_type * _M_p;
    _Bit_type _M_mask;

    _Bit_reference(_Bit_type * __x, _Bit_type __y)
    : _M_p(__x), _M_mask(__y) { }

    _Bit_reference() : _M_p(0), _M_mask(0) { }

    operator bool() const
    { return !!(*_M_p & _M_mask); }

    _Bit_reference&
    operator=(bool __x)
    {
      if (__x)
 *_M_p |= _M_mask;
      else
 *_M_p &= ~_M_mask;
      return *this;
    }

    _Bit_reference&
    operator=(const _Bit_reference& __x)
    { return *this = bool(__x); }

    bool
    operator==(const _Bit_reference& __x) const
    { return bool(*this) == bool(__x); }

    bool
    operator<(const _Bit_reference& __x) const
    { return !bool(*this) && bool(__x); }

    void
    flip()
    { *_M_p ^= _M_mask; }
  };

  struct _Bit_iterator_base
  : public std::iterator<std::random_access_iterator_tag, bool>
  {
    _Bit_type * _M_p;
    unsigned int _M_offset;

    _Bit_iterator_base(_Bit_type * __x, unsigned int __y)
    : _M_p(__x), _M_offset(__y) { }

    void
    _M_bump_up()
    {
      if (_M_offset++ == int(_S_word_bit) - 1)
 {
   _M_offset = 0;
   ++_M_p;
 }
    }

    void
    _M_bump_down()
    {
      if (_M_offset-- == 0)
 {
   _M_offset = int(_S_word_bit) - 1;
   --_M_p;
 }
    }

    void
    _M_incr(ptrdiff_t __i)
    {
      difference_type __n = __i + _M_offset;
      _M_p += __n / int(_S_word_bit);
      __n = __n % int(_S_word_bit);
      if (__n < 0)
 {
   __n += int(_S_word_bit);
   --_M_p;
 }
      _M_offset = static_cast<unsigned int>(__n);
    }

    bool
    operator==(const _Bit_iterator_base& __i) const
    { return _M_p == __i._M_p && _M_offset == __i._M_offset; }

    bool
    operator<(const _Bit_iterator_base& __i) const
    {
      return _M_p < __i._M_p
      || (_M_p == __i._M_p && _M_offset < __i._M_offset);
    }

    bool
    operator!=(const _Bit_iterator_base& __i) const
    { return !(*this == __i); }

    bool
    operator>(const _Bit_iterator_base& __i) const
    { return __i < *this; }

    bool
    operator<=(const _Bit_iterator_base& __i) const
    { return !(__i < *this); }

    bool
    operator>=(const _Bit_iterator_base& __i) const
    { return !(*this < __i); }
  };

  inline ptrdiff_t
  operator-(const _Bit_iterator_base& __x, const _Bit_iterator_base& __y)
  {
    return (int(_S_word_bit) * (__x._M_p - __y._M_p)
     + __x._M_offset - __y._M_offset);
  }

  struct _Bit_iterator : public _Bit_iterator_base
  {
    typedef _Bit_reference reference;
    typedef _Bit_reference* pointer;
    typedef _Bit_iterator iterator;

    _Bit_iterator() : _Bit_iterator_base(0, 0) { }

    _Bit_iterator(_Bit_type * __x, unsigned int __y)
    : _Bit_iterator_base(__x, __y) { }

    reference
    operator*() const
    { return reference(_M_p, 1UL << _M_offset); }

    iterator&
    operator++()
    {
      _M_bump_up();
      return *this;
    }

    iterator
    operator++(int)
    {
      iterator __tmp = *this;
      _M_bump_up();
      return __tmp;
    }

    iterator&
    operator--()
    {
      _M_bump_down();
      return *this;
    }

    iterator
    operator--(int)
    {
      iterator __tmp = *this;
      _M_bump_down();
      return __tmp;
    }

    iterator&
    operator+=(difference_type __i)
    {
      _M_incr(__i);
      return *this;
    }

    iterator&
    operator-=(difference_type __i)
    {
      *this += -__i;
      return *this;
    }

    iterator
    operator+(difference_type __i) const
    {
      iterator __tmp = *this;
      return __tmp += __i;
    }

    iterator
    operator-(difference_type __i) const
    {
      iterator __tmp = *this;
      return __tmp -= __i;
    }

    reference
    operator[](difference_type __i) const
    { return *(*this + __i); }
  };

  inline _Bit_iterator
  operator+(ptrdiff_t __n, const _Bit_iterator& __x)
  { return __x + __n; }

  struct _Bit_const_iterator : public _Bit_iterator_base
  {
    typedef bool reference;
    typedef bool const_reference;
    typedef const bool* pointer;
    typedef _Bit_const_iterator const_iterator;

    _Bit_const_iterator() : _Bit_iterator_base(0, 0) { }

    _Bit_const_iterator(_Bit_type * __x, unsigned int __y)
    : _Bit_iterator_base(__x, __y) { }

    _Bit_const_iterator(const _Bit_iterator& __x)
    : _Bit_iterator_base(__x._M_p, __x._M_offset) { }

    const_reference
    operator*() const
    { return _Bit_reference(_M_p, 1UL << _M_offset); }

    const_iterator&
    operator++()
    {
      _M_bump_up();
      return *this;
    }

    const_iterator
    operator++(int)
    {
      const_iterator __tmp = *this;
      _M_bump_up();
      return __tmp;
    }

    const_iterator&
    operator--()
    {
      _M_bump_down();
      return *this;
    }

    const_iterator
    operator--(int)
    {
      const_iterator __tmp = *this;
      _M_bump_down();
      return __tmp;
    }

    const_iterator&
    operator+=(difference_type __i)
    {
      _M_incr(__i);
      return *this;
    }

    const_iterator&
    operator-=(difference_type __i)
    {
      *this += -__i;
      return *this;
    }

    const_iterator
    operator+(difference_type __i) const
    {
      const_iterator __tmp = *this;
      return __tmp += __i;
    }

    const_iterator
    operator-(difference_type __i) const
    {
      const_iterator __tmp = *this;
      return __tmp -= __i;
    }

    const_reference
    operator[](difference_type __i) const
    { return *(*this + __i); }
  };

  inline _Bit_const_iterator
  operator+(ptrdiff_t __n, const _Bit_const_iterator& __x)
  { return __x + __n; }

  inline void
  __fill_bvector(_Bit_iterator __first, _Bit_iterator __last, bool __x)
  {
    for (; __first != __last; ++__first)
      *__first = __x;
  }

  inline void
  fill(_Bit_iterator __first, _Bit_iterator __last, const bool& __x)
  {
    if (__first._M_p != __last._M_p)
      {
 std::fill(__first._M_p + 1, __last._M_p, __x ? ~0 : 0);
 __fill_bvector(__first, _Bit_iterator(__first._M_p + 1, 0), __x);
 __fill_bvector(_Bit_iterator(__last._M_p, 0), __last, __x);
      }
    else
      __fill_bvector(__first, __last, __x);
  }

  template<class _Alloc>
    struct _Bvector_base
    {
      typedef typename _Alloc::template rebind<_Bit_type>::other
        _Bit_alloc_type;

      struct _Bvector_impl
      : public _Bit_alloc_type
      {
 _Bit_iterator _M_start;
 _Bit_iterator _M_finish;
 _Bit_type* _M_end_of_storage;
 _Bvector_impl(const _Bit_alloc_type& __a)
 : _Bit_alloc_type(__a), _M_start(), _M_finish(), _M_end_of_storage(0)
 { }
      };

    public:
      typedef _Alloc allocator_type;

      _Bit_alloc_type&
      _M_get_Bit_allocator()
      { return *static_cast<_Bit_alloc_type*>(&this->_M_impl); }

      const _Bit_alloc_type&
      _M_get_Bit_allocator() const
      { return *static_cast<const _Bit_alloc_type*>(&this->_M_impl); }

      allocator_type
      get_allocator() const
      { return allocator_type(_M_get_Bit_allocator()); }

      _Bvector_base(const allocator_type& __a) : _M_impl(__a) { }

      ~_Bvector_base()
      { this->_M_deallocate(); }

    protected:
      _Bvector_impl _M_impl;

      _Bit_type*
      _M_allocate(size_t __n)
      { return _M_impl.allocate((__n + int(_S_word_bit) - 1)
    / int(_S_word_bit)); }

      void
      _M_deallocate()
      {
 if (_M_impl._M_start._M_p)
   _M_impl.deallocate(_M_impl._M_start._M_p,
        _M_impl._M_end_of_storage - _M_impl._M_start._M_p);
      }
    };

}




namespace std __attribute__ ((__visibility__ ("default"))) {
template<typename _Alloc>
  class vector<bool, _Alloc> : protected _Bvector_base<_Alloc>
  {
    typedef _Bvector_base<_Alloc> _Base;

  public:
    typedef bool value_type;
    typedef size_t size_type;
    typedef ptrdiff_t difference_type;
    typedef _Bit_reference reference;
    typedef bool const_reference;
    typedef _Bit_reference* pointer;
    typedef const bool* const_pointer;
    typedef _Bit_iterator iterator;
    typedef _Bit_const_iterator const_iterator;
    typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
    typedef std::reverse_iterator<iterator> reverse_iterator;
    typedef _Alloc allocator_type;

    allocator_type get_allocator() const
    { return _Base::get_allocator(); }

  protected:
    using _Base::_M_allocate;
    using _Base::_M_deallocate;
    using _Base::_M_get_Bit_allocator;

  public:
    explicit
    vector(const allocator_type& __a = allocator_type())
    : _Base(__a) { }

    explicit
    vector(size_type __n, const bool& __value = bool(),
    const allocator_type& __a = allocator_type())
    : _Base(__a)
    {
      _M_initialize(__n);
      std::fill(this->_M_impl._M_start._M_p, this->_M_impl._M_end_of_storage,
  __value ? ~0 : 0);
    }

    vector(const vector& __x)
    : _Base(__x._M_get_Bit_allocator())
    {
      _M_initialize(__x.size());
      _M_copy_aligned(__x.begin(), __x.end(), this->_M_impl._M_start);
    }

    template<class _InputIterator>
      vector(_InputIterator __first, _InputIterator __last,
      const allocator_type& __a = allocator_type())
      : _Base(__a)
      {
 typedef typename std::__is_integer<_InputIterator>::__type _Integral;
 _M_initialize_dispatch(__first, __last, _Integral());
      }

    ~vector() { }

    vector&
    operator=(const vector& __x)
    {
      if (&__x == this)
 return *this;
      if (__x.size() > capacity())
 {
   this->_M_deallocate();
   _M_initialize(__x.size());
 }
      this->_M_impl._M_finish = _M_copy_aligned(__x.begin(), __x.end(),
      begin());
      return *this;
    }





    void
    assign(size_type __n, const bool& __x)
    { _M_fill_assign(__n, __x); }

    template<class _InputIterator>
      void
      assign(_InputIterator __first, _InputIterator __last)
      {
 typedef typename std::__is_integer<_InputIterator>::__type _Integral;
 _M_assign_dispatch(__first, __last, _Integral());
      }

    iterator
    begin()
    { return this->_M_impl._M_start; }

    const_iterator
    begin() const
    { return this->_M_impl._M_start; }

    iterator
    end()
    { return this->_M_impl._M_finish; }

    const_iterator
    end() const
    { return this->_M_impl._M_finish; }

    reverse_iterator
    rbegin()
    { return reverse_iterator(end()); }

    const_reverse_iterator
    rbegin() const
    { return const_reverse_iterator(end()); }

    reverse_iterator
    rend()
    { return reverse_iterator(begin()); }

    const_reverse_iterator
    rend() const
    { return const_reverse_iterator(begin()); }

    size_type
    size() const
    { return size_type(end() - begin()); }

    size_type
    max_size() const
    {
      const size_type __asize = _M_get_Bit_allocator().max_size();
      return (__asize <= size_type(-1) / int(_S_word_bit) ?
       __asize * int(_S_word_bit) : size_type(-1));
    }

    size_type
    capacity() const
    { return size_type(const_iterator(this->_M_impl._M_end_of_storage, 0)
         - begin()); }

    bool
    empty() const
    { return begin() == end(); }

    reference
    operator[](size_type __n)
    {
      return *iterator(this->_M_impl._M_start._M_p
         + __n / int(_S_word_bit), __n % int(_S_word_bit));
    }

    const_reference
    operator[](size_type __n) const
    {
      return *const_iterator(this->_M_impl._M_start._M_p
        + __n / int(_S_word_bit), __n % int(_S_word_bit));
    }

  protected:
    void
    _M_range_check(size_type __n) const
    {
      if (__n >= this->size())
        __throw_out_of_range(("vector<bool>::_M_range_check"));
    }

  public:
    reference
    at(size_type __n)
    { _M_range_check(__n); return (*this)[__n]; }

    const_reference
    at(size_type __n) const
    { _M_range_check(__n); return (*this)[__n]; }

    void
    reserve(size_type __n)
    {
      if (__n > this->max_size())
 __throw_length_error(("vector::reserve"));
      if (this->capacity() < __n)
 {
   _Bit_type* __q = this->_M_allocate(__n);
   this->_M_impl._M_finish = _M_copy_aligned(begin(), end(),
          iterator(__q, 0));
   this->_M_deallocate();
   this->_M_impl._M_start = iterator(__q, 0);
   this->_M_impl._M_end_of_storage = (__q + (__n + int(_S_word_bit) - 1)
          / int(_S_word_bit));
 }
    }

    reference
    front()
    { return *begin(); }

    const_reference
    front() const
    { return *begin(); }

    reference
    back()
    { return *(end() - 1); }

    const_reference
    back() const
    { return *(end() - 1); }






    void
    data() { }

    void
    push_back(bool __x)
    {
      if (this->_M_impl._M_finish._M_p != this->_M_impl._M_end_of_storage)
        *this->_M_impl._M_finish++ = __x;
      else
        _M_insert_aux(end(), __x);
    }

    void
    swap(vector<bool, _Alloc>& __x)
    {
      std::swap(this->_M_impl._M_start, __x._M_impl._M_start);
      std::swap(this->_M_impl._M_finish, __x._M_impl._M_finish);
      std::swap(this->_M_impl._M_end_of_storage,
  __x._M_impl._M_end_of_storage);



      std::__alloc_swap<typename _Base::_Bit_alloc_type>::
 _S_do_it(_M_get_Bit_allocator(), __x._M_get_Bit_allocator());
    }


    static void
    swap(reference __x, reference __y)
    {
      bool __tmp = __x;
      __x = __y;
      __y = __tmp;
    }

    iterator
    insert(iterator __position, const bool& __x = bool())
    {
      const difference_type __n = __position - begin();
      if (this->_M_impl._M_finish._M_p != this->_M_impl._M_end_of_storage
   && __position == end())
        *this->_M_impl._M_finish++ = __x;
      else
        _M_insert_aux(__position, __x);
      return begin() + __n;
    }

    template<class _InputIterator>
      void
      insert(iterator __position,
      _InputIterator __first, _InputIterator __last)
      {
 typedef typename std::__is_integer<_InputIterator>::__type _Integral;
 _M_insert_dispatch(__position, __first, __last, _Integral());
      }

    void
    insert(iterator __position, size_type __n, const bool& __x)
    { _M_fill_insert(__position, __n, __x); }

    void
    pop_back()
    { --this->_M_impl._M_finish; }

    iterator
    erase(iterator __position)
    {
      if (__position + 1 != end())
        std::copy(__position + 1, end(), __position);
      --this->_M_impl._M_finish;
      return __position;
    }

    iterator
    erase(iterator __first, iterator __last)
    {
      _M_erase_at_end(std::copy(__last, end(), __first));
      return __first;
    }

    void
    resize(size_type __new_size, bool __x = bool())
    {
      if (__new_size < size())
        _M_erase_at_end(begin() + difference_type(__new_size));
      else
        insert(end(), __new_size - size(), __x);
    }

    void
    flip()
    {
      for (_Bit_type * __p = this->_M_impl._M_start._M_p;
    __p != this->_M_impl._M_end_of_storage; ++__p)
        *__p = ~*__p;
    }

    void
    clear()
    { _M_erase_at_end(begin()); }


  protected:

    iterator
    _M_copy_aligned(const_iterator __first, const_iterator __last,
      iterator __result)
    {
      _Bit_type* __q = std::copy(__first._M_p, __last._M_p, __result._M_p);
      return std::copy(const_iterator(__last._M_p, 0), __last,
         iterator(__q, 0));
    }

    void
    _M_initialize(size_type __n)
    {
      _Bit_type* __q = this->_M_allocate(__n);
      this->_M_impl._M_end_of_storage = (__q
      + ((__n + int(_S_word_bit) - 1)
         / int(_S_word_bit)));
      this->_M_impl._M_start = iterator(__q, 0);
      this->_M_impl._M_finish = this->_M_impl._M_start + difference_type(__n);
    }


    template<class _Integer>
      void
      _M_initialize_dispatch(_Integer __n, _Integer __x, __true_type)
      {
 _M_initialize(__n);
 std::fill(this->_M_impl._M_start._M_p,
    this->_M_impl._M_end_of_storage, __x ? ~0 : 0);
      }

    template<class _InputIterator>
      void
      _M_initialize_dispatch(_InputIterator __first, _InputIterator __last,
        __false_type)
      { _M_initialize_range(__first, __last,
       std::__iterator_category(__first)); }

    template<class _InputIterator>
      void
      _M_initialize_range(_InputIterator __first, _InputIterator __last,
     std::input_iterator_tag)
      {
 for (; __first != __last; ++__first)
   push_back(*__first);
      }

    template<class _ForwardIterator>
      void
      _M_initialize_range(_ForwardIterator __first, _ForwardIterator __last,
     std::forward_iterator_tag)
      {
 const size_type __n = std::distance(__first, __last);
 _M_initialize(__n);
 std::copy(__first, __last, this->_M_impl._M_start);
      }

    template<class _Integer>
      void
      _M_assign_dispatch(_Integer __n, _Integer __val, __true_type)
      { _M_fill_assign((size_t) __n, (bool) __val); }

    template<class _InputIterator>
      void
      _M_assign_dispatch(_InputIterator __first, _InputIterator __last,
    __false_type)
      { _M_assign_aux(__first, __last, std::__iterator_category(__first)); }

    void
    _M_fill_assign(size_t __n, bool __x)
    {
      if (__n > size())
 {
   std::fill(this->_M_impl._M_start._M_p,
      this->_M_impl._M_end_of_storage, __x ? ~0 : 0);
   insert(end(), __n - size(), __x);
 }
      else
 {
   _M_erase_at_end(begin() + __n);
   std::fill(this->_M_impl._M_start._M_p,
      this->_M_impl._M_end_of_storage, __x ? ~0 : 0);
 }
    }

    template<class _InputIterator>
      void
      _M_assign_aux(_InputIterator __first, _InputIterator __last,
      std::input_iterator_tag)
      {
 iterator __cur = begin();
 for (; __first != __last && __cur != end(); ++__cur, ++__first)
   *__cur = *__first;
 if (__first == __last)
   _M_erase_at_end(__cur);
 else
   insert(end(), __first, __last);
      }

    template<class _ForwardIterator>
      void
      _M_assign_aux(_ForwardIterator __first, _ForwardIterator __last,
      std::forward_iterator_tag)
      {
 const size_type __len = std::distance(__first, __last);
 if (__len < size())
   _M_erase_at_end(std::copy(__first, __last, begin()));
 else
   {
     _ForwardIterator __mid = __first;
     std::advance(__mid, size());
     std::copy(__first, __mid, begin());
     insert(end(), __mid, __last);
   }
      }


    template<class _Integer>
      void
      _M_insert_dispatch(iterator __pos, _Integer __n, _Integer __x,
    __true_type)
      { _M_fill_insert(__pos, __n, __x); }

    template<class _InputIterator>
      void
      _M_insert_dispatch(iterator __pos,
    _InputIterator __first, _InputIterator __last,
    __false_type)
      { _M_insert_range(__pos, __first, __last,
   std::__iterator_category(__first)); }

    void
    _M_fill_insert(iterator __position, size_type __n, bool __x)
    {
      if (__n == 0)
 return;
      if (capacity() - size() >= __n)
 {
   std::copy_backward(__position, end(),
        this->_M_impl._M_finish + difference_type(__n));
   std::fill(__position, __position + difference_type(__n), __x);
   this->_M_impl._M_finish += difference_type(__n);
 }
      else
 {
   const size_type __len = size() + std::max(size(), __n);
   _Bit_type * __q = this->_M_allocate(__len);
   iterator __i = _M_copy_aligned(begin(), __position,
      iterator(__q, 0));
   std::fill(__i, __i + difference_type(__n), __x);
   this->_M_impl._M_finish = std::copy(__position, end(),
           __i + difference_type(__n));
   this->_M_deallocate();
   this->_M_impl._M_end_of_storage = (__q + ((__len
           + int(_S_word_bit) - 1)
          / int(_S_word_bit)));
   this->_M_impl._M_start = iterator(__q, 0);
 }
    }

    template<class _InputIterator>
      void
      _M_insert_range(iterator __pos, _InputIterator __first,
        _InputIterator __last, std::input_iterator_tag)
      {
 for (; __first != __last; ++__first)
   {
     __pos = insert(__pos, *__first);
     ++__pos;
   }
      }

    template<class _ForwardIterator>
      void
      _M_insert_range(iterator __position, _ForwardIterator __first,
        _ForwardIterator __last, std::forward_iterator_tag)
      {
 if (__first != __last)
   {
     size_type __n = std::distance(__first, __last);
     if (capacity() - size() >= __n)
       {
  std::copy_backward(__position, end(),
       this->_M_impl._M_finish
       + difference_type(__n));
  std::copy(__first, __last, __position);
  this->_M_impl._M_finish += difference_type(__n);
       }
     else
       {
  const size_type __len = size() + std::max(size(), __n);
  _Bit_type * __q = this->_M_allocate(__len);
  iterator __i = _M_copy_aligned(begin(), __position,
            iterator(__q, 0));
  __i = std::copy(__first, __last, __i);
  this->_M_impl._M_finish = std::copy(__position, end(), __i);
  this->_M_deallocate();
  this->_M_impl._M_end_of_storage = (__q
         + ((__len
             + int(_S_word_bit) - 1)
            / int(_S_word_bit)));
  this->_M_impl._M_start = iterator(__q, 0);
       }
   }
      }

    void
    _M_insert_aux(iterator __position, bool __x)
    {
      if (this->_M_impl._M_finish._M_p != this->_M_impl._M_end_of_storage)
 {
   std::copy_backward(__position, this->_M_impl._M_finish,
        this->_M_impl._M_finish + 1);
   *__position = __x;
   ++this->_M_impl._M_finish;
 }
      else
 {
   const size_type __len = size() ? 2 * size()
                                  : static_cast<size_type>(_S_word_bit);
   _Bit_type * __q = this->_M_allocate(__len);
   iterator __i = _M_copy_aligned(begin(), __position,
      iterator(__q, 0));
   *__i++ = __x;
   this->_M_impl._M_finish = std::copy(__position, end(), __i);
   this->_M_deallocate();
   this->_M_impl._M_end_of_storage = (__q + ((__len
           + int(_S_word_bit) - 1)
          / int(_S_word_bit)));
   this->_M_impl._M_start = iterator(__q, 0);
 }
    }

    void
    _M_erase_at_end(iterator __pos)
    { this->_M_impl._M_finish = __pos; }
  };

}


namespace std __attribute__ ((__visibility__ ("default"))) {

  template<typename _Tp, typename _Alloc>
    void
    vector<_Tp, _Alloc>::
    reserve(size_type __n)
    {
      if (__n > this->max_size())
 __throw_length_error(("vector::reserve"));
      if (this->capacity() < __n)
 {
   const size_type __old_size = size();
   pointer __tmp = _M_allocate_and_copy(__n, this->_M_impl._M_start,
            this->_M_impl._M_finish);
   std::_Destroy(this->_M_impl._M_start, this->_M_impl._M_finish,
   _M_get_Tp_allocator());
   _M_deallocate(this->_M_impl._M_start,
   this->_M_impl._M_end_of_storage
   - this->_M_impl._M_start);
   this->_M_impl._M_start = __tmp;
   this->_M_impl._M_finish = __tmp + __old_size;
   this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;
 }
    }

  template<typename _Tp, typename _Alloc>
    typename vector<_Tp, _Alloc>::iterator
    vector<_Tp, _Alloc>::
    insert(iterator __position, const value_type& __x)
    {
      const size_type __n = __position - begin();
      if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage
   && __position == end())
 {
   this->_M_impl.construct(this->_M_impl._M_finish, __x);
   ++this->_M_impl._M_finish;
 }
      else
        _M_insert_aux(__position, __x);
      return iterator(this->_M_impl._M_start + __n);
    }

  template<typename _Tp, typename _Alloc>
    typename vector<_Tp, _Alloc>::iterator
    vector<_Tp, _Alloc>::
    erase(iterator __position)
    {
      if (__position + 1 != end())
        std::copy(__position + 1, end(), __position);
      --this->_M_impl._M_finish;
      this->_M_impl.destroy(this->_M_impl._M_finish);
      return __position;
    }

  template<typename _Tp, typename _Alloc>
    typename vector<_Tp, _Alloc>::iterator
    vector<_Tp, _Alloc>::
    erase(iterator __first, iterator __last)
    {
      if (__last != end())
 std::copy(__last, end(), __first);
      _M_erase_at_end(__first.base() + (end() - __last));
      return __first;
    }

  template<typename _Tp, typename _Alloc>
    vector<_Tp, _Alloc>&
    vector<_Tp, _Alloc>::
    operator=(const vector<_Tp, _Alloc>& __x)
    {
      if (&__x != this)
 {
   const size_type __xlen = __x.size();
   if (__xlen > capacity())
     {
       pointer __tmp = _M_allocate_and_copy(__xlen, __x.begin(),
         __x.end());
       std::_Destroy(this->_M_impl._M_start, this->_M_impl._M_finish,
       _M_get_Tp_allocator());
       _M_deallocate(this->_M_impl._M_start,
       this->_M_impl._M_end_of_storage
       - this->_M_impl._M_start);
       this->_M_impl._M_start = __tmp;
       this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __xlen;
     }
   else if (size() >= __xlen)
     {
       std::_Destroy(std::copy(__x.begin(), __x.end(), begin()),
       end(), _M_get_Tp_allocator());
     }
   else
     {
       std::copy(__x._M_impl._M_start, __x._M_impl._M_start + size(),
   this->_M_impl._M_start);
       std::__uninitialized_copy_a(__x._M_impl._M_start + size(),
       __x._M_impl._M_finish,
       this->_M_impl._M_finish,
       _M_get_Tp_allocator());
     }
   this->_M_impl._M_finish = this->_M_impl._M_start + __xlen;
 }
      return *this;
    }

  template<typename _Tp, typename _Alloc>
    void
    vector<_Tp, _Alloc>::
    _M_fill_assign(size_t __n, const value_type& __val)
    {
      if (__n > capacity())
 {
   vector __tmp(__n, __val, _M_get_Tp_allocator());
   __tmp.swap(*this);
 }
      else if (__n > size())
 {
   std::fill(begin(), end(), __val);
   std::__uninitialized_fill_n_a(this->_M_impl._M_finish,
     __n - size(), __val,
     _M_get_Tp_allocator());
   this->_M_impl._M_finish += __n - size();
 }
      else
        _M_erase_at_end(std::fill_n(this->_M_impl._M_start, __n, __val));
    }

  template<typename _Tp, typename _Alloc>
    template<typename _InputIterator>
      void
      vector<_Tp, _Alloc>::
      _M_assign_aux(_InputIterator __first, _InputIterator __last,
      std::input_iterator_tag)
      {
 pointer __cur(this->_M_impl._M_start);
 for (; __first != __last && __cur != this->_M_impl._M_finish;
      ++__cur, ++__first)
   *__cur = *__first;
 if (__first == __last)
   _M_erase_at_end(__cur);
 else
   insert(end(), __first, __last);
      }

  template<typename _Tp, typename _Alloc>
    template<typename _ForwardIterator>
      void
      vector<_Tp, _Alloc>::
      _M_assign_aux(_ForwardIterator __first, _ForwardIterator __last,
      std::forward_iterator_tag)
      {
 const size_type __len = std::distance(__first, __last);

 if (__len > capacity())
   {
     pointer __tmp(_M_allocate_and_copy(__len, __first, __last));
     std::_Destroy(this->_M_impl._M_start, this->_M_impl._M_finish,
     _M_get_Tp_allocator());
     _M_deallocate(this->_M_impl._M_start,
     this->_M_impl._M_end_of_storage
     - this->_M_impl._M_start);
     this->_M_impl._M_start = __tmp;
     this->_M_impl._M_finish = this->_M_impl._M_start + __len;
     this->_M_impl._M_end_of_storage = this->_M_impl._M_finish;
   }
 else if (size() >= __len)
   _M_erase_at_end(std::copy(__first, __last, this->_M_impl._M_start));
 else
   {
     _ForwardIterator __mid = __first;
     std::advance(__mid, size());
     std::copy(__first, __mid, this->_M_impl._M_start);
     this->_M_impl._M_finish =
       std::__uninitialized_copy_a(__mid, __last,
       this->_M_impl._M_finish,
       _M_get_Tp_allocator());
   }
      }

  template<typename _Tp, typename _Alloc>
    void
    vector<_Tp, _Alloc>::
    _M_insert_aux(iterator __position, const _Tp& __x)
    {
      if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage)
 {
   this->_M_impl.construct(this->_M_impl._M_finish,
      *(this->_M_impl._M_finish - 1));
   ++this->_M_impl._M_finish;
   _Tp __x_copy = __x;
   std::copy_backward(__position.base(),
        this->_M_impl._M_finish - 2,
        this->_M_impl._M_finish - 1);
   *__position = __x_copy;
 }
      else
 {
   const size_type __old_size = size();
   if (__old_size == this->max_size())
     __throw_length_error(("vector::_M_insert_aux"));




   size_type __len = __old_size != 0 ? 2 * __old_size : 1;
   if (__len < __old_size)
     __len = this->max_size();

   pointer __new_start(this->_M_allocate(__len));
   pointer __new_finish(__new_start);
   if (true)
     {
       __new_finish =
  std::__uninitialized_copy_a(this->_M_impl._M_start,
         __position.base(), __new_start,
         _M_get_Tp_allocator());
       this->_M_impl.construct(__new_finish, __x);
       ++__new_finish;
       __new_finish =
  std::__uninitialized_copy_a(__position.base(),
         this->_M_impl._M_finish,
         __new_finish,
         _M_get_Tp_allocator());
     }
   if (false)
     {
       std::_Destroy(__new_start, __new_finish, _M_get_Tp_allocator());
       _M_deallocate(__new_start, __len);
                              ;
     }
   std::_Destroy(this->_M_impl._M_start, this->_M_impl._M_finish,
   _M_get_Tp_allocator());
   _M_deallocate(this->_M_impl._M_start,
   this->_M_impl._M_end_of_storage
   - this->_M_impl._M_start);
   this->_M_impl._M_start = __new_start;
   this->_M_impl._M_finish = __new_finish;
   this->_M_impl._M_end_of_storage = __new_start + __len;
 }
    }

  template<typename _Tp, typename _Alloc>
    void
    vector<_Tp, _Alloc>::
    _M_fill_insert(iterator __position, size_type __n, const value_type& __x)
    {
      if (__n != 0)
 {
   if (size_type(this->_M_impl._M_end_of_storage
   - this->_M_impl._M_finish) >= __n)
     {
       value_type __x_copy = __x;
       const size_type __elems_after = end() - __position;
       pointer __old_finish(this->_M_impl._M_finish);
       if (__elems_after > __n)
  {
    std::__uninitialized_copy_a(this->_M_impl._M_finish - __n,
           this->_M_impl._M_finish,
           this->_M_impl._M_finish,
           _M_get_Tp_allocator());
    this->_M_impl._M_finish += __n;
    std::copy_backward(__position.base(), __old_finish - __n,
         __old_finish);
    std::fill(__position.base(), __position.base() + __n,
       __x_copy);
  }
       else
  {
    std::__uninitialized_fill_n_a(this->_M_impl._M_finish,
      __n - __elems_after,
      __x_copy,
      _M_get_Tp_allocator());
    this->_M_impl._M_finish += __n - __elems_after;
    std::__uninitialized_copy_a(__position.base(), __old_finish,
           this->_M_impl._M_finish,
           _M_get_Tp_allocator());
    this->_M_impl._M_finish += __elems_after;
    std::fill(__position.base(), __old_finish, __x_copy);
  }
     }
   else
     {
       const size_type __old_size = size();
       if (this->max_size() - __old_size < __n)
  __throw_length_error(("vector::_M_fill_insert"));


       size_type __len = __old_size + std::max(__old_size, __n);
       if (__len < __old_size)
  __len = this->max_size();

       pointer __new_start(this->_M_allocate(__len));
       pointer __new_finish(__new_start);
       if (true)
  {
    __new_finish =
      std::__uninitialized_copy_a(this->_M_impl._M_start,
      __position.base(),
      __new_start,
      _M_get_Tp_allocator());
    std::__uninitialized_fill_n_a(__new_finish, __n, __x,
      _M_get_Tp_allocator());
    __new_finish += __n;
    __new_finish =
      std::__uninitialized_copy_a(__position.base(),
      this->_M_impl._M_finish,
      __new_finish,
      _M_get_Tp_allocator());
  }
       if (false)
  {
    std::_Destroy(__new_start, __new_finish,
    _M_get_Tp_allocator());
    _M_deallocate(__new_start, __len);
                           ;
  }
       std::_Destroy(this->_M_impl._M_start, this->_M_impl._M_finish,
       _M_get_Tp_allocator());
       _M_deallocate(this->_M_impl._M_start,
       this->_M_impl._M_end_of_storage
       - this->_M_impl._M_start);
       this->_M_impl._M_start = __new_start;
       this->_M_impl._M_finish = __new_finish;
       this->_M_impl._M_end_of_storage = __new_start + __len;
     }
 }
    }

  template<typename _Tp, typename _Alloc> template<typename _InputIterator>
    void
    vector<_Tp, _Alloc>::
    _M_range_insert(iterator __pos, _InputIterator __first,
      _InputIterator __last, std::input_iterator_tag)
    {
      for (; __first != __last; ++__first)
 {
   __pos = insert(__pos, *__first);
   ++__pos;
 }
    }

  template<typename _Tp, typename _Alloc>
    template<typename _ForwardIterator>
      void
      vector<_Tp, _Alloc>::
      _M_range_insert(iterator __position, _ForwardIterator __first,
        _ForwardIterator __last, std::forward_iterator_tag)
      {
 if (__first != __last)
   {
     const size_type __n = std::distance(__first, __last);
     if (size_type(this->_M_impl._M_end_of_storage
     - this->_M_impl._M_finish) >= __n)
       {
  const size_type __elems_after = end() - __position;
  pointer __old_finish(this->_M_impl._M_finish);
  if (__elems_after > __n)
    {
      std::__uninitialized_copy_a(this->_M_impl._M_finish - __n,
      this->_M_impl._M_finish,
      this->_M_impl._M_finish,
      _M_get_Tp_allocator());
      this->_M_impl._M_finish += __n;
      std::copy_backward(__position.base(), __old_finish - __n,
           __old_finish);
      std::copy(__first, __last, __position);
    }
  else
    {
      _ForwardIterator __mid = __first;
      std::advance(__mid, __elems_after);
      std::__uninitialized_copy_a(__mid, __last,
      this->_M_impl._M_finish,
      _M_get_Tp_allocator());
      this->_M_impl._M_finish += __n - __elems_after;
      std::__uninitialized_copy_a(__position.base(),
      __old_finish,
      this->_M_impl._M_finish,
      _M_get_Tp_allocator());
      this->_M_impl._M_finish += __elems_after;
      std::copy(__first, __mid, __position);
    }
       }
     else
       {
  const size_type __old_size = size();
  if (this->max_size() - __old_size < __n)
    __throw_length_error(("vector::_M_range_insert"));


  size_type __len = __old_size + std::max(__old_size, __n);
  if (__len < __old_size)
    __len = this->max_size();

  pointer __new_start(this->_M_allocate(__len));
  pointer __new_finish(__new_start);
  if (true)
    {
      __new_finish =
        std::__uninitialized_copy_a(this->_M_impl._M_start,
        __position.base(),
        __new_start,
        _M_get_Tp_allocator());
      __new_finish =
        std::__uninitialized_copy_a(__first, __last, __new_finish,
        _M_get_Tp_allocator());
      __new_finish =
        std::__uninitialized_copy_a(__position.base(),
        this->_M_impl._M_finish,
        __new_finish,
        _M_get_Tp_allocator());
    }
  if (false)
    {
      std::_Destroy(__new_start, __new_finish,
      _M_get_Tp_allocator());
      _M_deallocate(__new_start, __len);
                             ;
    }
  std::_Destroy(this->_M_impl._M_start, this->_M_impl._M_finish,
         _M_get_Tp_allocator());
  _M_deallocate(this->_M_impl._M_start,
         this->_M_impl._M_end_of_storage
         - this->_M_impl._M_start);
  this->_M_impl._M_start = __new_start;
  this->_M_impl._M_finish = __new_finish;
  this->_M_impl._M_end_of_storage = __new_start + __len;
       }
   }
      }

}

namespace llvm {

template <typename T> class SmallVectorImpl;
class AliasAnalysis;
class TargetInstrInfo;
class TargetRegisterClass;
class TargetRegisterInfo;
class MachineFunction;
class MachineMemOperand;




class MachineInstr : public ilist_node<MachineInstr> {
public:
  typedef MachineMemOperand **mmo_iterator;





  enum CommentFlag {
    ReloadReuse = 0x1
  };

  enum MIFlag {
    NoFlags = 0,
    FrameSetup = 1 << 0

  };
private:
  const MCInstrDesc *MCID;

  uint8_t Flags;



  uint8_t AsmPrinterFlags;






  std::vector<MachineOperand> Operands;
  mmo_iterator MemRefs;
  mmo_iterator MemRefsEnd;
  MachineBasicBlock *Parent;
  DebugLoc debugLoc;

  MachineInstr(const MachineInstr&);
  void operator=(const MachineInstr&);


  friend struct ilist_traits<MachineInstr>;
  friend struct ilist_traits<MachineBasicBlock>;
  void setParent(MachineBasicBlock *P) { Parent = P; }



  MachineInstr(MachineFunction &, const MachineInstr &);



  MachineInstr();
  explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);




  MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);




  explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
                        bool NoImp = false);




  MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
               const MCInstrDesc &MCID);

  ~MachineInstr();


  friend class MachineFunction;

public:
  const MachineBasicBlock* getParent() const { return Parent; }
  MachineBasicBlock* getParent() { return Parent; }



  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }



  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }



  bool getAsmPrinterFlag(CommentFlag Flag) const {
    return AsmPrinterFlags & Flag;
  }



  void setAsmPrinterFlag(CommentFlag Flag) {
    AsmPrinterFlags |= (uint8_t)Flag;
  }


  uint8_t getFlags() const {
    return Flags;
  }


  bool getFlag(MIFlag Flag) const {
    return Flags & Flag;
  }


  void setFlag(MIFlag Flag) {
    Flags |= (uint8_t)Flag;
  }

  void setFlags(unsigned flags) {
    Flags = flags;
  }



  void clearAsmPrinterFlag(CommentFlag Flag) {
    AsmPrinterFlags &= ~Flag;
  }



  DebugLoc getDebugLoc() const { return debugLoc; }
  void emitError(StringRef Msg) const;



  const MCInstrDesc &getDesc() const { return *MCID; }



  int getOpcode() const { return MCID->Opcode; }



  unsigned getNumOperands() const { return (unsigned)Operands.size(); }

  const MachineOperand& getOperand(unsigned i) const {
    ((i < getNumOperands() && "getOperand() out of range!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineInstr.h", 202, "i < getNumOperands() && \"getOperand() out of range!\""));
    return Operands[i];
  }
  MachineOperand& getOperand(unsigned i) {
    ((i < getNumOperands() && "getOperand() out of range!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/MachineInstr.h", 206, "i < getNumOperands() && \"getOperand() out of range!\""));
    return Operands[i];
  }



  unsigned getNumExplicitOperands() const;


  typedef std::vector<MachineOperand>::iterator mop_iterator;
  typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;

  mop_iterator operands_begin() { return Operands.begin(); }
  mop_iterator operands_end() { return Operands.end(); }

  const_mop_iterator operands_begin() const { return Operands.begin(); }
  const_mop_iterator operands_end() const { return Operands.end(); }


  mmo_iterator memoperands_begin() const { return MemRefs; }
  mmo_iterator memoperands_end() const { return MemRefsEnd; }
  bool memoperands_empty() const { return MemRefsEnd == MemRefs; }



  bool hasOneMemOperand() const {
    return MemRefsEnd - MemRefs == 1;
  }

  enum MICheckType {
    CheckDefs,
    CheckKillDead,
    IgnoreDefs,
    IgnoreVRegDefs
  };



  bool isIdenticalTo(const MachineInstr *Other,
                     MICheckType Check = CheckDefs) const;



  MachineInstr *removeFromParent();



  void eraseFromParent();



  bool isLabel() const {
    return getOpcode() == TargetOpcode::PROLOG_LABEL ||
           getOpcode() == TargetOpcode::EH_LABEL ||
           getOpcode() == TargetOpcode::GC_LABEL;
  }

  bool isPrologLabel() const {
    return getOpcode() == TargetOpcode::PROLOG_LABEL;
  }
  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }

  bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
  bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
  bool isStackAligningInlineAsm() const;
  bool isInsertSubreg() const {
    return getOpcode() == TargetOpcode::INSERT_SUBREG;
  }
  bool isSubregToReg() const {
    return getOpcode() == TargetOpcode::SUBREG_TO_REG;
  }
  bool isRegSequence() const {
    return getOpcode() == TargetOpcode::REG_SEQUENCE;
  }
  bool isCopy() const {
    return getOpcode() == TargetOpcode::COPY;
  }
  bool isFullCopy() const {
    return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
  }



  bool isCopyLike() const {
    return isCopy() || isSubregToReg();
  }


  bool isIdentityCopy() const {
    return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
      getOperand(0).getSubReg() == getOperand(1).getSubReg();
  }






  bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = __null) const {
    return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
  }




  bool readsVirtualRegister(unsigned Reg) const {
    return readsWritesVirtualRegister(Reg).first;
  }





  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
                                      SmallVectorImpl<unsigned> *Ops = 0) const;




  bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = __null) const {
    return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
  }





  bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=__null) const {
    return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
  }




  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
    return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
  }




  bool registerDefIsDead(unsigned Reg,
                         const TargetRegisterInfo *TRI = __null) const {
    return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
  }




  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
                                const TargetRegisterInfo *TRI = __null) const;



  MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
                                         const TargetRegisterInfo *TRI = __null) {
    int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
    return (Idx == -1) ? __null : &getOperand(Idx);
  }






  int findRegisterDefOperandIdx(unsigned Reg,
                                bool isDead = false, bool Overlap = false,
                                const TargetRegisterInfo *TRI = __null) const;



  MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
                                         const TargetRegisterInfo *TRI = __null) {
    int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
    return (Idx == -1) ? __null : &getOperand(Idx);
  }




  int findFirstPredOperandIdx() const;
  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
  const TargetRegisterClass*
  getRegClassConstraint(unsigned OpIdx,
                        const TargetInstrInfo *TII,
                        const TargetRegisterInfo *TRI) const;





  bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;




  bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;



  void clearKillInfo();



  void copyKillDeadInfo(const MachineInstr *MI);


  void copyPredicates(const MachineInstr *MI);



  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
                          const TargetRegisterInfo &RegInfo);





  bool addRegisterKilled(unsigned IncomingReg,
                         const TargetRegisterInfo *RegInfo,
                         bool AddIfNotFound = false);





  bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
                       bool AddIfNotFound = false);



  void addRegisterDefined(unsigned IncomingReg,
                          const TargetRegisterInfo *RegInfo = 0);



  void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
                             const TargetRegisterInfo &TRI);




  bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
                    bool &SawStore) const;



  bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
                     unsigned DstReg) const;





  bool hasVolatileMemoryRef() const;






  bool isInvariantLoad(AliasAnalysis *AA) const;




  unsigned isConstantValuePHI() const;
  bool hasUnmodeledSideEffects() const;



  bool allDefsAreDead() const;



  void copyImplicitOps(const MachineInstr *MI);




  void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
  void dump() const;
  void addOperand(const MachineOperand &Op);




  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }




  void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }




  void RemoveOperand(unsigned i);




  void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);



  void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
    MemRefs = NewMemRefs;
    MemRefsEnd = NewMemRefsEnd;
  }

private:



  MachineRegisterInfo *getRegInfo();



  void addImplicitDefUseOperands();




  void RemoveRegOperandsFromUseLists();




  void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
};





struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
  static inline MachineInstr *getEmptyKey() {
    return 0;
  }

  static inline MachineInstr *getTombstoneKey() {
    return reinterpret_cast<MachineInstr*>(-1);
  }

  static unsigned getHashValue(const MachineInstr* const &MI);

  static bool isEqual(const MachineInstr* const &LHS,
                      const MachineInstr* const &RHS) {
    if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
        LHS == getEmptyKey() || LHS == getTombstoneKey())
      return LHS == RHS;
    return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
  }
};




inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
  MI.print(OS);
  return OS;
}

}
namespace llvm {




template<class GraphType>
struct GraphTraits {
  typedef typename GraphType::UnknownGraphTypeError NodeType;
};
template <class GraphType>
struct Inverse {
  const GraphType &Graph;

  inline Inverse(const GraphType &G) : Graph(G) {}
};



template<class T>
struct GraphTraits<Inverse<Inverse<T> > > {
  typedef typename GraphTraits<T>::NodeType NodeType;
  typedef typename GraphTraits<T>::ChildIteratorType ChildIteratorType;

  static NodeType *getEntryNode(Inverse<Inverse<T> > *G) {
    return GraphTraits<T>::getEntryNode(G->Graph.Graph);
  }

  static ChildIteratorType child_begin(NodeType* N) {
    return GraphTraits<T>::child_begin(N);
  }

  static ChildIteratorType child_end(NodeType* N) {
    return GraphTraits<T>::child_end(N);
  }
};

}



namespace llvm {

class Pass;
class BasicBlock;
class MachineFunction;
class MCSymbol;
class SlotIndexes;
class StringRef;
class raw_ostream;
class MachineBranchProbabilityInfo;

template <>
struct ilist_traits<MachineInstr> : public ilist_default_traits<MachineInstr> {
private:
  mutable ilist_half_node<MachineInstr> Sentinel;


  friend class MachineBasicBlock;
  MachineBasicBlock* Parent;

public:
  MachineInstr *createSentinel() const {
    return static_cast<MachineInstr*>(&Sentinel);
  }
  void destroySentinel(MachineInstr *) const {}

  MachineInstr *provideInitialHead() const { return createSentinel(); }
  MachineInstr *ensureHead(MachineInstr*) const { return createSentinel(); }
  static void noteHead(MachineInstr*, MachineInstr*) {}

  void addNodeToList(MachineInstr* N);
  void removeNodeFromList(MachineInstr* N);
  void transferNodesFromList(ilist_traits &SrcTraits,
                             ilist_iterator<MachineInstr> first,
                             ilist_iterator<MachineInstr> last);
  void deleteNode(MachineInstr *N);
private:
  void createNode(const MachineInstr &);
};

class MachineBasicBlock : public ilist_node<MachineBasicBlock> {
  typedef ilist<MachineInstr> Instructions;
  Instructions Insts;
  const BasicBlock *BB;
  int Number;
  MachineFunction *xParent;



  std::vector<MachineBasicBlock *> Predecessors;
  std::vector<MachineBasicBlock *> Successors;





  std::vector<uint32_t> Weights;
  typedef std::vector<uint32_t>::iterator weight_iterator;



  std::vector<unsigned> LiveIns;



  unsigned Alignment;



  bool IsLandingPad;



  bool AddressTaken;


  MachineBasicBlock() {}

  explicit MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb);

  ~MachineBasicBlock();


  friend class MachineFunction;

public:




  const BasicBlock *getBasicBlock() const { return BB; }



  StringRef getName() const;



  bool hasAddressTaken() const { return AddressTaken; }



  void setHasAddressTaken() { AddressTaken = true; }



  const MachineFunction *getParent() const { return xParent; }
  MachineFunction *getParent() { return xParent; }

  typedef Instructions::iterator iterator;
  typedef Instructions::const_iterator const_iterator;
  typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
  typedef std::reverse_iterator<iterator> reverse_iterator;

  unsigned size() const { return (unsigned)Insts.size(); }
  bool empty() const { return Insts.empty(); }

  MachineInstr& front() { return Insts.front(); }
  MachineInstr& back() { return Insts.back(); }
  const MachineInstr& front() const { return Insts.front(); }
  const MachineInstr& back() const { return Insts.back(); }

  iterator begin() { return Insts.begin(); }
  const_iterator begin() const { return Insts.begin(); }
  iterator end() { return Insts.end(); }
  const_iterator end() const { return Insts.end(); }
  reverse_iterator rbegin() { return Insts.rbegin(); }
  const_reverse_iterator rbegin() const { return Insts.rbegin(); }
  reverse_iterator rend () { return Insts.rend(); }
  const_reverse_iterator rend () const { return Insts.rend(); }


  typedef std::vector<MachineBasicBlock *>::iterator pred_iterator;
  typedef std::vector<MachineBasicBlock *>::const_iterator const_pred_iterator;
  typedef std::vector<MachineBasicBlock *>::iterator succ_iterator;
  typedef std::vector<MachineBasicBlock *>::const_iterator const_succ_iterator;
  typedef std::vector<MachineBasicBlock *>::reverse_iterator
                                                         pred_reverse_iterator;
  typedef std::vector<MachineBasicBlock *>::const_reverse_iterator
                                                   const_pred_reverse_iterator;
  typedef std::vector<MachineBasicBlock *>::reverse_iterator
                                                         succ_reverse_iterator;
  typedef std::vector<MachineBasicBlock *>::const_reverse_iterator
                                                   const_succ_reverse_iterator;

  pred_iterator pred_begin() { return Predecessors.begin(); }
  const_pred_iterator pred_begin() const { return Predecessors.begin(); }
  pred_iterator pred_end() { return Predecessors.end(); }
  const_pred_iterator pred_end() const { return Predecessors.end(); }
  pred_reverse_iterator pred_rbegin()
                                          { return Predecessors.rbegin();}
  const_pred_reverse_iterator pred_rbegin() const
                                          { return Predecessors.rbegin();}
  pred_reverse_iterator pred_rend()
                                          { return Predecessors.rend(); }
  const_pred_reverse_iterator pred_rend() const
                                          { return Predecessors.rend(); }
  unsigned pred_size() const {
    return (unsigned)Predecessors.size();
  }
  bool pred_empty() const { return Predecessors.empty(); }
  succ_iterator succ_begin() { return Successors.begin(); }
  const_succ_iterator succ_begin() const { return Successors.begin(); }
  succ_iterator succ_end() { return Successors.end(); }
  const_succ_iterator succ_end() const { return Successors.end(); }
  succ_reverse_iterator succ_rbegin()
                                          { return Successors.rbegin(); }
  const_succ_reverse_iterator succ_rbegin() const
                                          { return Successors.rbegin(); }
  succ_reverse_iterator succ_rend()
                                          { return Successors.rend(); }
  const_succ_reverse_iterator succ_rend() const
                                          { return Successors.rend(); }
  unsigned succ_size() const {
    return (unsigned)Successors.size();
  }
  bool succ_empty() const { return Successors.empty(); }





  void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }



  void removeLiveIn(unsigned Reg);



  bool isLiveIn(unsigned Reg) const;



  typedef std::vector<unsigned>::const_iterator livein_iterator;
  livein_iterator livein_begin() const { return LiveIns.begin(); }
  livein_iterator livein_end() const { return LiveIns.end(); }
  bool livein_empty() const { return LiveIns.empty(); }



  unsigned getAlignment() const { return Alignment; }



  void setAlignment(unsigned Align) { Alignment = Align; }



  bool isLandingPad() const { return IsLandingPad; }



  void setIsLandingPad(bool V = true) { IsLandingPad = V; }



  const MachineBasicBlock *getLandingPadSuccessor() const;






  void moveBefore(MachineBasicBlock *NewAfter);
  void moveAfter(MachineBasicBlock *NewBefore);





  void updateTerminator();
  void addSuccessor(MachineBasicBlock *succ, uint32_t weight = 0);




  void removeSuccessor(MachineBasicBlock *succ);





  succ_iterator removeSuccessor(succ_iterator I);



  void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New);





  void transferSuccessors(MachineBasicBlock *fromMBB);




  void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB);



  bool isSuccessor(const MachineBasicBlock *MBB) const;






  bool isLayoutSuccessor(const MachineBasicBlock *MBB) const;





  bool canFallThrough();






  iterator getFirstNonPHI();




  iterator SkipPHIsAndLabels(iterator I);




  iterator getFirstTerminator();

  const_iterator getFirstTerminator() const {
    return const_cast<MachineBasicBlock*>(this)->getFirstTerminator();
  }



  iterator getLastNonDebugInstr();

  const_iterator getLastNonDebugInstr() const {
    return const_cast<MachineBasicBlock*>(this)->getLastNonDebugInstr();
  }







  MachineBasicBlock *SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P);

  void pop_front() { Insts.pop_front(); }
  void pop_back() { Insts.pop_back(); }
  void push_back(MachineInstr *MI) { Insts.push_back(MI); }
  template<typename IT>
  void insert(iterator I, IT S, IT E) { Insts.insert(I, S, E); }
  iterator insert(iterator I, MachineInstr *M) { return Insts.insert(I, M); }
  iterator insertAfter(iterator I, MachineInstr *M) {
    return Insts.insertAfter(I, M);
  }




  iterator erase(iterator I) { return Insts.erase(I); }
  iterator erase(iterator I, iterator E) { return Insts.erase(I, E); }
  MachineInstr *remove(MachineInstr *I) { return Insts.remove(I); }
  void clear() { Insts.clear(); }



  void splice(iterator where, MachineBasicBlock *Other, iterator From) {
    Insts.splice(where, Other->Insts, From);
  }



  void splice(iterator where, MachineBasicBlock *Other, iterator From,
              iterator To) {
    Insts.splice(where, Other->Insts, From, To);
  }



  MachineBasicBlock *removeFromParent();



  void eraseFromParent();



  void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New);







  bool CorrectExtraCFGEdges(MachineBasicBlock *DestA,
                            MachineBasicBlock *DestB,
                            bool isCond);



  DebugLoc findDebugLoc(MachineBasicBlock::iterator &MBBI);


  void dump() const;
  void print(raw_ostream &OS, SlotIndexes* = 0) const;





  int getNumber() const { return Number; }
  void setNumber(int N) { Number = N; }



  MCSymbol *getSymbol() const;


private:


  weight_iterator getWeightIterator(succ_iterator I);

  friend class MachineBranchProbabilityInfo;




  uint32_t getSuccWeight(MachineBasicBlock *succ);



  friend struct ilist_traits<MachineBasicBlock>;







  void addPredecessor(MachineBasicBlock *pred);






  void removePredecessor(MachineBasicBlock *pred);
};

raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB);

void WriteAsOperand(raw_ostream &, const MachineBasicBlock*, bool t);


struct MBB2NumberFunctor :
  public std::unary_function<const MachineBasicBlock*, unsigned> {
  unsigned operator()(const MachineBasicBlock *MBB) const {
    return MBB->getNumber();
  }
};
template <> struct GraphTraits<MachineBasicBlock *> {
  typedef MachineBasicBlock NodeType;
  typedef MachineBasicBlock::succ_iterator ChildIteratorType;

  static NodeType *getEntryNode(MachineBasicBlock *BB) { return BB; }
  static inline ChildIteratorType child_begin(NodeType *N) {
    return N->succ_begin();
  }
  static inline ChildIteratorType child_end(NodeType *N) {
    return N->succ_end();
  }
};

template <> struct GraphTraits<const MachineBasicBlock *> {
  typedef const MachineBasicBlock NodeType;
  typedef MachineBasicBlock::const_succ_iterator ChildIteratorType;

  static NodeType *getEntryNode(const MachineBasicBlock *BB) { return BB; }
  static inline ChildIteratorType child_begin(NodeType *N) {
    return N->succ_begin();
  }
  static inline ChildIteratorType child_end(NodeType *N) {
    return N->succ_end();
  }
};







template <> struct GraphTraits<Inverse<MachineBasicBlock*> > {
  typedef MachineBasicBlock NodeType;
  typedef MachineBasicBlock::pred_iterator ChildIteratorType;
  static NodeType *getEntryNode(Inverse<MachineBasicBlock *> G) {
    return G.Graph;
  }
  static inline ChildIteratorType child_begin(NodeType *N) {
    return N->pred_begin();
  }
  static inline ChildIteratorType child_end(NodeType *N) {
    return N->pred_end();
  }
};

template <> struct GraphTraits<Inverse<const MachineBasicBlock*> > {
  typedef const MachineBasicBlock NodeType;
  typedef MachineBasicBlock::const_pred_iterator ChildIteratorType;
  static NodeType *getEntryNode(Inverse<const MachineBasicBlock*> G) {
    return G.Graph;
  }
  static inline ChildIteratorType child_begin(NodeType *N) {
    return N->pred_begin();
  }
  static inline ChildIteratorType child_end(NodeType *N) {
    return N->pred_end();
  }
};

}





namespace llvm {
  class Type;
  class LLVMContext;
  struct EVT;




  class MVT {
  public:
    enum SimpleValueType {


      Other = 0,
      i1 = 1,
      i8 = 2,
      i16 = 3,
      i32 = 4,
      i64 = 5,
      i128 = 6,

      FIRST_INTEGER_VALUETYPE = i1,
      LAST_INTEGER_VALUETYPE = i128,

      f32 = 7,
      f64 = 8,
      f80 = 9,
      f128 = 10,
      ppcf128 = 11,

      v2i8 = 12,
      v4i8 = 13,
      v8i8 = 14,
      v16i8 = 15,
      v32i8 = 16,
      v2i16 = 17,
      v4i16 = 18,
      v8i16 = 19,
      v16i16 = 20,
      v2i32 = 21,
      v4i32 = 22,
      v8i32 = 23,
      v1i64 = 24,
      v2i64 = 25,
      v4i64 = 26,
      v8i64 = 27,

      v2f32 = 28,
      v4f32 = 29,
      v8f32 = 30,
      v2f64 = 31,
      v4f64 = 32,

      FIRST_VECTOR_VALUETYPE = v2i8,
      LAST_VECTOR_VALUETYPE = v4f64,

      x86mmx = 33,

      Glue = 34,

      isVoid = 35,

      untyped = 36,



      LAST_VALUETYPE = 37,




      MAX_ALLOWED_VALUETYPE = 64,


      Metadata = 250,




      iPTRAny = 251,




      vAny = 252,




      fAny = 253,




      iAny = 254,



      iPTR = 255,


      LastSimpleValueType = 255,



      INVALID_SIMPLE_VALUE_TYPE = LastSimpleValueType + 1
    };

    SimpleValueType SimpleTy;

    MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {}
    MVT(SimpleValueType SVT) : SimpleTy(SVT) { }

    bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
    bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
    bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
    bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
    bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
    bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }


    bool isFloatingPoint() const {
      return ((SimpleTy >= MVT::f32 && SimpleTy <= MVT::ppcf128) ||
       (SimpleTy >= MVT::v2f32 && SimpleTy <= MVT::v4f64));
    }


    bool isInteger() const {
      return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
               SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
       (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64));
    }


    bool isVector() const {
      return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
              SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
    }


    bool isPow2VectorType() const {
      unsigned NElts = getVectorNumElements();
      return !(NElts & (NElts - 1));
    }



    MVT getPow2VectorType() const {
      if (isPow2VectorType())
        return *this;

      unsigned NElts = getVectorNumElements();
      unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
      return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
    }



    MVT getScalarType() const {
      return isVector() ? getVectorElementType() : *this;
    }

    MVT getVectorElementType() const {
      switch (SimpleTy) {
      default:
        return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
      case v2i8 :
      case v4i8 :
      case v8i8 :
      case v16i8:
      case v32i8: return i8;
      case v2i16:
      case v4i16:
      case v8i16:
      case v16i16: return i16;
      case v2i32:
      case v4i32:
      case v8i32: return i32;
      case v1i64:
      case v2i64:
      case v4i64:
      case v8i64: return i64;
      case v2f32:
      case v4f32:
      case v8f32: return f32;
      case v2f64:
      case v4f64: return f64;
      }
    }

    unsigned getVectorNumElements() const {
      switch (SimpleTy) {
      default:
        return ~0U;
      case v32i8: return 32;
      case v16i8:
      case v16i16: return 16;
      case v8i8 :
      case v8i16:
      case v8i32:
      case v8i64:
      case v8f32: return 8;
      case v4i8:
      case v4i16:
      case v4i32:
      case v4i64:
      case v4f32:
      case v4f64: return 4;
      case v2i8:
      case v2i16:
      case v2i32:
      case v2i64:
      case v2f32:
      case v2f64: return 2;
      case v1i64: return 1;
      }
    }

    unsigned getSizeInBits() const {
      switch (SimpleTy) {
      case iPTR:
        ((0 && "Value type size is target-dependent. Ask TLI.") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 245, "0 && \"Value type size is target-dependent. Ask TLI.\""));
      case iPTRAny:
      case iAny:
      case fAny:
        ((0 && "Value type is overloaded.") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 249, "0 && \"Value type is overloaded.\""));
      default:
        ((0 && "getSizeInBits called on extended MVT.") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 251, "0 && \"getSizeInBits called on extended MVT.\""));
      case i1 : return 1;
      case i8 : return 8;
      case i16 :
      case v2i8: return 16;
      case f32 :
      case i32 :
      case v4i8:
      case v2i16: return 32;
      case x86mmx:
      case f64 :
      case i64 :
      case v8i8:
      case v4i16:
      case v2i32:
      case v1i64:
      case v2f32: return 64;
      case f80 : return 80;
      case f128:
      case ppcf128:
      case i128:
      case v16i8:
      case v8i16:
      case v4i32:
      case v2i64:
      case v4f32:
      case v2f64: return 128;
      case v32i8:
      case v16i16:
      case v8i32:
      case v4i64:
      case v8f32:
      case v4f64: return 256;
      case v8i64: return 512;
      }
    }



    unsigned getStoreSize() const {
      return (getSizeInBits() + 7) / 8;
    }



    unsigned getStoreSizeInBits() const {
      return getStoreSize() * 8;
    }

    static MVT getFloatingPointVT(unsigned BitWidth) {
      switch (BitWidth) {
      default:
        ((false && "Bad bit width!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 303, "false && \"Bad bit width!\""));
      case 32:
        return MVT::f32;
      case 64:
        return MVT::f64;
      case 80:
        return MVT::f80;
      case 128:
        return MVT::f128;
      }
    }

    static MVT getIntegerVT(unsigned BitWidth) {
      switch (BitWidth) {
      default:
        return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
      case 1:
        return MVT::i1;
      case 8:
        return MVT::i8;
      case 16:
        return MVT::i16;
      case 32:
        return MVT::i32;
      case 64:
        return MVT::i64;
      case 128:
        return MVT::i128;
      }
    }

    static MVT getVectorVT(MVT VT, unsigned NumElements) {
      switch (VT.SimpleTy) {
      default:
        break;
      case MVT::i8:
        if (NumElements == 2) return MVT::v2i8;
        if (NumElements == 4) return MVT::v4i8;
        if (NumElements == 8) return MVT::v8i8;
        if (NumElements == 16) return MVT::v16i8;
        if (NumElements == 32) return MVT::v32i8;
        break;
      case MVT::i16:
        if (NumElements == 2) return MVT::v2i16;
        if (NumElements == 4) return MVT::v4i16;
        if (NumElements == 8) return MVT::v8i16;
        if (NumElements == 16) return MVT::v16i16;
        break;
      case MVT::i32:
        if (NumElements == 2) return MVT::v2i32;
        if (NumElements == 4) return MVT::v4i32;
        if (NumElements == 8) return MVT::v8i32;
        break;
      case MVT::i64:
        if (NumElements == 1) return MVT::v1i64;
        if (NumElements == 2) return MVT::v2i64;
        if (NumElements == 4) return MVT::v4i64;
        if (NumElements == 8) return MVT::v8i64;
        break;
      case MVT::f32:
        if (NumElements == 2) return MVT::v2f32;
        if (NumElements == 4) return MVT::v4f32;
        if (NumElements == 8) return MVT::v8f32;
        break;
      case MVT::f64:
        if (NumElements == 2) return MVT::v2f64;
        if (NumElements == 4) return MVT::v4f64;
        break;
      }
      return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
    }
  };





  struct EVT {
  private:
    MVT V;
    Type *LLVMTy;

  public:
    EVT() : V((MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE)),
            LLVMTy(0) {}
    EVT(MVT::SimpleValueType SVT) : V(SVT), LLVMTy(0) { }
    EVT(MVT S) : V(S), LLVMTy(0) {}

    bool operator==(EVT VT) const {
      return !(*this != VT);
    }
    bool operator!=(EVT VT) const {
      if (V.SimpleTy != VT.V.SimpleTy)
        return true;
      if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
        return LLVMTy != VT.LLVMTy;
      return false;
    }




    static EVT getFloatingPointVT(unsigned BitWidth) {
      return MVT::getFloatingPointVT(BitWidth);
    }



    static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth) {
      MVT M = MVT::getIntegerVT(BitWidth);
      if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
        return M;
      return getExtendedIntegerVT(Context, BitWidth);
    }



    static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) {
      MVT M = MVT::getVectorVT(VT.V, NumElements);
      if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
        return M;
      return getExtendedVectorVT(Context, VT, NumElements);
    }



    static EVT getIntVectorWithNumElements(LLVMContext &C, unsigned NumElts) {
      switch (NumElts) {
      default: return getVectorVT(C, MVT::i8, NumElts);
      case 1: return MVT::v1i64;
      case 2: return MVT::v2i32;
      case 4: return MVT::v4i16;
      case 8: return MVT::v8i8;
      case 16: return MVT::v16i8;
      }
      return MVT::INVALID_SIMPLE_VALUE_TYPE;
    }




    EVT changeVectorElementTypeToInteger() const {
      if (!isSimple())
        return changeExtendedVectorElementTypeToInteger();
      MVT EltTy = getSimpleVT().getVectorElementType();
      unsigned BitWidth = EltTy.getSizeInBits();
      MVT IntTy = MVT::getIntegerVT(BitWidth);
      MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements());
      ((VecTy != MVT::INVALID_SIMPLE_VALUE_TYPE && "Simple vector VT not representable by simple integer vector VT!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 452, "VecTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""));

      return VecTy;
    }



    bool isSimple() const {
      return V.SimpleTy <= MVT::LastSimpleValueType;
    }



    bool isExtended() const {
      return !isSimple();
    }


    bool isFloatingPoint() const {
      return isSimple() ? V.isFloatingPoint() : isExtendedFloatingPoint();
    }


    bool isInteger() const {
      return isSimple() ? V.isInteger() : isExtendedInteger();
    }


    bool isVector() const {
      return isSimple() ? V.isVector() : isExtendedVector();
    }


    bool is64BitVector() const {
      if (!isSimple())
        return isExtended64BitVector();

      return (V == MVT::v8i8 || V==MVT::v4i16 || V==MVT::v2i32 ||
              V == MVT::v1i64 || V==MVT::v2f32);
    }


    bool is128BitVector() const {
      if (!isSimple())
        return isExtended128BitVector();
      return (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
              V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64);
    }


    inline bool is256BitVector() const {
      if (!isSimple())
        return isExtended256BitVector();
      return (V == MVT::v8f32 || V == MVT::v4f64 || V == MVT::v32i8 ||
              V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64);
    }


    inline bool is512BitVector() const {
      return isSimple() ? (V == MVT::v8i64) : isExtended512BitVector();
    }


    bool isOverloaded() const {
      return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
    }


    bool isByteSized() const {
      return (getSizeInBits() & 7) == 0;
    }


    bool isRound() const {
      unsigned BitSize = getSizeInBits();
      return BitSize >= 8 && !(BitSize & (BitSize - 1));
    }


    bool bitsEq(EVT VT) const {
      if (EVT::operator==(VT)) return true;
      return getSizeInBits() == VT.getSizeInBits();
    }


    bool bitsGT(EVT VT) const {
      if (EVT::operator==(VT)) return false;
      return getSizeInBits() > VT.getSizeInBits();
    }


    bool bitsGE(EVT VT) const {
      if (EVT::operator==(VT)) return true;
      return getSizeInBits() >= VT.getSizeInBits();
    }


    bool bitsLT(EVT VT) const {
      if (EVT::operator==(VT)) return false;
      return getSizeInBits() < VT.getSizeInBits();
    }


    bool bitsLE(EVT VT) const {
      if (EVT::operator==(VT)) return true;
      return getSizeInBits() <= VT.getSizeInBits();
    }




    MVT getSimpleVT() const {
      ((isSimple() && "Expected a SimpleValueType!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 563, "isSimple() && \"Expected a SimpleValueType!\""));
      return V;
    }



    EVT getScalarType() const {
      return isVector() ? getVectorElementType() : *this;
    }



    EVT getVectorElementType() const {
      ((isVector() && "Invalid vector type!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 576, "isVector() && \"Invalid vector type!\""));
      if (isSimple())
        return V.getVectorElementType();
      return getExtendedVectorElementType();
    }



    unsigned getVectorNumElements() const {
      ((isVector() && "Invalid vector type!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 585, "isVector() && \"Invalid vector type!\""));
      if (isSimple())
        return V.getVectorNumElements();
      return getExtendedVectorNumElements();
    }


    unsigned getSizeInBits() const {
      if (isSimple())
        return V.getSizeInBits();
      return getExtendedSizeInBits();
    }



    unsigned getStoreSize() const {
      return (getSizeInBits() + 7) / 8;
    }



    unsigned getStoreSizeInBits() const {
      return getStoreSize() * 8;
    }




    EVT getRoundIntegerType(LLVMContext &Context) const {
      ((isInteger() && !isVector() && "Invalid integer type!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 614, "isInteger() && !isVector() && \"Invalid integer type!\""));
      unsigned BitWidth = getSizeInBits();
      if (BitWidth <= 8)
        return EVT(MVT::i8);
      return getIntegerVT(Context, 1 << Log2_32_Ceil(BitWidth));
    }





    EVT getHalfSizedIntegerVT(LLVMContext &Context) const {
      ((isInteger() && !isVector() && "Invalid integer type!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/CodeGen/ValueTypes.h", 626, "isInteger() && !isVector() && \"Invalid integer type!\""));
      unsigned EVTSize = getSizeInBits();
      for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
          IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) {
        EVT HalfVT = EVT((MVT::SimpleValueType)IntVT);
        if (HalfVT.getSizeInBits() * 2 >= EVTSize)
          return HalfVT;
      }
      return getIntegerVT(Context, (EVTSize + 1) / 2);
    }


    bool isPow2VectorType() const {
      unsigned NElts = getVectorNumElements();
      return !(NElts & (NElts - 1));
    }



    EVT getPow2VectorType(LLVMContext &Context) const {
      if (!isPow2VectorType()) {
        unsigned NElts = getVectorNumElements();
        unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
        return EVT::getVectorVT(Context, getVectorElementType(), Pow2NElts);
      }
      else {
        return *this;
      }
    }



    std::string getEVTString() const;




    Type *getTypeForEVT(LLVMContext &Context) const;




    static EVT getEVT(Type *Ty, bool HandleUnknown = false);

    intptr_t getRawBits() {
      if (isSimple())
        return V.SimpleTy;
      else
        return (intptr_t)(LLVMTy);
    }



    struct compareRawBits {
      bool operator()(EVT L, EVT R) const {
        if (L.V.SimpleTy == R.V.SimpleTy)
          return L.LLVMTy < R.LLVMTy;
        else
          return L.V.SimpleTy < R.V.SimpleTy;
      }
    };

  private:



    EVT changeExtendedVectorElementTypeToInteger() const;
    static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth);
    static EVT getExtendedVectorVT(LLVMContext &C, EVT VT,
                                   unsigned NumElements);
    bool isExtendedFloatingPoint() const;
    bool isExtendedInteger() const;
    bool isExtendedVector() const;
    bool isExtended64BitVector() const;
    bool isExtended128BitVector() const;
    bool isExtended256BitVector() const;
    bool isExtended512BitVector() const;
    EVT getExtendedVectorElementType() const;
    unsigned getExtendedVectorNumElements() const;
    unsigned getExtendedSizeInBits() const;
  };

}

namespace llvm {



class SmallVectorBase {
protected:
  void *BeginX, *EndX, *CapacityX;






  union U {
    double D;
    long double LD;
    long long L;
    void *P;
  } FirstEl;


protected:
  SmallVectorBase(size_t Size)
    : BeginX(&FirstEl), EndX(&FirstEl), CapacityX((char*)&FirstEl+Size) {}



  bool isSmall() const {
    return BeginX == static_cast<const void*>(&FirstEl);
  }



  void grow_pod(size_t MinSizeInBytes, size_t TSize);

public:

  size_t size_in_bytes() const {
    return size_t((char*)EndX - (char*)BeginX);
  }


  size_t capacity_in_bytes() const {
    return size_t((char*)CapacityX - (char*)BeginX);
  }

  bool empty() const { return BeginX == EndX; }
};


template <typename T>
class SmallVectorTemplateCommon : public SmallVectorBase {
protected:
  void setEnd(T *P) { this->EndX = P; }
public:
  SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(Size) {}

  typedef size_t size_type;
  typedef ptrdiff_t difference_type;
  typedef T value_type;
  typedef T *iterator;
  typedef const T *const_iterator;

  typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
  typedef std::reverse_iterator<iterator> reverse_iterator;

  typedef T &reference;
  typedef const T &const_reference;
  typedef T *pointer;
  typedef const T *const_pointer;


  iterator begin() { return (iterator)this->BeginX; }
  const_iterator begin() const { return (const_iterator)this->BeginX; }
  iterator end() { return (iterator)this->EndX; }
  const_iterator end() const { return (const_iterator)this->EndX; }
protected:
  iterator capacity_ptr() { return (iterator)this->CapacityX; }
  const_iterator capacity_ptr() const { return (const_iterator)this->CapacityX;}
public:


  reverse_iterator rbegin() { return reverse_iterator(end()); }
  const_reverse_iterator rbegin() const{ return const_reverse_iterator(end()); }
  reverse_iterator rend() { return reverse_iterator(begin()); }
  const_reverse_iterator rend() const { return const_reverse_iterator(begin());}

  size_type size() const { return end()-begin(); }
  size_type max_size() const { return size_type(-1) / sizeof(T); }



  size_t capacity() const { return capacity_ptr() - begin(); }


  pointer data() { return pointer(begin()); }

  const_pointer data() const { return const_pointer(begin()); }

  reference operator[](unsigned idx) {
    ((begin() + idx < end()) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/SmallVector.h", 150, "begin() + idx < end()"));
    return begin()[idx];
  }
  const_reference operator[](unsigned idx) const {
    ((begin() + idx < end()) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/SmallVector.h", 154, "begin() + idx < end()"));
    return begin()[idx];
  }

  reference front() {
    return begin()[0];
  }
  const_reference front() const {
    return begin()[0];
  }

  reference back() {
    return end()[-1];
  }
  const_reference back() const {
    return end()[-1];
  }
};



template <typename T, bool isPodLike>
class SmallVectorTemplateBase : public SmallVectorTemplateCommon<T> {
public:
  SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}

  static void destroy_range(T *S, T *E) {
    while (S != E) {
      --E;
      E->~T();
    }
  }



  template<typename It1, typename It2>
  static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
    std::uninitialized_copy(I, E, Dest);
  }



  void grow(size_t MinSize = 0);
};


template <typename T, bool isPodLike>
void SmallVectorTemplateBase<T, isPodLike>::grow(size_t MinSize) {
  size_t CurCapacity = this->capacity();
  size_t CurSize = this->size();
  size_t NewCapacity = 2*CurCapacity + 1;
  if (NewCapacity < MinSize)
    NewCapacity = MinSize;
  T *NewElts = static_cast<T*>(malloc(NewCapacity*sizeof(T)));


  this->uninitialized_copy(this->begin(), this->end(), NewElts);


  destroy_range(this->begin(), this->end());


  if (!this->isSmall())
    free(this->begin());

  this->setEnd(NewElts+CurSize);
  this->BeginX = NewElts;
  this->CapacityX = this->begin()+NewCapacity;
}




template <typename T>
class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T> {
public:
  SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}


  static void destroy_range(T *, T *) {}



  template<typename It1, typename It2>
  static void uninitialized_copy(It1 I, It1 E, It2 Dest) {

    std::uninitialized_copy(I, E, Dest);
  }



  template<typename T1, typename T2>
  static void uninitialized_copy(T1 *I, T1 *E, T2 *Dest) {



    memcpy(Dest, I, (E-I)*sizeof(T));
  }



  void grow(size_t MinSize = 0) {
    this->grow_pod(MinSize*sizeof(T), sizeof(T));
  }
};





template <typename T>
class SmallVectorImpl : public SmallVectorTemplateBase<T, isPodLike<T>::value> {
  typedef SmallVectorTemplateBase<T, isPodLike<T>::value > SuperClass;

  SmallVectorImpl(const SmallVectorImpl&);
public:
  typedef typename SuperClass::iterator iterator;
  typedef typename SuperClass::size_type size_type;


  explicit SmallVectorImpl(unsigned N)
    : SmallVectorTemplateBase<T, isPodLike<T>::value>(N*sizeof(T)) {
  }

  ~SmallVectorImpl() {

    this->destroy_range(this->begin(), this->end());


    if (!this->isSmall())
      free(this->begin());
  }


  void clear() {
    this->destroy_range(this->begin(), this->end());
    this->EndX = this->BeginX;
  }

  void resize(unsigned N) {
    if (N < this->size()) {
      this->destroy_range(this->begin()+N, this->end());
      this->setEnd(this->begin()+N);
    } else if (N > this->size()) {
      if (this->capacity() < N)
        this->grow(N);
      this->construct_range(this->end(), this->begin()+N, T());
      this->setEnd(this->begin()+N);
    }
  }

  void resize(unsigned N, const T &NV) {
    if (N < this->size()) {
      this->destroy_range(this->begin()+N, this->end());
      this->setEnd(this->begin()+N);
    } else if (N > this->size()) {
      if (this->capacity() < N)
        this->grow(N);
      construct_range(this->end(), this->begin()+N, NV);
      this->setEnd(this->begin()+N);
    }
  }

  void reserve(unsigned N) {
    if (this->capacity() < N)
      this->grow(N);
  }

  void push_back(const T &Elt) {
    if (this->EndX < this->CapacityX) {
    Retry:
      new (this->end()) T(Elt);
      this->setEnd(this->end()+1);
      return;
    }
    this->grow();
    goto Retry;
  }

  void pop_back() {
    this->setEnd(this->end()-1);
    this->end()->~T();
  }

  T pop_back_val() {
    T Result = this->back();
    pop_back();
    return Result;
  }

  void swap(SmallVectorImpl &RHS);



  template<typename in_iter>
  void append(in_iter in_start, in_iter in_end) {
    size_type NumInputs = std::distance(in_start, in_end);

    if (NumInputs > size_type(this->capacity_ptr()-this->end()))
      this->grow(this->size()+NumInputs);




    std::uninitialized_copy(in_start, in_end, this->end());
    this->setEnd(this->end() + NumInputs);
  }



  void append(size_type NumInputs, const T &Elt) {

    if (NumInputs > size_type(this->capacity_ptr()-this->end()))
      this->grow(this->size()+NumInputs);


    std::uninitialized_fill_n(this->end(), NumInputs, Elt);
    this->setEnd(this->end() + NumInputs);
  }

  void assign(unsigned NumElts, const T &Elt) {
    clear();
    if (this->capacity() < NumElts)
      this->grow(NumElts);
    this->setEnd(this->begin()+NumElts);
    construct_range(this->begin(), this->end(), Elt);
  }

  iterator erase(iterator I) {
    iterator N = I;

    std::copy(I+1, this->end(), I);

    pop_back();
    return(N);
  }

  iterator erase(iterator S, iterator E) {
    iterator N = S;

    iterator I = std::copy(E, this->end(), S);

    this->destroy_range(I, this->end());
    this->setEnd(I);
    return(N);
  }

  iterator insert(iterator I, const T &Elt) {
    if (I == this->end()) {
      push_back(Elt);
      return this->end()-1;
    }

    if (this->EndX < this->CapacityX) {
    Retry:
      new (this->end()) T(this->back());
      this->setEnd(this->end()+1);

      std::copy_backward(I, this->end()-1, this->end());



      const T *EltPtr = &Elt;
      if (I <= EltPtr && EltPtr < this->EndX)
        ++EltPtr;

      *I = *EltPtr;
      return I;
    }
    size_t EltNo = I-this->begin();
    this->grow();
    I = this->begin()+EltNo;
    goto Retry;
  }

  iterator insert(iterator I, size_type NumToInsert, const T &Elt) {
    if (I == this->end()) {
      append(NumToInsert, Elt);
      return this->end()-1;
    }


    size_t InsertElt = I - this->begin();


    reserve(static_cast<unsigned>(this->size() + NumToInsert));


    I = this->begin()+InsertElt;





    if (size_t(this->end()-I) >= NumToInsert) {
      T *OldEnd = this->end();
      append(this->end()-NumToInsert, this->end());


      std::copy_backward(I, OldEnd-NumToInsert, OldEnd);

      std::fill_n(I, NumToInsert, Elt);
      return I;
    }





    T *OldEnd = this->end();
    this->setEnd(this->end() + NumToInsert);
    size_t NumOverwritten = OldEnd-I;
    this->uninitialized_copy(I, OldEnd, this->end()-NumOverwritten);


    std::fill_n(I, NumOverwritten, Elt);


    std::uninitialized_fill_n(OldEnd, NumToInsert-NumOverwritten, Elt);
    return I;
  }

  template<typename ItTy>
  iterator insert(iterator I, ItTy From, ItTy To) {
    if (I == this->end()) {
      append(From, To);
      return this->end()-1;
    }

    size_t NumToInsert = std::distance(From, To);

    size_t InsertElt = I - this->begin();


    reserve(static_cast<unsigned>(this->size() + NumToInsert));


    I = this->begin()+InsertElt;





    if (size_t(this->end()-I) >= NumToInsert) {
      T *OldEnd = this->end();
      append(this->end()-NumToInsert, this->end());


      std::copy_backward(I, OldEnd-NumToInsert, OldEnd);

      std::copy(From, To, I);
      return I;
    }





    T *OldEnd = this->end();
    this->setEnd(this->end() + NumToInsert);
    size_t NumOverwritten = OldEnd-I;
    this->uninitialized_copy(I, OldEnd, this->end()-NumOverwritten);


    for (; NumOverwritten > 0; --NumOverwritten) {
      *I = *From;
      ++I; ++From;
    }


    this->uninitialized_copy(From, To, OldEnd);
    return I;
  }

  const SmallVectorImpl
  &operator=(const SmallVectorImpl &RHS);

  bool operator==(const SmallVectorImpl &RHS) const {
    if (this->size() != RHS.size()) return false;
    return std::equal(this->begin(), this->end(), RHS.begin());
  }
  bool operator!=(const SmallVectorImpl &RHS) const {
    return !(*this == RHS);
  }

  bool operator<(const SmallVectorImpl &RHS) const {
    return std::lexicographical_compare(this->begin(), this->end(),
                                        RHS.begin(), RHS.end());
  }
  void set_size(unsigned N) {
    ((N <= this->capacity()) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/SmallVector.h", 554, "N <= this->capacity()"));
    this->setEnd(this->begin() + N);
  }

private:
  static void construct_range(T *S, T *E, const T &Elt) {
    for (; S != E; ++S)
      new (S) T(Elt);
  }
};


template <typename T>
void SmallVectorImpl<T>::swap(SmallVectorImpl<T> &RHS) {
  if (this == &RHS) return;


  if (!this->isSmall() && !RHS.isSmall()) {
    std::swap(this->BeginX, RHS.BeginX);
    std::swap(this->EndX, RHS.EndX);
    std::swap(this->CapacityX, RHS.CapacityX);
    return;
  }
  if (RHS.size() > this->capacity())
    this->grow(RHS.size());
  if (this->size() > RHS.capacity())
    RHS.grow(this->size());


  size_t NumShared = this->size();
  if (NumShared > RHS.size()) NumShared = RHS.size();
  for (unsigned i = 0; i != static_cast<unsigned>(NumShared); ++i)
    std::swap((*this)[i], RHS[i]);


  if (this->size() > RHS.size()) {
    size_t EltDiff = this->size() - RHS.size();
    this->uninitialized_copy(this->begin()+NumShared, this->end(), RHS.end());
    RHS.setEnd(RHS.end()+EltDiff);
    this->destroy_range(this->begin()+NumShared, this->end());
    this->setEnd(this->begin()+NumShared);
  } else if (RHS.size() > this->size()) {
    size_t EltDiff = RHS.size() - this->size();
    this->uninitialized_copy(RHS.begin()+NumShared, RHS.end(), this->end());
    this->setEnd(this->end() + EltDiff);
    this->destroy_range(RHS.begin()+NumShared, RHS.end());
    RHS.setEnd(RHS.begin()+NumShared);
  }
}

template <typename T>
const SmallVectorImpl<T> &SmallVectorImpl<T>::
  operator=(const SmallVectorImpl<T> &RHS) {

  if (this == &RHS) return *this;



  size_t RHSSize = RHS.size();
  size_t CurSize = this->size();
  if (CurSize >= RHSSize) {

    iterator NewEnd;
    if (RHSSize)
      NewEnd = std::copy(RHS.begin(), RHS.begin()+RHSSize, this->begin());
    else
      NewEnd = this->begin();


    this->destroy_range(NewEnd, this->end());


    this->setEnd(NewEnd);
    return *this;
  }



  if (this->capacity() < RHSSize) {

    this->destroy_range(this->begin(), this->end());
    this->setEnd(this->begin());
    CurSize = 0;
    this->grow(RHSSize);
  } else if (CurSize) {

    std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin());
  }


  this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(),
                           this->begin()+CurSize);


  this->setEnd(this->begin()+RHSSize);
  return *this;
}
template <typename T, unsigned N>
class SmallVector : public SmallVectorImpl<T> {


  typedef typename SmallVectorImpl<T>::U U;
  enum {

    MinUs = (static_cast<unsigned int>(sizeof(T))*N +
             static_cast<unsigned int>(sizeof(U)) - 1) /
            static_cast<unsigned int>(sizeof(U)),




    NumInlineEltsElts = MinUs > 1 ? (MinUs - 1) : 1,



    NumTsAvailable = (NumInlineEltsElts+1)*static_cast<unsigned int>(sizeof(U))/
                     static_cast<unsigned int>(sizeof(T))
  };
  U InlineElts[NumInlineEltsElts];
public:
  SmallVector() : SmallVectorImpl<T>(NumTsAvailable) {
  }

  explicit SmallVector(unsigned Size, const T &Value = T())
    : SmallVectorImpl<T>(NumTsAvailable) {
    this->reserve(Size);
    while (Size--)
      this->push_back(Value);
  }

  template<typename ItTy>
  SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(NumTsAvailable) {
    this->append(S, E);
  }

  SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(NumTsAvailable) {
    if (!RHS.empty())
      SmallVectorImpl<T>::operator=(RHS);
  }

  const SmallVector &operator=(const SmallVector &RHS) {
    SmallVectorImpl<T>::operator=(RHS);
    return *this;
  }

};




template <typename T>
class SmallVector<T,0> : public SmallVectorImpl<T> {
public:
  SmallVector() : SmallVectorImpl<T>(0) {}

  explicit SmallVector(unsigned Size, const T &Value = T())
    : SmallVectorImpl<T>(0) {
    this->reserve(Size);
    while (Size--)
      this->push_back(Value);
  }

  template<typename ItTy>
  SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(0) {
    this->append(S, E);
  }

  SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(0) {
    SmallVectorImpl<T>::operator=(RHS);
  }

  SmallVector &operator=(const SmallVectorImpl<T> &RHS) {
    return SmallVectorImpl<T>::operator=(RHS);
  }

};

template<typename T, unsigned N>
static inline size_t capacity_in_bytes(const SmallVector<T, N> &X) {
  return X.capacity_in_bytes();
}

}

namespace std {

  template<typename T>
  inline void
  swap(llvm::SmallVectorImpl<T> &LHS, llvm::SmallVectorImpl<T> &RHS) {
    LHS.swap(RHS);
  }


  template<typename T, unsigned N>
  inline void
  swap(llvm::SmallVector<T, N> &LHS, llvm::SmallVector<T, N> &RHS) {
    LHS.swap(RHS);
  }
}


namespace llvm {
  class APInt;
  template<typename T>
  class ArrayRef {
  public:
    typedef const T *iterator;
    typedef const T *const_iterator;
    typedef size_t size_type;

  private:

    const T *Data;


    size_type Length;

  public:




                 ArrayRef() : Data(0), Length(0) {}


                 ArrayRef(const T &OneElt)
      : Data(&OneElt), Length(1) {}


                 ArrayRef(const T *data, size_t length)
      : Data(data), Length(length) {}


    ArrayRef(const T *begin, const T *end)
      : Data(begin), Length(end - begin) {}


                 ArrayRef(const SmallVectorImpl<T> &Vec)
      : Data(Vec.data()), Length(Vec.size()) {}


                 ArrayRef(const std::vector<T> &Vec)
      : Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {}


    template <size_t N>
                 ArrayRef(const T (&Arr)[N])
      : Data(Arr), Length(N) {}





    iterator begin() const { return Data; }
    iterator end() const { return Data + Length; }


    bool empty() const { return Length == 0; }

    const T *data() const { return Data; }


    size_t size() const { return Length; }


    const T &front() const {
      ((!empty()) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ArrayRef.h", 93, "!empty()"));
      return Data[0];
    }


    const T &back() const {
      ((!empty()) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ArrayRef.h", 99, "!empty()"));
      return Data[Length-1];
    }


    bool equals(ArrayRef RHS) const {
      if (Length != RHS.Length)
        return false;
      for (size_type i = 0; i != Length; i++)
        if (Data[i] != RHS.Data[i])
          return false;
      return true;
    }


    ArrayRef<T> slice(unsigned N) {
      ((N <= size() && "Invalid specifier") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ArrayRef.h", 115, "N <= size() && \"Invalid specifier\""));
      return ArrayRef<T>(data()+N, size()-N);
    }



    ArrayRef<T> slice(unsigned N, unsigned M) {
      ((N+M <= size() && "Invalid specifier") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ArrayRef.h", 122, "N+M <= size() && \"Invalid specifier\""));
      return ArrayRef<T>(data()+N, M);
    }




    const T &operator[](size_t Index) const {
      ((Index < Length && "Invalid index!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/ArrayRef.h", 130, "Index < Length && \"Invalid index!\""));
      return Data[Index];
    }




    std::vector<T> vec() const {
      return std::vector<T>(Data, Data+Length);
    }




    operator std::vector<T>() const {
      return std::vector<T>(Data, Data+Length);
    }


  };





  template<typename T>
  ArrayRef<T> makeArrayRef(const T &OneElt) {
    return OneElt;
  }


  template<typename T>
  ArrayRef<T> makeArrayRef(const T *data, size_t length) {
    return ArrayRef<T>(data, length);
  }


  template<typename T>
  ArrayRef<T> makeArrayRef(const T *begin, const T *end) {
    return ArrayRef<T>(begin, end);
  }


  template <typename T>
  ArrayRef<T> makeArrayRef(const SmallVectorImpl<T> &Vec) {
    return Vec;
  }


  template <typename T, unsigned N>
  ArrayRef<T> makeArrayRef(const SmallVector<T, N> &Vec) {
    return Vec;
  }


  template<typename T>
  ArrayRef<T> makeArrayRef(const std::vector<T> &Vec) {
    return Vec;
  }


  template<typename T, size_t N>
  ArrayRef<T> makeArrayRef(const T (&Arr)[N]) {
    return ArrayRef<T>(Arr);
  }





  template<typename T>
  inline bool operator==(ArrayRef<T> LHS, ArrayRef<T> RHS) {
    return LHS.equals(RHS);
  }

  template<typename T>
  inline bool operator!=(ArrayRef<T> LHS, ArrayRef<T> RHS) {
    return !(LHS == RHS);
  }




  template <typename T> struct isPodLike;
  template <typename T> struct isPodLike<ArrayRef<T> > {
    static const bool value = true;
  };
}



namespace llvm {

class BitVector;
class MachineFunction;
class RegScavenger;
template<class T> class SmallVectorImpl;
class raw_ostream;

class TargetRegisterClass {
public:
  typedef const unsigned* iterator;
  typedef const unsigned* const_iterator;
  typedef const EVT* vt_iterator;
  typedef const TargetRegisterClass* const * sc_iterator;
private:
  const MCRegisterClass *MC;
  const vt_iterator VTs;
  const unsigned *SubClassMask;
  const sc_iterator SuperClasses;
  const sc_iterator SuperRegClasses;
public:
  TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
                      const unsigned *subcm,
                      const TargetRegisterClass * const *supcs,
                      const TargetRegisterClass * const *superregcs)
    : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
      SuperRegClasses(superregcs) {}

  virtual ~TargetRegisterClass() {}



  unsigned getID() const { return MC->getID(); }



  const char *getName() const { return MC->getName(); }



  iterator begin() const { return MC->begin(); }
  iterator end() const { return MC->end(); }



  unsigned getNumRegs() const { return MC->getNumRegs(); }



  unsigned getRegister(unsigned i) const {
    return MC->getRegister(i);
  }



  bool contains(unsigned Reg) const {
    return MC->contains(Reg);
  }


  bool contains(unsigned Reg1, unsigned Reg2) const {
    return MC->contains(Reg1, Reg2);
  }



  unsigned getSize() const { return MC->getSize(); }



  unsigned getAlignment() const { return MC->getAlignment(); }




  int getCopyCost() const { return MC->getCopyCost(); }



  bool isAllocatable() const { return MC->isAllocatable(); }



  bool hasType(EVT vt) const {
    for(int i = 0; VTs[i] != MVT::Other; ++i)
      if (VTs[i] == vt)
        return true;
    return false;
  }



  vt_iterator vt_begin() const {
    return VTs;
  }

  vt_iterator vt_end() const {
    vt_iterator I = VTs;
    while (*I != MVT::Other) ++I;
    return I;
  }



  sc_iterator superregclasses_begin() const {
    return SuperRegClasses;
  }

  sc_iterator superregclasses_end() const {
    sc_iterator I = SuperRegClasses;
    while (*I != __null) ++I;
    return I;
  }



  bool hasSubClass(const TargetRegisterClass *RC) const {
    return RC != this && hasSubClassEq(RC);
  }



  bool hasSubClassEq(const TargetRegisterClass *RC) const {
    unsigned ID = RC->getID();
    return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
  }



  bool hasSuperClass(const TargetRegisterClass *RC) const {
    return RC->hasSubClass(this);
  }



  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
    return RC->hasSubClassEq(this);
  }




  const unsigned *getSubClassMask() const {
    return SubClassMask;
  }




  sc_iterator getSuperClasses() const {
    return SuperClasses;
  }



  bool isASubClass() const {
    return SuperClasses[0] != 0;
  }
  virtual
  ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
    return makeArrayRef(begin(), getNumRegs());
  }
};



struct TargetRegisterInfoDesc {
  unsigned CostPerUse;
  bool inAllocatableClass;
};







class TargetRegisterInfo : public MCRegisterInfo {
public:
  typedef const TargetRegisterClass * const * regclass_iterator;
private:
  const TargetRegisterInfoDesc *InfoDesc;
  const char *const *SubRegIndexNames;
  regclass_iterator RegClassBegin, RegClassEnd;

protected:
  TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
                     regclass_iterator RegClassBegin,
                     regclass_iterator RegClassEnd,
                     const char *const *subregindexnames);
  virtual ~TargetRegisterInfo();
public:
  static bool isStackSlot(unsigned Reg) {
    return int(Reg) >= (1 << 30);
  }



  static int stackSlot2Index(unsigned Reg) {
    ((isStackSlot(Reg) && "Not a stack slot") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 260, "isStackSlot(Reg) && \"Not a stack slot\""));
    return int(Reg - (1u << 30));
  }



  static unsigned index2StackSlot(int FI) {
    ((FI >= 0 && "Cannot hold a negative frame index.") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 267, "FI >= 0 && \"Cannot hold a negative frame index.\""));
    return FI + (1u << 30);
  }



  static bool isPhysicalRegister(unsigned Reg) {
    ((!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 274, "!isStackSlot(Reg) && \"Not a register! Check isStackSlot() first.\""));
    return int(Reg) > 0;
  }



  static bool isVirtualRegister(unsigned Reg) {
    ((!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 281, "!isStackSlot(Reg) && \"Not a register! Check isStackSlot() first.\""));
    return int(Reg) < 0;
  }



  static unsigned virtReg2Index(unsigned Reg) {
    ((isVirtualRegister(Reg) && "Not a virtual register") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 288, "isVirtualRegister(Reg) && \"Not a virtual register\""));
    return Reg & ~(1u << 31);
  }



  static unsigned index2VirtReg(unsigned Index) {
    return Index | (1u << 31);
  }




  const TargetRegisterClass *
    getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;




  BitVector getAllocatableSet(const MachineFunction &MF,
                              const TargetRegisterClass *RC = __null) const;



  unsigned getCostPerUse(unsigned RegNo) const {
    return InfoDesc[RegNo].CostPerUse;
  }



  bool isInAllocatableClass(unsigned RegNo) const {
    return InfoDesc[RegNo].inAllocatableClass;
  }



  const char *getSubRegIndexName(unsigned SubIdx) const {
    ((SubIdx && "This is not a subregister index") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 325, "SubIdx && \"This is not a subregister index\""));
    return SubRegIndexNames[SubIdx-1];
  }



  bool regsOverlap(unsigned regA, unsigned regB) const {
    if (regA == regB) return true;
    if (isVirtualRegister(regA) || isVirtualRegister(regB))
      return false;
    for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
      if (*regList == regB) return true;
    }
    return false;
  }



  bool isSubRegister(unsigned regA, unsigned regB) const {
    return isSuperRegister(regB, regA);
  }



  bool isSuperRegister(unsigned regA, unsigned regB) const {
    for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
      if (*regList == regB) return true;
    }
    return false;
  }





  virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
                                                                      const = 0;






  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;




  virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;




  virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;



  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
                               const TargetRegisterClass *RC) const {
    for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
      if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
        return SR;
    return 0;
  }







  virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
                                       SmallVectorImpl<unsigned> &SubIndices,
                                       unsigned &NewSubIdx) const {
    return 0;
  }




  virtual const TargetRegisterClass *
  getMatchingSuperRegClass(const TargetRegisterClass *A,
                           const TargetRegisterClass *B, unsigned Idx) const {
    return 0;
  }
  virtual const TargetRegisterClass *
  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
  virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {

    return b;
  }







  regclass_iterator regclass_begin() const { return RegClassBegin; }
  regclass_iterator regclass_end() const { return RegClassEnd; }

  unsigned getNumRegClasses() const {
    return (unsigned)(regclass_end()-regclass_begin());
  }



  const TargetRegisterClass *getRegClass(unsigned i) const {
    ((i < getNumRegClasses() && "Register Class ID out of range") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 458, "i < getNumRegClasses() && \"Register Class ID out of range\""));
    return RegClassBegin[i];
  }



  const TargetRegisterClass *
  getCommonSubClass(const TargetRegisterClass *A,
                    const TargetRegisterClass *B) const;




  virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
    ((0 && "Target didn't implement getPointerRegClass!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 472, "0 && \"Target didn't implement getPointerRegClass!\""));
    return 0;
  }






  virtual const TargetRegisterClass *
  getCrossCopyRegClass(const TargetRegisterClass *RC) const {
    return RC;
  }





  virtual const TargetRegisterClass*
  getLargestLegalSuperClass(const TargetRegisterClass *RC) const {


    return RC;
  }




  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                                       MachineFunction &MF) const {
    return 0;
  }







  virtual ArrayRef<unsigned>
  getRawAllocationOrder(const TargetRegisterClass *RC,
                        unsigned HintType, unsigned HintReg,
                        const MachineFunction &MF) const {
    return RC->getRawAllocationOrder(MF);
  }



  virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
                                       const MachineFunction &MF) const {
    if (Type == 0 && Reg && isPhysicalRegister(Reg))
      return Reg;
    return 0;
  }





  virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
    return false;
  }







  virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
                                  MachineFunction &MF) const {

  }



  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
    return false;
  }




  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
    return true;
  }



  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
    return false;
  }




  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
    return false;
  }







  virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
                                    int &FrameIdx) const {
    return false;
  }




  virtual bool needsStackRealignment(const MachineFunction &MF) const {
    return false;
  }



  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
                                           int Idx) const {
    return 0;
  }





  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
    return false;
  }



  virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
                                            unsigned BaseReg, int FrameIdx,
                                            int64_t Offset) const {
    ((0 && "materializeFrameBaseRegister does not exist on this target") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 610, "0 && \"materializeFrameBaseRegister does not exist on this target\""));
  }



  virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
                                 unsigned BaseReg, int64_t Offset) const {
    ((0 && "resolveFrameIndex does not exist on this target") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 617, "0 && \"resolveFrameIndex does not exist on this target\""));
  }



  virtual bool isFrameOffsetLegal(const MachineInstr *MI,
                                  int64_t Offset) const {
    ((0 && "isFrameOffsetLegal does not exist on this target") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 624, "0 && \"isFrameOffsetLegal does not exist on this target\""));
    return false;
  }
  virtual void
  eliminateCallFramePseudoInstr(MachineFunction &MF,
                                MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MI) const {
    ((0 && "Call Frame Pseudo Instructions do not exist on this target!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Target/TargetRegisterInfo.h", 639, "0 && \"Call Frame Pseudo Instructions do not exist on this target!\""));
  }







  virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator I,
                                     MachineBasicBlock::iterator &UseMI,
                                     const TargetRegisterClass *RC,
                                     unsigned Reg) const {
    return false;
  }
  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
                                   int SPAdj, RegScavenger *RS=__null) const = 0;






  virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;



  virtual int getCompactUnwindRegNum(unsigned, bool) const {
    return -1;
  }
};



struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
  unsigned operator()(unsigned Reg) const {
    return TargetRegisterInfo::virtReg2Index(Reg);
  }
};
class PrintReg {
  const TargetRegisterInfo *TRI;
  unsigned Reg;
  unsigned SubIdx;
public:
  PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
    : TRI(tri), Reg(reg), SubIdx(subidx) {}
  void print(raw_ostream&) const;
};

static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
  PR.print(OS);
  return OS;
}

}

namespace llvm {

struct ARMGenRegisterInfo : public TargetRegisterInfo {
  explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0);
  virtual bool needsStackRealignment(const MachineFunction &) const
     { return false; }
  unsigned getSubReg(unsigned RegNo, unsigned Index) const;
  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
  unsigned composeSubRegIndices(unsigned, unsigned) const;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;
};



namespace ARM {
enum {
  NoSubRegister,
  dsub_0,
  dsub_1,
  dsub_2,
  dsub_3,
  dsub_4,
  dsub_5,
  dsub_6,
  dsub_7,
  qqsub_0,
  qqsub_1,
  qsub_0,
  qsub_1,
  qsub_2,
  qsub_3,
  ssub_0,
  ssub_1,
  ssub_2,
  ssub_3,
  NUM_TARGET_NAMED_SUBREGS = 31
};
}
namespace ARM {
  struct SPRClass : public TargetRegisterClass {
    SPRClass();
  };
  extern SPRClass SPRRegClass;
  static TargetRegisterClass * const SPRRegisterClass = &SPRRegClass;
  struct DPRClass : public TargetRegisterClass {
    DPRClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern DPRClass DPRRegClass;
  static TargetRegisterClass * const DPRRegisterClass = &DPRRegClass;
  struct GPRClass : public TargetRegisterClass {
    GPRClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern GPRClass GPRRegClass;
  static TargetRegisterClass * const GPRRegisterClass = &GPRRegClass;
  struct SPR_8Class : public TargetRegisterClass {
    SPR_8Class();
  };
  extern SPR_8Class SPR_8RegClass;
  static TargetRegisterClass * const SPR_8RegisterClass = &SPR_8RegClass;
  struct DPR_VFP2Class : public TargetRegisterClass {
    DPR_VFP2Class();
  };
  extern DPR_VFP2Class DPR_VFP2RegClass;
  static TargetRegisterClass * const DPR_VFP2RegisterClass = &DPR_VFP2RegClass;
  struct QPRClass : public TargetRegisterClass {
    QPRClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern QPRClass QPRRegClass;
  static TargetRegisterClass * const QPRRegisterClass = &QPRRegClass;
  struct GPRnopcClass : public TargetRegisterClass {
    GPRnopcClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern GPRnopcClass GPRnopcRegClass;
  static TargetRegisterClass * const GPRnopcRegisterClass = &GPRnopcRegClass;
  struct rGPRClass : public TargetRegisterClass {
    rGPRClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern rGPRClass rGPRRegClass;
  static TargetRegisterClass * const rGPRRegisterClass = &rGPRRegClass;
  struct tGPRClass : public TargetRegisterClass {
    tGPRClass();
  };
  extern tGPRClass tGPRRegClass;
  static TargetRegisterClass * const tGPRRegisterClass = &tGPRRegClass;
  struct hGPRClass : public TargetRegisterClass {
    hGPRClass();
  };
  extern hGPRClass hGPRRegClass;
  static TargetRegisterClass * const hGPRRegisterClass = &hGPRRegClass;
  struct DPR_8Class : public TargetRegisterClass {
    DPR_8Class();
  };
  extern DPR_8Class DPR_8RegClass;
  static TargetRegisterClass * const DPR_8RegisterClass = &DPR_8RegClass;
  struct QPR_VFP2Class : public TargetRegisterClass {
    QPR_VFP2Class();
  };
  extern QPR_VFP2Class QPR_VFP2RegClass;
  static TargetRegisterClass * const QPR_VFP2RegisterClass = &QPR_VFP2RegClass;
  struct QQPRClass : public TargetRegisterClass {
    QQPRClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern QQPRClass QQPRRegClass;
  static TargetRegisterClass * const QQPRRegisterClass = &QQPRRegClass;
  struct tcGPRClass : public TargetRegisterClass {
    tcGPRClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern tcGPRClass tcGPRRegClass;
  static TargetRegisterClass * const tcGPRRegisterClass = &tcGPRRegClass;
  struct QPR_8Class : public TargetRegisterClass {
    QPR_8Class();
  };
  extern QPR_8Class QPR_8RegClass;
  static TargetRegisterClass * const QPR_8RegisterClass = &QPR_8RegClass;
  struct QQPR_VFP2Class : public TargetRegisterClass {
    QQPR_VFP2Class();
  };
  extern QQPR_VFP2Class QQPR_VFP2RegClass;
  static TargetRegisterClass * const QQPR_VFP2RegisterClass = &QQPR_VFP2RegClass;
  struct QQQQPRClass : public TargetRegisterClass {
    QQQQPRClass();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern QQQQPRClass QQQQPRRegClass;
  static TargetRegisterClass * const QQQQPRRegisterClass = &QQQQPRRegClass;
  struct QQQQPR_with_ssub_0Class : public TargetRegisterClass {
    QQQQPR_with_ssub_0Class();
    ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
  };
  extern QQQQPR_with_ssub_0Class QQQQPR_with_ssub_0RegClass;
  static TargetRegisterClass * const QQQQPR_with_ssub_0RegisterClass = &QQQQPR_with_ssub_0RegClass;
  struct GPRspClass : public TargetRegisterClass {
    GPRspClass();
  };
  extern GPRspClass GPRspRegClass;
  static TargetRegisterClass * const GPRspRegisterClass = &GPRspRegClass;
  struct CCRClass : public TargetRegisterClass {
    CCRClass();
  };
  extern CCRClass CCRRegClass;
  static TargetRegisterClass * const CCRRegisterClass = &CCRRegClass;
}

}

namespace llvm {
  class ARMSubtarget;
  class ARMBaseInstrInfo;
  class Type;


namespace ARMRI {
  enum {
    RegPairOdd = 1,
    RegPairEven = 2
  };
}



static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
  using namespace ARM;
  switch (Reg) {
    case R0: case R1: case R2: case R3:
    case R4: case R5: case R6: case R7:
    case LR: case SP: case PC:
      return true;
    case R8: case R9: case R10: case R11:

      return !isDarwin;
    default:
      return false;
  }
}

static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) {
  using namespace ARM;
  switch (Reg) {
    case R8: case R9: case R10: case R11:

      return isDarwin;
    default:
      return false;
  }
}

static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) {
  using namespace ARM;
  switch (Reg) {
    case D15: case D14: case D13: case D12:
    case D11: case D10: case D9: case D8:
      return true;
    default:
      return false;
  }
}

class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
protected:
  const ARMBaseInstrInfo &TII;
  const ARMSubtarget &STI;


  unsigned FramePtr;




  unsigned BasePtr;


  explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
                               const ARMSubtarget &STI);


  unsigned getOpcode(int Op) const;

public:

  const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;

  BitVector getReservedRegs(const MachineFunction &MF) const;




  virtual const TargetRegisterClass *
  getMatchingSuperRegClass(const TargetRegisterClass *A,
                           const TargetRegisterClass *B, unsigned Idx) const;







  virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
                                       SmallVectorImpl<unsigned> &SubIndices,
                                       unsigned &NewSubIdx) const;

  const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
  const TargetRegisterClass*
  getCrossCopyRegClass(const TargetRegisterClass *RC) const;

  const TargetRegisterClass*
  getLargestLegalSuperClass(const TargetRegisterClass *RC) const;

  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                               MachineFunction &MF) const;

  ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC,
                                           unsigned HintType, unsigned HintReg,
                                           const MachineFunction &MF) const;

  unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
                               const MachineFunction &MF) const;

  void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
                          MachineFunction &MF) const;

  virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;

  bool hasBasePointer(const MachineFunction &MF) const;

  bool canRealignStack(const MachineFunction &MF) const;
  bool needsStackRealignment(const MachineFunction &MF) const;
  int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
                                    unsigned BaseReg, int FrameIdx,
                                    int64_t Offset) const;
  void resolveFrameIndex(MachineBasicBlock::iterator I,
                         unsigned BaseReg, int64_t Offset) const;
  bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;

  bool cannotEliminateFrame(const MachineFunction &MF) const;


  unsigned getFrameRegister(const MachineFunction &MF) const;
  unsigned getBaseRegister() const { return BasePtr; }


  unsigned getEHExceptionRegister() const;
  unsigned getEHHandlerRegister() const;

  bool isLowRegister(unsigned Reg) const;




  virtual void emitLoadConstPool(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator &MBBI,
                                 DebugLoc dl,
                                 unsigned DestReg, unsigned SubIdx,
                                 int Val,
                                 ARMCC::CondCodes Pred = ARMCC::AL,
                                 unsigned PredReg = 0,
                                 unsigned MIFlags = MachineInstr::NoFlags)const;


  virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;

  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;

  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;

  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;

  virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                           MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator I) const;

  virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
                                   int SPAdj, RegScavenger *RS = __null) const;

private:
  unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;

  unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
};

}

namespace llvm {
  class ARMSubtarget;
  class ARMBaseInstrInfo;
  class Type;

struct ARMRegisterInfo : public ARMBaseRegisterInfo {
public:
  ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
};

}



namespace llvm {
  template <typename T>
  class SmallVectorImpl;
  class StringRef;
  class raw_ostream;
  class Twine {

    enum NodeKind {


      NullKind,


      EmptyKind,


      TwineKind,


      CStringKind,


      StdStringKind,


      StringRefKind,


      CharKind,



      DecUIKind,



      DecIKind,



      DecULKind,


      DecLKind,



      DecULLKind,


      DecLLKind,



      UHexKind
    };

    union Child
    {
      const Twine *twine;
      const char *cString;
      const std::string *stdString;
      const StringRef *stringRef;
      char character;
      unsigned int decUI;
      int decI;
      const unsigned long *decUL;
      const long *decL;
      const unsigned long long *decULL;
      const long long *decLL;
      const uint64_t *uHex;
    };

  private:


    Child LHS;


    Child RHS;



    unsigned char LHSKind;

    unsigned char RHSKind;

  private:

    explicit Twine(NodeKind Kind)
      : LHSKind(Kind), RHSKind(EmptyKind) {
      ((isNullary() && "Invalid kind!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 166, "isNullary() && \"Invalid kind!\""));
    }


    explicit Twine(const Twine &_LHS, const Twine &_RHS)
      : LHSKind(TwineKind), RHSKind(TwineKind) {
      LHS.twine = &_LHS;
      RHS.twine = &_RHS;
      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 174, "isValid() && \"Invalid twine!\""));
    }


    explicit Twine(Child _LHS, NodeKind _LHSKind,
                   Child _RHS, NodeKind _RHSKind)
      : LHS(_LHS), RHS(_RHS), LHSKind(_LHSKind), RHSKind(_RHSKind) {
      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 181, "isValid() && \"Invalid twine!\""));
    }


    bool isNull() const {
      return getLHSKind() == NullKind;
    }


    bool isEmpty() const {
      return getLHSKind() == EmptyKind;
    }


    bool isNullary() const {
      return isNull() || isEmpty();
    }


    bool isUnary() const {
      return getRHSKind() == EmptyKind && !isNullary();
    }


    bool isBinary() const {
      return getLHSKind() != NullKind && getRHSKind() != EmptyKind;
    }



    bool isValid() const {

      if (isNullary() && getRHSKind() != EmptyKind)
        return false;


      if (getRHSKind() == NullKind)
        return false;


      if (getRHSKind() != EmptyKind && getLHSKind() == EmptyKind)
        return false;


      if (getLHSKind() == TwineKind &&
          !LHS.twine->isBinary())
        return false;
      if (getRHSKind() == TwineKind &&
          !RHS.twine->isBinary())
        return false;

      return true;
    }


    NodeKind getLHSKind() const { return (NodeKind) LHSKind; }


    NodeKind getRHSKind() const { return (NodeKind) RHSKind; }


    void printOneChild(raw_ostream &OS, Child Ptr, NodeKind Kind) const;


    void printOneChildRepr(raw_ostream &OS, Child Ptr,
                           NodeKind Kind) const;

  public:




                 Twine() : LHSKind(EmptyKind), RHSKind(EmptyKind) {
      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 254, "isValid() && \"Invalid twine!\""));
    }






                 Twine(const char *Str)
      : RHSKind(EmptyKind) {
      if (Str[0] != '\0') {
        LHS.cString = Str;
        LHSKind = CStringKind;
      } else
        LHSKind = EmptyKind;

      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 270, "isValid() && \"Invalid twine!\""));
    }


                 Twine(const std::string &Str)
      : LHSKind(StdStringKind), RHSKind(EmptyKind) {
      LHS.stdString = &Str;
      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 277, "isValid() && \"Invalid twine!\""));
    }


                 Twine(const StringRef &Str)
      : LHSKind(StringRefKind), RHSKind(EmptyKind) {
      LHS.stringRef = &Str;
      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 284, "isValid() && \"Invalid twine!\""));
    }


    explicit Twine(char Val)
      : LHSKind(CharKind), RHSKind(EmptyKind) {
      LHS.character = Val;
    }


    explicit Twine(signed char Val)
      : LHSKind(CharKind), RHSKind(EmptyKind) {
      LHS.character = static_cast<char>(Val);
    }


    explicit Twine(unsigned char Val)
      : LHSKind(CharKind), RHSKind(EmptyKind) {
      LHS.character = static_cast<char>(Val);
    }


    explicit Twine(unsigned Val)
      : LHSKind(DecUIKind), RHSKind(EmptyKind) {
      LHS.decUI = Val;
    }


    explicit Twine(int Val)
      : LHSKind(DecIKind), RHSKind(EmptyKind) {
      LHS.decI = Val;
    }


    explicit Twine(const unsigned long &Val)
      : LHSKind(DecULKind), RHSKind(EmptyKind) {
      LHS.decUL = &Val;
    }


    explicit Twine(const long &Val)
      : LHSKind(DecLKind), RHSKind(EmptyKind) {
      LHS.decL = &Val;
    }


    explicit Twine(const unsigned long long &Val)
      : LHSKind(DecULLKind), RHSKind(EmptyKind) {
      LHS.decULL = &Val;
    }


    explicit Twine(const long long &Val)
      : LHSKind(DecLLKind), RHSKind(EmptyKind) {
      LHS.decLL = &Val;
    }







                 Twine(const char *_LHS, const StringRef &_RHS)
      : LHSKind(CStringKind), RHSKind(StringRefKind) {
      LHS.cString = _LHS;
      RHS.stringRef = &_RHS;
      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 351, "isValid() && \"Invalid twine!\""));
    }


                 Twine(const StringRef &_LHS, const char *_RHS)
      : LHSKind(StringRefKind), RHSKind(CStringKind) {
      LHS.stringRef = &_LHS;
      RHS.cString = _RHS;
      ((isValid() && "Invalid twine!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 359, "isValid() && \"Invalid twine!\""));
    }



    static Twine createNull() {
      return Twine(NullKind);
    }






    static Twine utohexstr(const uint64_t &Val) {
      Child LHS, RHS;
      LHS.uHex = &Val;
      RHS.twine = 0;
      return Twine(LHS, UHexKind, RHS, EmptyKind);
    }







    bool isTriviallyEmpty() const {
      return isNullary();
    }



    bool isSingleStringRef() const {
      if (getRHSKind() != EmptyKind) return false;

      switch (getLHSKind()) {
      case EmptyKind:
      case CStringKind:
      case StdStringKind:
      case StringRefKind:
        return true;
      default:
        return false;
      }
    }





    Twine concat(const Twine &Suffix) const;






    std::string str() const;



    void toVector(SmallVectorImpl<char> &Out) const;



    StringRef getSingleStringRef() const {
      ((isSingleStringRef() &&"This cannot be had as a single stringref!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 426, "isSingleStringRef() &&\"This cannot be had as a single stringref!\""));
      switch (getLHSKind()) {
      default: ((0 && "Out of sync with isSingleStringRef") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Twine.h", 428, "0 && \"Out of sync with isSingleStringRef\""));
      case EmptyKind: return StringRef();
      case CStringKind: return StringRef(LHS.cString);
      case StdStringKind: return StringRef(*LHS.stdString);
      case StringRefKind: return *LHS.stringRef;
      }
    }




    StringRef toStringRef(SmallVectorImpl<char> &Out) const;







    StringRef toNullTerminatedStringRef(SmallVectorImpl<char> &Out) const;



    void print(raw_ostream &OS) const;


    void dump() const;


    void printRepr(raw_ostream &OS) const;


    void dumpRepr() const;


  };




  inline Twine Twine::concat(const Twine &Suffix) const {

    if (isNull() || Suffix.isNull())
      return Twine(NullKind);


    if (isEmpty())
      return Suffix;
    if (Suffix.isEmpty())
      return *this;



    Child NewLHS, NewRHS;
    NewLHS.twine = this;
    NewRHS.twine = &Suffix;
    NodeKind NewLHSKind = TwineKind, NewRHSKind = TwineKind;
    if (isUnary()) {
      NewLHS = LHS;
      NewLHSKind = getLHSKind();
    }
    if (Suffix.isUnary()) {
      NewRHS = Suffix.LHS;
      NewRHSKind = Suffix.getLHSKind();
    }

    return Twine(NewLHS, NewLHSKind, NewRHS, NewRHSKind);
  }

  inline Twine operator+(const Twine &LHS, const Twine &RHS) {
    return LHS.concat(RHS);
  }




  inline Twine operator+(const char *LHS, const StringRef &RHS) {
    return Twine(LHS, RHS);
  }




  inline Twine operator+(const StringRef &LHS, const char *RHS) {
    return Twine(LHS, RHS);
  }

  inline raw_ostream &operator<<(raw_ostream &OS, const Twine &RHS) {
    RHS.print(OS);
    return OS;
  }


}






namespace llvm {
class Triple {
public:
  enum ArchType {
    UnknownArch,

    alpha,
    arm,
    bfin,
    cellspu,
    mips,
    mipsel,
    mips64,
    mips64el,
    msp430,
    ppc,
    ppc64,
    sparc,
    sparcv9,
    systemz,
    tce,
    thumb,
    x86,
    x86_64,
    xcore,
    mblaze,
    ptx32,
    ptx64,
    le32,
    amdil,

    InvalidArch
  };
  enum VendorType {
    UnknownVendor,

    Apple,
    PC,
    SCEI
  };
  enum OSType {
    UnknownOS,

    AuroraUX,
    Cygwin,
    Darwin,
    DragonFly,
    FreeBSD,
    IOS,
    KFreeBSD,
    Linux,
    Lv2,
    MacOSX,
    MinGW32,
    NetBSD,
    OpenBSD,
    Psp,
    Solaris,
    Win32,
    Haiku,
    Minix,
    RTEMS,
    NativeClient
  };
  enum EnvironmentType {
    UnknownEnvironment,

    GNU,
    GNUEABI,
    EABI,
    MachO
  };

private:
  std::string Data;


  mutable ArchType Arch;


  mutable VendorType Vendor;


  mutable OSType OS;


  mutable EnvironmentType Environment;

  bool isInitialized() const { return Arch != InvalidArch; }
  static ArchType ParseArch(StringRef ArchName);
  static VendorType ParseVendor(StringRef VendorName);
  static OSType ParseOS(StringRef OSName);
  static EnvironmentType ParseEnvironment(StringRef EnvironmentName);
  void Parse() const;

public:



  Triple() : Data(), Arch(InvalidArch) {}
  explicit Triple(const Twine &Str) : Data(Str.str()), Arch(InvalidArch) {}
  Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr)
    : Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr).str()),
      Arch(InvalidArch) {
  }

  Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr,
         const Twine &EnvironmentStr)
    : Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr + Twine('-') +
            EnvironmentStr).str()), Arch(InvalidArch) {
  }
  static std::string normalize(StringRef Str);






  ArchType getArch() const {
    if (!isInitialized()) Parse();
    return Arch;
  }


  VendorType getVendor() const {
    if (!isInitialized()) Parse();
    return Vendor;
  }


  OSType getOS() const {
    if (!isInitialized()) Parse();
    return OS;
  }



  bool hasEnvironment() const {
    return getEnvironmentName() != "";
  }


  EnvironmentType getEnvironment() const {
    if (!isInitialized()) Parse();
    return Environment;
  }





  const std::string &str() const { return Data; }

  const std::string &getTriple() const { return Data; }



  StringRef getArchName() const;


  StringRef getVendorName() const;



  StringRef getOSName() const;



  StringRef getEnvironmentName() const;




  StringRef getOSAndEnvironmentName() const;







  void getOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const;



  unsigned getOSMajorVersion() const {
    unsigned Maj, Min, Micro;
    getOSVersion(Maj, Min, Micro);
    return Maj;
  }



  bool isOSVersionLT(unsigned Major, unsigned Minor = 0,
                     unsigned Micro = 0) const {
    unsigned LHS[3];
    getOSVersion(LHS[0], LHS[1], LHS[2]);

    if (LHS[0] != Major)
      return LHS[0] < Major;
    if (LHS[1] != Minor)
      return LHS[1] < Minor;
    if (LHS[2] != Micro)
      return LHS[1] < Micro;

    return false;
  }



  bool isMacOSX() const {
    return getOS() == Triple::Darwin || getOS() == Triple::MacOSX;
  }


  bool isOSDarwin() const {
    return isMacOSX() || getOS() == Triple::IOS;
  }


  bool isOSWindows() const {
    return getOS() == Triple::Win32 || getOS() == Triple::Cygwin ||
      getOS() == Triple::MinGW32;
  }




  unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
        unsigned Micro = 0) const {
    ((isMacOSX() && "Not an OS X triple!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Triple.h", 279, "isMacOSX() && \"Not an OS X triple!\""));


    if (getOS() == Triple::MacOSX)
      return isOSVersionLT(Major, Minor, Micro);


    ((Major == 10 && "Unexpected major version") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/Triple.h", 286, "Major == 10 && \"Unexpected major version\""));
    return isOSVersionLT(Minor + 4, Micro, 0);
  }







  void setArch(ArchType Kind);



  void setVendor(VendorType Kind);



  void setOS(OSType Kind);



  void setEnvironment(EnvironmentType Kind);


  void setTriple(const Twine &Str);



  void setArchName(StringRef Str);



  void setVendorName(StringRef Str);



  void setOSName(StringRef Str);



  void setEnvironmentName(StringRef Str);



  void setOSAndEnvironmentName(StringRef Str);



  const char *getArchNameForAssembler();







  static const char *getArchTypeName(ArchType Kind);







  static const char *getArchTypePrefix(ArchType Kind);



  static const char *getVendorTypeName(VendorType Kind);



  static const char *getOSTypeName(OSType Kind);



  static const char *getEnvironmentTypeName(EnvironmentType Kind);







  static ArchType getArchTypeForLLVMName(StringRef Str);




  static ArchType getArchTypeForDarwinArchName(StringRef Str);


};

}


namespace llvm {
  class raw_ostream;
  class StringRef;






struct SubtargetFeatureKV {
  const char *Key;
  const char *Desc;
  uint64_t Value;
  uint64_t Implies;


  bool operator<(const SubtargetFeatureKV &S) const {
    return strcmp(Key, S.Key) < 0;
  }
};






struct SubtargetInfoKV {
  const char *Key;
  void *Value;


  bool operator<(const SubtargetInfoKV &S) const {
    return strcmp(Key, S.Key) < 0;
  }
};
class SubtargetFeatures {
  std::vector<std::string> Features;
public:
  explicit SubtargetFeatures(const StringRef Initial = "");


  std::string getString() const;


  void AddFeature(const StringRef String, bool IsEnabled = true);



  uint64_t ToggleFeature(uint64_t Bits, const StringRef String,
                         const SubtargetFeatureKV *FeatureTable,
                         size_t FeatureTableSize);


  uint64_t getFeatureBits(const StringRef CPU,
                          const SubtargetFeatureKV *CPUTable,
                          size_t CPUTableSize,
                          const SubtargetFeatureKV *FeatureTable,
                          size_t FeatureTableSize);


  void *getItinerary(const StringRef CPU,
                     const SubtargetInfoKV *Table, size_t TableSize);


  void print(raw_ostream &OS) const;


  void dump() const;



  void getDefaultSubtargetFeatures(const Triple& Triple);
};

}
namespace llvm {
struct InstrStage {
  enum ReservationKinds {
    Required = 0,
    Reserved = 1
  };

  unsigned Cycles_;
  unsigned Units_;
  int NextCycles_;
  ReservationKinds Kind_;


  unsigned getCycles() const {
    return Cycles_;
  }


  unsigned getUnits() const {
    return Units_;
  }

  ReservationKinds getReservationKind() const {
    return Kind_;
  }



  unsigned getNextCycles() const {
    return (NextCycles_ >= 0) ? (unsigned)NextCycles_ : Cycles_;
  }
};
struct InstrItinerary {
  unsigned NumMicroOps;
  unsigned FirstStage;
  unsigned LastStage;
  unsigned FirstOperandCycle;
  unsigned LastOperandCycle;
};






class InstrItineraryData {
public:
  const InstrStage *Stages;
  const unsigned *OperandCycles;
  const unsigned *Forwardings;
  const InstrItinerary *Itineraries;
  unsigned IssueWidth;



  InstrItineraryData() : Stages(0), OperandCycles(0), Forwardings(0),
                         Itineraries(0), IssueWidth(0) {}

  InstrItineraryData(const InstrStage *S, const unsigned *OS,
                     const unsigned *F, const InstrItinerary *I)
    : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I),
      IssueWidth(0) {}



  bool isEmpty() const { return Itineraries == 0; }




  bool isEndMarker(unsigned ItinClassIndx) const {
    return ((Itineraries[ItinClassIndx].FirstStage == ~0U) &&
            (Itineraries[ItinClassIndx].LastStage == ~0U));
  }



  const InstrStage *beginStage(unsigned ItinClassIndx) const {
    unsigned StageIdx = Itineraries[ItinClassIndx].FirstStage;
    return Stages + StageIdx;
  }



  const InstrStage *endStage(unsigned ItinClassIndx) const {
    unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;
    return Stages + StageIdx;
  }





  unsigned getStageLatency(unsigned ItinClassIndx) const {






    if (isEmpty() || Itineraries[ItinClassIndx].FirstStage == 0)
      return 1;


    unsigned Latency = 0, StartCycle = 0;
    for (const InstrStage *IS = beginStage(ItinClassIndx),
           *E = endStage(ItinClassIndx); IS != E; ++IS) {
      Latency = std::max(Latency, StartCycle + IS->getCycles());
      StartCycle += IS->getNextCycles();
    }

    return Latency;
  }




  int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const {
    if (isEmpty())
      return -1;

    unsigned FirstIdx = Itineraries[ItinClassIndx].FirstOperandCycle;
    unsigned LastIdx = Itineraries[ItinClassIndx].LastOperandCycle;
    if ((FirstIdx + OperandIdx) >= LastIdx)
      return -1;

    return (int)OperandCycles[FirstIdx + OperandIdx];
  }






  bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
                             unsigned UseClass, unsigned UseIdx) const {
    unsigned FirstDefIdx = Itineraries[DefClass].FirstOperandCycle;
    unsigned LastDefIdx = Itineraries[DefClass].LastOperandCycle;
    if ((FirstDefIdx + DefIdx) >= LastDefIdx)
      return false;
    if (Forwardings[FirstDefIdx + DefIdx] == 0)
      return false;

    unsigned FirstUseIdx = Itineraries[UseClass].FirstOperandCycle;
    unsigned LastUseIdx = Itineraries[UseClass].LastOperandCycle;
    if ((FirstUseIdx + UseIdx) >= LastUseIdx)
      return false;

    return Forwardings[FirstDefIdx + DefIdx] ==
      Forwardings[FirstUseIdx + UseIdx];
  }




  int getOperandLatency(unsigned DefClass, unsigned DefIdx,
                        unsigned UseClass, unsigned UseIdx) const {
    if (isEmpty())
      return -1;

    int DefCycle = getOperandCycle(DefClass, DefIdx);
    if (DefCycle == -1)
      return -1;

    int UseCycle = getOperandCycle(UseClass, UseIdx);
    if (UseCycle == -1)
      return -1;

    UseCycle = DefCycle - UseCycle + 1;
    if (UseCycle > 0 &&
        hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))

      --UseCycle;
    return UseCycle;
  }



  bool isMicroCoded(unsigned ItinClassIndx) const {
    if (isEmpty())
      return false;
    return Itineraries[ItinClassIndx].NumMicroOps != 1;
  }
};


}


namespace llvm {

class StringRef;





class MCSubtargetInfo {
  std::string TargetTriple;
  const SubtargetFeatureKV *ProcFeatures;
  const SubtargetFeatureKV *ProcDesc;
  const SubtargetInfoKV *ProcItins;
  const InstrStage *Stages;
  const unsigned *OperandCycles;
  const unsigned *ForwardingPathes;
  unsigned NumFeatures;
  unsigned NumProcs;
  uint64_t FeatureBits;

public:
  void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
                           const SubtargetFeatureKV *PF,
                           const SubtargetFeatureKV *PD,
                           const SubtargetInfoKV *PI, const InstrStage *IS,
                           const unsigned *OC, const unsigned *FP,
                           unsigned NF, unsigned NP);


  StringRef getTargetTriple() const {
    return TargetTriple;
  }



  uint64_t getFeatureBits() const {
    return FeatureBits;
  }



  uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);



  uint64_t ToggleFeature(uint64_t FB);



  uint64_t ToggleFeature(StringRef FS);



  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
};

}


namespace llvm {

class SDep;
class SUnit;
class TargetRegisterClass;
template <typename T> class SmallVectorImpl;







class TargetSubtargetInfo : public MCSubtargetInfo {
  TargetSubtargetInfo(const TargetSubtargetInfo&);
  void operator=(const TargetSubtargetInfo&);
protected:
  TargetSubtargetInfo();
public:


  typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
  typedef SmallVectorImpl<TargetRegisterClass*> RegClassVector;

  virtual ~TargetSubtargetInfo();





  virtual unsigned getSpecialAddressLatency() const { return 0; }






  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                                     AntiDepBreakMode& Mode,
                                     RegClassVector& CriticalPathRCs) const;


  virtual void adjustSchedDependency(SUnit *def, SUnit *use,
                                     SDep& dep) const { }
};

}






namespace llvm {
struct ARMGenSubtargetInfo : public TargetSubtargetInfo {
  explicit ARMGenSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS);
};
}

namespace llvm {
class GlobalValue;
class StringRef;

class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
  enum ARMProcFamilyEnum {
    Others, CortexA8, CortexA9
  };


  ARMProcFamilyEnum ARMProcFamily;



  bool HasV4TOps;
  bool HasV5TOps;
  bool HasV5TEOps;
  bool HasV6Ops;
  bool HasV6T2Ops;
  bool HasV7Ops;



  bool HasVFPv2;
  bool HasVFPv3;
  bool HasNEON;




  bool UseNEONForSinglePrecisionFP;



  bool SlowFPVMLx;



  bool HasVMLxForwarding;


  bool SlowFPBrcc;


  bool InThumbMode;


  bool InNaClMode;


  bool HasThumb2;



  bool IsMClass;


  bool NoARM;


  bool PostRAScheduler;


  bool IsR9Reserved;



  bool UseMovt;




  bool SupportsTailCall;



  bool HasFP16;



  bool HasD16;


  bool HasHardwareDivide;



  bool HasT2ExtractPack;



  bool HasDataBarrier;



  bool Pref32BitThumb;




  bool AvoidCPSRPartialUpdate;



  bool HasMPExtension;



  bool FPOnlySP;




  bool AllowsUnalignedMem;



  bool Thumb2DSP;



  unsigned stackAlignment;


  std::string CPUString;


  Triple TargetTriple;


  InstrItineraryData InstrItins;

 public:
  enum {
    isELF, isDarwin
  } TargetType;

  enum {
    ARM_ABI_APCS,
    ARM_ABI_AAPCS
  } TargetABI;




  ARMSubtarget(const std::string &TT, const std::string &CPU,
               const std::string &FS);



  unsigned getMaxInlineSizeThreshold() const {


    return isThumb1Only() ? 0 : 64;
  }


  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);

  void computeIssueWidth();

  bool hasV4TOps() const { return HasV4TOps; }
  bool hasV5TOps() const { return HasV5TOps; }
  bool hasV5TEOps() const { return HasV5TEOps; }
  bool hasV6Ops() const { return HasV6Ops; }
  bool hasV6T2Ops() const { return HasV6T2Ops; }
  bool hasV7Ops() const { return HasV7Ops; }

  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
  bool isCortexA9() const { return ARMProcFamily == CortexA9; }

  bool hasARMOps() const { return !NoARM; }

  bool hasVFP2() const { return HasVFPv2; }
  bool hasVFP3() const { return HasVFPv3; }
  bool hasNEON() const { return HasNEON; }
  bool useNEONForSinglePrecisionFP() const {
    return hasNEON() && UseNEONForSinglePrecisionFP; }

  bool hasDivide() const { return HasHardwareDivide; }
  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
  bool hasDataBarrier() const { return HasDataBarrier; }
  bool useFPVMLx() const { return !SlowFPVMLx; }
  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
  bool isFPBrccSlow() const { return SlowFPBrcc; }
  bool isFPOnlySP() const { return FPOnlySP; }
  bool prefers32BitThumb() const { return Pref32BitThumb; }
  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
  bool hasMPExtension() const { return HasMPExtension; }
  bool hasThumb2DSP() const { return Thumb2DSP; }

  bool hasFP16() const { return HasFP16; }
  bool hasD16() const { return HasD16; }

  const Triple &getTargetTriple() const { return TargetTriple; }

  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
  bool isTargetNaCl() const {
    return TargetTriple.getOS() == Triple::NativeClient;
  }
  bool isTargetELF() const { return !isTargetDarwin(); }

  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }

  bool isThumb() const { return InThumbMode; }
  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
  bool isThumb2() const { return InThumbMode && HasThumb2; }
  bool hasThumb2() const { return HasThumb2; }
  bool isMClass() const { return IsMClass; }
  bool isARClass() const { return !IsMClass; }

  bool isR9Reserved() const { return IsR9Reserved; }

  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
  bool supportsTailCall() const { return SupportsTailCall; }

  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }

  const std::string & getCPUString() const { return CPUString; }

  unsigned getMispredictionPenalty() const;


  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
                             RegClassVector& CriticalPathRCs) const;



  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }




  unsigned getStackAlignment() const { return stackAlignment; }



  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
};
}





namespace llvm {
  class Serializer;
  class Deserializer;
  class FoldingSetNodeID;
  class raw_ostream;
  class StringRef;

  template<typename T>
  class SmallVectorImpl;



  typedef uint64_t integerPart;

  const unsigned int host_char_bit = 8;
  const unsigned int integerPartWidth = host_char_bit *
    static_cast<unsigned int>(sizeof(integerPart));
class APInt {
  unsigned BitWidth;



  union {
    uint64_t VAL;
    uint64_t *pVal;
  };


  enum {

    APINT_BITS_PER_WORD = static_cast<unsigned int>(sizeof(uint64_t)) *
                          8,

    APINT_WORD_SIZE = static_cast<unsigned int>(sizeof(uint64_t))
  };




  APInt(uint64_t* val, unsigned bits) : BitWidth(bits), pVal(val) { }



  bool isSingleWord() const {
    return BitWidth <= APINT_BITS_PER_WORD;
  }



  static unsigned whichWord(unsigned bitPosition) {
    return bitPosition / APINT_BITS_PER_WORD;
  }




  static unsigned whichBit(unsigned bitPosition) {
    return bitPosition % APINT_BITS_PER_WORD;
  }






  static uint64_t maskBit(unsigned bitPosition) {
    return 1ULL << whichBit(bitPosition);
  }






  APInt& clearUnusedBits() {

    unsigned wordBits = BitWidth % APINT_BITS_PER_WORD;
    if (wordBits == 0)



      return *this;


    uint64_t mask = ~uint64_t(0ULL) >> (APINT_BITS_PER_WORD - wordBits);
    if (isSingleWord())
      VAL &= mask;
    else
      pVal[getNumWords() - 1] &= mask;
    return *this;
  }



  uint64_t getWord(unsigned bitPosition) const {
    return isSingleWord() ? VAL : pVal[whichWord(bitPosition)];
  }
  void fromString(unsigned numBits, StringRef str, uint8_t radix);






  static void divide(const APInt LHS, unsigned lhsWords,
                     const APInt &RHS, unsigned rhsWords,
                     APInt *Quotient, APInt *Remainder);


  void initSlowCase(unsigned numBits, uint64_t val, bool isSigned);


  void initFromArray(ArrayRef<uint64_t> array);


  void initSlowCase(const APInt& that);


  APInt shlSlowCase(unsigned shiftAmt) const;


  APInt AndSlowCase(const APInt& RHS) const;


  APInt OrSlowCase(const APInt& RHS) const;


  APInt XorSlowCase(const APInt& RHS) const;


  APInt& AssignSlowCase(const APInt& RHS);


  bool EqualSlowCase(const APInt& RHS) const;


  bool EqualSlowCase(uint64_t Val) const;


  unsigned countLeadingZerosSlowCase() const;


  unsigned countTrailingOnesSlowCase() const;


  unsigned countPopulationSlowCase() const;

public:
  APInt(unsigned numBits, uint64_t val, bool isSigned = false)
    : BitWidth(numBits), VAL(0) {
    ((BitWidth && "bitwidth too small") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 229, "BitWidth && \"bitwidth too small\""));
    if (isSingleWord())
      VAL = val;
    else
      initSlowCase(numBits, val, isSigned);
    clearUnusedBits();
  }






  APInt(unsigned numBits, ArrayRef<uint64_t> bigVal);







  APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);
  APInt(unsigned numBits, StringRef str, uint8_t radix);



  APInt(const APInt& that)
    : BitWidth(that.BitWidth), VAL(0) {
    ((BitWidth && "bitwidth too small") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 268, "BitWidth && \"bitwidth too small\""));
    if (isSingleWord())
      VAL = that.VAL;
    else
      initSlowCase(that);
  }


  ~APInt() {
    if (!isSingleWord())
      delete [] pVal;
  }



  explicit APInt() : BitWidth(1) {}



  void Profile(FoldingSetNodeID& id) const;







  bool isNegative() const {
    return (*this)[BitWidth - 1];
  }



  bool isNonNegative() const {
    return !isNegative();
  }





  bool isStrictlyPositive() const {
    return isNonNegative() && !!*this;
  }



  bool isAllOnesValue() const {
    return countPopulation() == BitWidth;
  }




  bool isMaxValue() const {
    return countPopulation() == BitWidth;
  }




  bool isMaxSignedValue() const {
    return BitWidth == 1 ? VAL == 0 :
                          !isNegative() && countPopulation() == BitWidth - 1;
  }




  bool isMinValue() const {
    return !*this;
  }




  bool isMinSignedValue() const {
    return BitWidth == 1 ? VAL == 1 : isNegative() && isPowerOf2();
  }


  bool isIntN(unsigned N) const {
    ((N && "N == 0 ???") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 350, "N && \"N == 0 ???\""));
    if (N >= getBitWidth())
      return true;

    if (isSingleWord())
      return isUIntN(N, VAL);
    return APInt(N, makeArrayRef(pVal, getNumWords())).zext(getBitWidth())
      == (*this);
  }


  bool isSignedIntN(unsigned N) const {
    ((N && "N == 0 ???") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 362, "N && \"N == 0 ???\""));
    return getMinSignedBits() <= N;
  }


  bool isPowerOf2() const {
    if (isSingleWord())
      return isPowerOf2_64(VAL);
    return countPopulationSlowCase() == 1;
  }


  bool isSignBit() const { return isMinSignedValue(); }



  bool getBoolValue() const {
    return !!*this;
  }




  uint64_t getLimitedValue(uint64_t Limit = ~0ULL) const {
    return (getActiveBits() > 64 || getZExtValue() > Limit) ?
      Limit : getZExtValue();
  }





  static APInt getMaxValue(unsigned numBits) {
    return getAllOnesValue(numBits);
  }


  static APInt getSignedMaxValue(unsigned numBits) {
    APInt API = getAllOnesValue(numBits);
    API.clearBit(numBits - 1);
    return API;
  }


  static APInt getMinValue(unsigned numBits) {
    return APInt(numBits, 0);
  }


  static APInt getSignedMinValue(unsigned numBits) {
    APInt API(numBits, 0);
    API.setBit(numBits - 1);
    return API;
  }




  static APInt getSignBit(unsigned BitWidth) {
    return getSignedMinValue(BitWidth);
  }



  static APInt getAllOnesValue(unsigned numBits) {
    return APInt(numBits, -1ULL, true);
  }



  static APInt getNullValue(unsigned numBits) {
    return APInt(numBits, 0);
  }




  APInt getHiBits(unsigned numBits) const;




  APInt getLoBits(unsigned numBits) const;


  static APInt getOneBitSet(unsigned numBits, unsigned BitNo) {
    APInt Res(numBits, 0);
    Res.setBit(BitNo);
    return Res;
  }
  static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit) {
    ((hiBit <= numBits && "hiBit out of range") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 464, "hiBit <= numBits && \"hiBit out of range\""));
    ((loBit < numBits && "loBit out of range") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 465, "loBit < numBits && \"loBit out of range\""));
    if (hiBit < loBit)
      return getLowBitsSet(numBits, hiBit) |
             getHighBitsSet(numBits, numBits-loBit);
    return getLowBitsSet(numBits, hiBit-loBit).shl(loBit);
  }





  static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet) {
    ((hiBitsSet <= numBits && "Too many bits to set!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 477, "hiBitsSet <= numBits && \"Too many bits to set!\""));

    if (hiBitsSet == 0)
      return APInt(numBits, 0);
    unsigned shiftAmt = numBits - hiBitsSet;

    if (numBits <= APINT_BITS_PER_WORD)
      return APInt(numBits, ~0ULL << shiftAmt);
    return getAllOnesValue(numBits).shl(shiftAmt);
  }





  static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) {
    ((loBitsSet <= numBits && "Too many bits to set!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 493, "loBitsSet <= numBits && \"Too many bits to set!\""));

    if (loBitsSet == 0)
      return APInt(numBits, 0);
    if (loBitsSet == APINT_BITS_PER_WORD)
      return APInt(numBits, -1ULL);

    if (numBits < APINT_BITS_PER_WORD)
      return APInt(numBits, (1ULL << loBitsSet) - 1);
    return getAllOnesValue(numBits).lshr(numBits - loBitsSet);
  }




  uint64_t getHashValue() const;




  const uint64_t* getRawData() const {
    if (isSingleWord())
      return &VAL;
    return &pVal[0];
  }






  const APInt operator++(int) {
    APInt API(*this);
    ++(*this);
    return API;
  }



  APInt& operator++();



  const APInt operator--(int) {
    APInt API(*this);
    --(*this);
    return API;
  }



  APInt& operator--();




  APInt operator~() const {
    APInt Result(*this);
    Result.flipAllBits();
    return Result;
  }




  APInt operator-() const {
    return APInt(BitWidth, 0) - (*this);
  }




  bool operator!() const;






  APInt& operator=(const APInt& RHS) {

    if (isSingleWord() && RHS.isSingleWord()) {
      VAL = RHS.VAL;
      BitWidth = RHS.BitWidth;
      return clearUnusedBits();
    }

    return AssignSlowCase(RHS);
  }






  APInt& operator=(uint64_t RHS);





  APInt& operator&=(const APInt& RHS);





  APInt& operator|=(const APInt& RHS);






  APInt& operator|=(uint64_t RHS) {
    if (isSingleWord()) {
      VAL |= RHS;
      clearUnusedBits();
    } else {
      pVal[0] |= RHS;
    }
    return *this;
  }





  APInt& operator^=(const APInt& RHS);




  APInt& operator*=(const APInt& RHS);




  APInt& operator+=(const APInt& RHS);




  APInt& operator-=(const APInt& RHS);




  APInt& operator<<=(unsigned shiftAmt) {
    *this = shl(shiftAmt);
    return *this;
  }







  APInt operator&(const APInt& RHS) const {
    ((BitWidth == RHS.BitWidth && "Bit widths must be the same") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 653, "BitWidth == RHS.BitWidth && \"Bit widths must be the same\""));
    if (isSingleWord())
      return APInt(getBitWidth(), VAL & RHS.VAL);
    return AndSlowCase(RHS);
  }
  APInt And(const APInt& RHS) const {
    return this->operator&(RHS);
  }




  APInt operator|(const APInt& RHS) const {
    ((BitWidth == RHS.BitWidth && "Bit widths must be the same") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 666, "BitWidth == RHS.BitWidth && \"Bit widths must be the same\""));
    if (isSingleWord())
      return APInt(getBitWidth(), VAL | RHS.VAL);
    return OrSlowCase(RHS);
  }
  APInt Or(const APInt& RHS) const {
    return this->operator|(RHS);
  }




  APInt operator^(const APInt& RHS) const {
    ((BitWidth == RHS.BitWidth && "Bit widths must be the same") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 679, "BitWidth == RHS.BitWidth && \"Bit widths must be the same\""));
    if (isSingleWord())
      return APInt(BitWidth, VAL ^ RHS.VAL);
    return XorSlowCase(RHS);
  }
  APInt Xor(const APInt& RHS) const {
    return this->operator^(RHS);
  }



  APInt operator*(const APInt& RHS) const;



  APInt operator+(const APInt& RHS) const;
  APInt operator+(uint64_t RHS) const {
    return (*this) + APInt(BitWidth, RHS);
  }



  APInt operator-(const APInt& RHS) const;
  APInt operator-(uint64_t RHS) const {
    return (*this) - APInt(BitWidth, RHS);
  }

  APInt operator<<(unsigned Bits) const {
    return shl(Bits);
  }

  APInt operator<<(const APInt &Bits) const {
    return shl(Bits);
  }



  APInt ashr(unsigned shiftAmt) const;



  APInt lshr(unsigned shiftAmt) const;



  APInt shl(unsigned shiftAmt) const {
    ((shiftAmt <= BitWidth && "Invalid shift amount") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 725, "shiftAmt <= BitWidth && \"Invalid shift amount\""));
    if (isSingleWord()) {
      if (shiftAmt == BitWidth)
        return APInt(BitWidth, 0);
      return APInt(BitWidth, VAL << shiftAmt);
    }
    return shlSlowCase(shiftAmt);
  }


  APInt rotl(unsigned rotateAmt) const;


  APInt rotr(unsigned rotateAmt) const;



  APInt ashr(const APInt &shiftAmt) const;



  APInt lshr(const APInt &shiftAmt) const;



  APInt shl(const APInt &shiftAmt) const;


  APInt rotl(const APInt &rotateAmt) const;


  APInt rotr(const APInt &rotateAmt) const;





  APInt udiv(const APInt &RHS) const;



  APInt sdiv(const APInt &RHS) const {
    if (isNegative())
      if (RHS.isNegative())
        return (-(*this)).udiv(-RHS);
      else
        return -((-(*this)).udiv(RHS));
    else if (RHS.isNegative())
      return -(this->udiv(-RHS));
    return this->udiv(RHS);
  }
  APInt urem(const APInt &RHS) const;



  APInt srem(const APInt &RHS) const {
    if (isNegative())
      if (RHS.isNegative())
        return -((-(*this)).urem(-RHS));
      else
        return -((-(*this)).urem(RHS));
    else if (RHS.isNegative())
      return this->urem(-RHS);
    return this->urem(RHS);
  }







  static void udivrem(const APInt &LHS, const APInt &RHS,
                      APInt &Quotient, APInt &Remainder);

  static void sdivrem(const APInt &LHS, const APInt &RHS,
                      APInt &Quotient, APInt &Remainder) {
    if (LHS.isNegative()) {
      if (RHS.isNegative())
        APInt::udivrem(-LHS, -RHS, Quotient, Remainder);
      else
        APInt::udivrem(-LHS, RHS, Quotient, Remainder);
      Quotient = -Quotient;
      Remainder = -Remainder;
    } else if (RHS.isNegative()) {
      APInt::udivrem(LHS, -RHS, Quotient, Remainder);
      Quotient = -Quotient;
    } else {
      APInt::udivrem(LHS, RHS, Quotient, Remainder);
    }
  }



  APInt sadd_ov(const APInt &RHS, bool &Overflow) const;
  APInt uadd_ov(const APInt &RHS, bool &Overflow) const;
  APInt ssub_ov(const APInt &RHS, bool &Overflow) const;
  APInt usub_ov(const APInt &RHS, bool &Overflow) const;
  APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;
  APInt smul_ov(const APInt &RHS, bool &Overflow) const;
  APInt umul_ov(const APInt &RHS, bool &Overflow) const;
  APInt sshl_ov(unsigned Amt, bool &Overflow) const;



  bool operator[](unsigned bitPosition) const;







  bool operator==(const APInt& RHS) const {
    ((BitWidth == RHS.BitWidth && "Comparison requires equal bit widths") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 847, "BitWidth == RHS.BitWidth && \"Comparison requires equal bit widths\""));
    if (isSingleWord())
      return VAL == RHS.VAL;
    return EqualSlowCase(RHS);
  }





  bool operator==(uint64_t Val) const {
    if (isSingleWord())
      return VAL == Val;
    return EqualSlowCase(Val);
  }





  bool eq(const APInt &RHS) const {
    return (*this) == RHS;
  }





  bool operator!=(const APInt& RHS) const {
    return !((*this) == RHS);
  }





  bool operator!=(uint64_t Val) const {
    return !((*this) == Val);
  }





  bool ne(const APInt &RHS) const {
    return !((*this) == RHS);
  }





  bool ult(const APInt &RHS) const;





  bool ult(uint64_t RHS) const {
    return ult(APInt(getBitWidth(), RHS));
  }





  bool slt(const APInt& RHS) const;





  bool slt(uint64_t RHS) const {
    return slt(APInt(getBitWidth(), RHS));
  }





  bool ule(const APInt& RHS) const {
    return ult(RHS) || eq(RHS);
  }





  bool ule(uint64_t RHS) const {
    return ule(APInt(getBitWidth(), RHS));
  }





  bool sle(const APInt& RHS) const {
    return slt(RHS) || eq(RHS);
  }





  bool sle(uint64_t RHS) const {
    return sle(APInt(getBitWidth(), RHS));
  }





  bool ugt(const APInt& RHS) const {
    return !ult(RHS) && !eq(RHS);
  }





  bool ugt(uint64_t RHS) const {
    return ugt(APInt(getBitWidth(), RHS));
  }





  bool sgt(const APInt& RHS) const {
    return !slt(RHS) && !eq(RHS);
  }





  bool sgt(uint64_t RHS) const {
    return sgt(APInt(getBitWidth(), RHS));
  }





  bool uge(const APInt& RHS) const {
    return !ult(RHS);
  }





  bool uge(uint64_t RHS) const {
    return uge(APInt(getBitWidth(), RHS));
  }





  bool sge(const APInt& RHS) const {
    return !slt(RHS);
  }





  bool sge(uint64_t RHS) const {
    return sge(APInt(getBitWidth(), RHS));
  }






  bool intersects(const APInt &RHS) const {
    return (*this & RHS) != 0;
  }







  APInt trunc(unsigned width) const;






  APInt sext(unsigned width) const;





  APInt zext(unsigned width) const;




  APInt sextOrTrunc(unsigned width) const;




  APInt zextOrTrunc(unsigned width) const;





  void setAllBits() {
    if (isSingleWord())
      VAL = -1ULL;
    else {

      for (unsigned i = 0; i < getNumWords(); ++i)
 pVal[i] = -1ULL;
    }

    clearUnusedBits();
  }



  void setBit(unsigned bitPosition);


  void clearAllBits() {
    if (isSingleWord())
      VAL = 0;
    else
      memset(pVal, 0, getNumWords() * APINT_WORD_SIZE);
  }



  void clearBit(unsigned bitPosition);


  void flipAllBits() {
    if (isSingleWord())
      VAL ^= -1ULL;
    else {
      for (unsigned i = 0; i < getNumWords(); ++i)
        pVal[i] ^= -1ULL;
    }
    clearUnusedBits();
  }




  void flipBit(unsigned bitPosition);






  unsigned getBitWidth() const {
    return BitWidth;
  }




  unsigned getNumWords() const {
    return getNumWords(BitWidth);
  }





  static unsigned getNumWords(unsigned BitWidth) {
    return (BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD;
  }





  unsigned getActiveBits() const {
    return BitWidth - countLeadingZeros();
  }




  unsigned getActiveWords() const {
    return whichWord(getActiveBits()-1) + 1;
  }
  unsigned getMinSignedBits() const {
    if (isNegative())
      return BitWidth - countLeadingOnes() + 1;
    return getActiveBits()+1;
  }





  uint64_t getZExtValue() const {
    if (isSingleWord())
      return VAL;
    ((getActiveBits() <= 64 && "Too many bits for uint64_t") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 1166, "getActiveBits() <= 64 && \"Too many bits for uint64_t\""));
    return pVal[0];
  }





  int64_t getSExtValue() const {
    if (isSingleWord())
      return int64_t(VAL << (APINT_BITS_PER_WORD - BitWidth)) >>
                     (APINT_BITS_PER_WORD - BitWidth);
    ((getMinSignedBits() <= 64 && "Too many bits for int64_t") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/APInt.h", 1178, "getMinSignedBits() <= 64 && \"Too many bits for int64_t\""));
    return int64_t(pVal[0]);
  }




  static unsigned getBitsNeeded(StringRef str, uint8_t radix);







  unsigned countLeadingZeros() const {
    if (isSingleWord()) {
      unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth;
      return CountLeadingZeros_64(VAL) - unusedBits;
    }
    return countLeadingZerosSlowCase();
  }







  unsigned countLeadingOnes() const;



  unsigned getNumSignBits() const {
    return isNegative() ? countLeadingOnes() : countLeadingZeros();
  }
  unsigned countTrailingZeros() const;
  unsigned countTrailingOnes() const {
    if (isSingleWord())
      return CountTrailingOnes_64(VAL);
    return countTrailingOnesSlowCase();
  }







  unsigned countPopulation() const {
    if (isSingleWord())
      return CountPopulation_64(VAL);
    return countPopulationSlowCase();
  }




  void print(raw_ostream &OS, bool isSigned) const;



  void toString(SmallVectorImpl<char> &Str, unsigned Radix, bool Signed,
                bool formatAsCLiteral = false) const;



  void toStringUnsigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {
    toString(Str, Radix, false, false);
  }



  void toStringSigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {
    toString(Str, Radix, true, false);
  }




  std::string toString(unsigned Radix, bool Signed) const;



  APInt byteSwap() const;


  double roundToDouble(bool isSigned) const;


  double roundToDouble() const {
    return roundToDouble(false);
  }


  double signedRoundToDouble() const {
    return roundToDouble(true);
  }





  double bitsToDouble() const {
    union {
      uint64_t I;
      double D;
    } T;
    T.I = (isSingleWord() ? VAL : pVal[0]);
    return T.D;
  }





  float bitsToFloat() const {
    union {
      unsigned I;
      float F;
    } T;
    T.I = unsigned((isSingleWord() ? VAL : pVal[0]));
    return T.F;
  }




  static APInt doubleToBits(double V) {
    union {
      uint64_t I;
      double D;
    } T;
    T.D = V;
    return APInt(sizeof T * 8, T.I);
  }




  static APInt floatToBits(float V) {
    union {
      unsigned I;
      float F;
    } T;
    T.F = V;
    return APInt(sizeof T * 8, T.I);
  }






  unsigned logBase2() const {
    return BitWidth - 1 - countLeadingZeros();
  }


  unsigned ceilLogBase2() const {
    return BitWidth - (*this - 1).countLeadingZeros();
  }



  int32_t exactLogBase2() const {
    if (!isPowerOf2())
      return -1;
    return logBase2();
  }


  APInt sqrt() const;



  APInt abs() const {
    if (isNegative())
      return -(*this);
    return *this;
  }


  APInt multiplicativeInverse(const APInt& modulo) const;






  struct ms;
  ms magic() const;


  struct mu;
  mu magicu(unsigned LeadingZeros = 0) const;
  static void tcSet(integerPart *, integerPart, unsigned int);


  static void tcAssign(integerPart *, const integerPart *, unsigned int);


  static bool tcIsZero(const integerPart *, unsigned int);


  static int tcExtractBit(const integerPart *, unsigned int bit);





  static void tcExtract(integerPart *, unsigned int dstCount,
                        const integerPart *,
                        unsigned int srcBits, unsigned int srcLSB);


  static void tcSetBit(integerPart *, unsigned int bit);


  static void tcClearBit(integerPart *, unsigned int bit);




  static unsigned int tcLSB(const integerPart *, unsigned int);
  static unsigned int tcMSB(const integerPart *parts, unsigned int n);


  static void tcNegate(integerPart *, unsigned int);



  static integerPart tcAdd(integerPart *, const integerPart *,
                           integerPart carry, unsigned);



  static integerPart tcSubtract(integerPart *, const integerPart *,
                                integerPart carry, unsigned);
  static int tcMultiplyPart(integerPart *dst, const integerPart *src,
                            integerPart multiplier, integerPart carry,
                            unsigned int srcParts, unsigned int dstParts,
                            bool add);





  static int tcMultiply(integerPart *, const integerPart *,
                        const integerPart *, unsigned);





  static unsigned int tcFullMultiply(integerPart *, const integerPart *,
                                     const integerPart *, unsigned, unsigned);
  static int tcDivide(integerPart *lhs, const integerPart *rhs,
                      integerPart *remainder, integerPart *scratch,
                      unsigned int parts);



  static void tcShiftLeft(integerPart *, unsigned int parts,
                          unsigned int count);



  static void tcShiftRight(integerPart *, unsigned int parts,
                           unsigned int count);


  static void tcAnd(integerPart *, const integerPart *, unsigned int);
  static void tcOr(integerPart *, const integerPart *, unsigned int);
  static void tcXor(integerPart *, const integerPart *, unsigned int);
  static void tcComplement(integerPart *, unsigned int);


  static int tcCompare(const integerPart *, const integerPart *,
                       unsigned int);


  static integerPart tcIncrement(integerPart *, unsigned int);


  static void tcSetLeastSignificantBits(integerPart *, unsigned int,
                                        unsigned int bits);


  void dump() const;


};


struct APInt::ms {
  APInt m;
  unsigned s;
};


struct APInt::mu {
  APInt m;
  bool a;
  unsigned s;
};

inline bool operator==(uint64_t V1, const APInt& V2) {
  return V2 == V1;
}

inline bool operator!=(uint64_t V1, const APInt& V2) {
  return V2 != V1;
}

inline raw_ostream &operator<<(raw_ostream &OS, const APInt &I) {
  I.print(OS, true);
  return OS;
}

namespace APIntOps {


inline APInt smin(const APInt &A, const APInt &B) {
  return A.slt(B) ? A : B;
}


inline APInt smax(const APInt &A, const APInt &B) {
  return A.sgt(B) ? A : B;
}


inline APInt umin(const APInt &A, const APInt &B) {
  return A.ult(B) ? A : B;
}


inline APInt umax(const APInt &A, const APInt &B) {
  return A.ugt(B) ? A : B;
}


inline bool isIntN(unsigned N, const APInt& APIVal) {
  return APIVal.isIntN(N);
}


inline bool isSignedIntN(unsigned N, const APInt& APIVal) {
  return APIVal.isSignedIntN(N);
}



inline bool isMask(unsigned numBits, const APInt& APIVal) {
  return numBits <= APIVal.getBitWidth() &&
    APIVal == APInt::getLowBitsSet(APIVal.getBitWidth(), numBits);
}



inline bool isShiftedMask(unsigned numBits, const APInt& APIVal) {
  return isMask(numBits, (APIVal - APInt(numBits,1)) | APIVal);
}


inline APInt byteSwap(const APInt& APIVal) {
  return APIVal.byteSwap();
}


inline unsigned logBase2(const APInt& APIVal) {
  return APIVal.logBase2();
}





APInt GreatestCommonDivisor(const APInt& Val1, const APInt& Val2);



inline double RoundAPIntToDouble(const APInt& APIVal) {
  return APIVal.roundToDouble();
}



inline double RoundSignedAPIntToDouble(const APInt& APIVal) {
  return APIVal.signedRoundToDouble();
}


inline float RoundAPIntToFloat(const APInt& APIVal) {
  return float(RoundAPIntToDouble(APIVal));
}



inline float RoundSignedAPIntToFloat(const APInt& APIVal) {
  return float(APIVal.signedRoundToDouble());
}



APInt RoundDoubleToAPInt(double Double, unsigned width);



inline APInt RoundFloatToAPInt(float Float, unsigned width) {
  return RoundDoubleToAPInt(double(Float), width);
}



inline APInt ashr(const APInt& LHS, unsigned shiftAmt) {
  return LHS.ashr(shiftAmt);
}



inline APInt lshr(const APInt& LHS, unsigned shiftAmt) {
  return LHS.lshr(shiftAmt);
}



inline APInt shl(const APInt& LHS, unsigned shiftAmt) {
  return LHS.shl(shiftAmt);
}



inline APInt sdiv(const APInt& LHS, const APInt& RHS) {
  return LHS.sdiv(RHS);
}



inline APInt udiv(const APInt& LHS, const APInt& RHS) {
  return LHS.udiv(RHS);
}



inline APInt srem(const APInt& LHS, const APInt& RHS) {
  return LHS.srem(RHS);
}



inline APInt urem(const APInt& LHS, const APInt& RHS) {
  return LHS.urem(RHS);
}



inline APInt mul(const APInt& LHS, const APInt& RHS) {
  return LHS * RHS;
}



inline APInt add(const APInt& LHS, const APInt& RHS) {
  return LHS + RHS;
}



inline APInt sub(const APInt& LHS, const APInt& RHS) {
  return LHS - RHS;
}




inline APInt And(const APInt& LHS, const APInt& RHS) {
  return LHS & RHS;
}



inline APInt Or(const APInt& LHS, const APInt& RHS) {
  return LHS | RHS;
}



inline APInt Xor(const APInt& LHS, const APInt& RHS) {
  return LHS ^ RHS;
}



inline APInt Not(const APInt& APIVal) {
  return ~APIVal;
}

}

}

namespace llvm {


  typedef signed short exponent_t;

  struct fltSemantics;
  class APSInt;
  class StringRef;




  enum lostFraction {
    lfExactlyZero,
    lfLessThanHalf,
    lfExactlyHalf,
    lfMoreThanHalf
  };

  class APFloat {
  public:


    static const fltSemantics IEEEhalf;
    static const fltSemantics IEEEsingle;
    static const fltSemantics IEEEdouble;
    static const fltSemantics IEEEquad;
    static const fltSemantics PPCDoubleDouble;
    static const fltSemantics x87DoubleExtended;


    static const fltSemantics Bogus;

    static unsigned int semanticsPrecision(const fltSemantics &);


    enum cmpResult {
      cmpLessThan,
      cmpEqual,
      cmpGreaterThan,
      cmpUnordered
    };


    enum roundingMode {
      rmNearestTiesToEven,
      rmTowardPositive,
      rmTowardNegative,
      rmTowardZero,
      rmNearestTiesToAway
    };



    enum opStatus {
      opOK = 0x00,
      opInvalidOp = 0x01,
      opDivByZero = 0x02,
      opOverflow = 0x04,
      opUnderflow = 0x08,
      opInexact = 0x10
    };


    enum fltCategory {
      fcInfinity,
      fcNaN,
      fcNormal,
      fcZero
    };

    enum uninitializedTag {
      uninitialized
    };


    APFloat(const fltSemantics &);
    APFloat(const fltSemantics &, StringRef);
    APFloat(const fltSemantics &, integerPart);
    APFloat(const fltSemantics &, fltCategory, bool negative);
    APFloat(const fltSemantics &, uninitializedTag);
    explicit APFloat(double d);
    explicit APFloat(float f);
    explicit APFloat(const APInt &, bool isIEEE = false);
    APFloat(const APFloat &);
    ~APFloat();


    static APFloat getZero(const fltSemantics &Sem, bool Negative = false) {
      return APFloat(Sem, fcZero, Negative);
    }
    static APFloat getInf(const fltSemantics &Sem, bool Negative = false) {
      return APFloat(Sem, fcInfinity, Negative);
    }






    static APFloat getNaN(const fltSemantics &Sem, bool Negative = false,
                          unsigned type = 0) {
      if (type) {
        APInt fill(64, type);
        return getQNaN(Sem, Negative, &fill);
      } else {
        return getQNaN(Sem, Negative, 0);
      }
    }


    static APFloat getQNaN(const fltSemantics &Sem,
                           bool Negative = false,
                           const APInt *payload = 0) {
      return makeNaN(Sem, false, Negative, payload);
    }


    static APFloat getSNaN(const fltSemantics &Sem,
                           bool Negative = false,
                           const APInt *payload = 0) {
      return makeNaN(Sem, true, Negative, payload);
    }





    static APFloat getLargest(const fltSemantics &Sem, bool Negative = false);






    static APFloat getSmallest(const fltSemantics &Sem, bool Negative = false);





    static APFloat getSmallestNormalized(const fltSemantics &Sem,
                                         bool Negative = false);






    static APFloat getAllOnesValue(unsigned BitWidth, bool isIEEE = false);



    void Profile(FoldingSetNodeID& NID) const;


    void Emit(Serializer& S) const;


    static APFloat ReadVal(Deserializer& D);


    opStatus add(const APFloat &, roundingMode);
    opStatus subtract(const APFloat &, roundingMode);
    opStatus multiply(const APFloat &, roundingMode);
    opStatus divide(const APFloat &, roundingMode);

    opStatus remainder(const APFloat &);

    opStatus mod(const APFloat &, roundingMode);
    opStatus fusedMultiplyAdd(const APFloat &, const APFloat &, roundingMode);


    void changeSign();
    void clearSign();
    void copySign(const APFloat &);


    opStatus convert(const fltSemantics &, roundingMode, bool *);
    opStatus convertToInteger(integerPart *, unsigned int, bool,
                              roundingMode, bool *) const;
    opStatus convertToInteger(APSInt&, roundingMode, bool *) const;
    opStatus convertFromAPInt(const APInt &,
                              bool, roundingMode);
    opStatus convertFromSignExtendedInteger(const integerPart *, unsigned int,
                                            bool, roundingMode);
    opStatus convertFromZeroExtendedInteger(const integerPart *, unsigned int,
                                            bool, roundingMode);
    opStatus convertFromString(StringRef, roundingMode);
    APInt bitcastToAPInt() const;
    double convertToDouble() const;
    float convertToFloat() const;
    cmpResult compare(const APFloat &) const;


    bool bitwiseIsEqual(const APFloat &) const;





    unsigned int convertToHexString(char *dst, unsigned int hexDigits,
                                    bool upperCase, roundingMode) const;


    fltCategory getCategory() const { return category; }
    const fltSemantics &getSemantics() const { return *semantics; }
    bool isZero() const { return category == fcZero; }
    bool isNonZero() const { return category != fcZero; }
    bool isNaN() const { return category == fcNaN; }
    bool isInfinity() const { return category == fcInfinity; }
    bool isNegative() const { return sign; }
    bool isPosZero() const { return isZero() && !isNegative(); }
    bool isNegZero() const { return isZero() && isNegative(); }

    APFloat& operator=(const APFloat &);


    uint32_t getHashValue() const;
    void toString(SmallVectorImpl<char> &Str,
                  unsigned FormatPrecision = 0,
                  unsigned FormatMaxPadding = 3) const;



    bool getExactInverse(APFloat *inv) const;

  private:


    integerPart *significandParts();
    const integerPart *significandParts() const;
    unsigned int partCount() const;


    integerPart addSignificand(const APFloat &);
    integerPart subtractSignificand(const APFloat &, integerPart);
    lostFraction addOrSubtractSignificand(const APFloat &, bool subtract);
    lostFraction multiplySignificand(const APFloat &, const APFloat *);
    lostFraction divideSignificand(const APFloat &);
    void incrementSignificand();
    void initialize(const fltSemantics *);
    void shiftSignificandLeft(unsigned int);
    lostFraction shiftSignificandRight(unsigned int);
    unsigned int significandLSB() const;
    unsigned int significandMSB() const;
    void zeroSignificand();


    opStatus addOrSubtractSpecials(const APFloat &, bool subtract);
    opStatus divideSpecials(const APFloat &);
    opStatus multiplySpecials(const APFloat &);
    opStatus modSpecials(const APFloat &);


    static APFloat makeNaN(const fltSemantics &Sem, bool SNaN, bool Negative,
                           const APInt *fill);
    void makeNaN(bool SNaN = false, bool Neg = false, const APInt *fill = 0);
    opStatus normalize(roundingMode, lostFraction);
    opStatus addOrSubtract(const APFloat &, roundingMode, bool subtract);
    cmpResult compareAbsoluteValue(const APFloat &) const;
    opStatus handleOverflow(roundingMode);
    bool roundAwayFromZero(roundingMode, lostFraction, unsigned int) const;
    opStatus convertToSignExtendedInteger(integerPart *, unsigned int, bool,
                                          roundingMode, bool *) const;
    opStatus convertFromUnsignedParts(const integerPart *, unsigned int,
                                      roundingMode);
    opStatus convertFromHexadecimalString(StringRef, roundingMode);
    opStatus convertFromDecimalString(StringRef, roundingMode);
    char *convertNormalToHexString(char *, unsigned int, bool,
                                   roundingMode) const;
    opStatus roundSignificandWithExponent(const integerPart *, unsigned int,
                                          int, roundingMode);

    APInt convertHalfAPFloatToAPInt() const;
    APInt convertFloatAPFloatToAPInt() const;
    APInt convertDoubleAPFloatToAPInt() const;
    APInt convertQuadrupleAPFloatToAPInt() const;
    APInt convertF80LongDoubleAPFloatToAPInt() const;
    APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
    void initFromAPInt(const APInt& api, bool isIEEE = false);
    void initFromHalfAPInt(const APInt& api);
    void initFromFloatAPInt(const APInt& api);
    void initFromDoubleAPInt(const APInt& api);
    void initFromQuadrupleAPInt(const APInt &api);
    void initFromF80LongDoubleAPInt(const APInt& api);
    void initFromPPCDoubleDoubleAPInt(const APInt& api);

    void assign(const APFloat &);
    void copySignificand(const APFloat &);
    void freeSignificand();


    const fltSemantics *semantics;



    union Significand
    {
      integerPart part;
      integerPart *parts;
    } significand;


    exponent_t exponent;




    fltCategory category: 3;


    unsigned int sign: 1;





    exponent_t exponent2 : 11;
    unsigned int sign2: 1;
  };
}




namespace llvm {


namespace ARM_AM {
  enum ShiftOpc {
    no_shift = 0,
    asr,
    lsl,
    lsr,
    ror,
    rrx
  };

  enum AddrOpc {
    sub = 0,
    add
  };

  static inline const char *getAddrOpcStr(AddrOpc Op) {
    return Op == sub ? "-" : "";
  }

  static inline const char *getShiftOpcStr(ShiftOpc Op) {
    switch (Op) {
    default: ((0 && "Unknown shift opc!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 46, "0 && \"Unknown shift opc!\""));
    case ARM_AM::asr: return "asr";
    case ARM_AM::lsl: return "lsl";
    case ARM_AM::lsr: return "lsr";
    case ARM_AM::ror: return "ror";
    case ARM_AM::rrx: return "rrx";
    }
  }

  static inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
    switch (Op) {
    default: ((0 && "Unknown shift opc!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 57, "0 && \"Unknown shift opc!\""));
    case ARM_AM::asr: return 2;
    case ARM_AM::lsl: return 0;
    case ARM_AM::lsr: return 1;
    case ARM_AM::ror: return 3;
    }
  }

  enum AMSubMode {
    bad_am_submode = 0,
    ia,
    ib,
    da,
    db
  };

  static inline const char *getAMSubModeStr(AMSubMode Mode) {
    switch (Mode) {
    default: ((0 && "Unknown addressing sub-mode!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 75, "0 && \"Unknown addressing sub-mode!\""));
    case ARM_AM::ia: return "ia";
    case ARM_AM::ib: return "ib";
    case ARM_AM::da: return "da";
    case ARM_AM::db: return "db";
    }
  }



  static inline unsigned rotr32(unsigned Val, unsigned Amt) {
    ((Amt < 32 && "Invalid rotate amount") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 86, "Amt < 32 && \"Invalid rotate amount\""));
    return (Val >> Amt) | (Val << ((32-Amt)&31));
  }



  static inline unsigned rotl32(unsigned Val, unsigned Amt) {
    ((Amt < 32 && "Invalid rotate amount") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 93, "Amt < 32 && \"Invalid rotate amount\""));
    return (Val << Amt) | (Val >> ((32-Amt)&31));
  }
  static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
    return ShOp | (Imm << 3);
  }
  static inline unsigned getSORegOffset(unsigned Op) {
    return Op >> 3;
  }
  static inline ShiftOpc getSORegShOp(unsigned Op) {
    return (ShiftOpc)(Op & 7);
  }



  static inline unsigned getSOImmValImm(unsigned Imm) {
    return Imm & 0xFF;
  }


  static inline unsigned getSOImmValRot(unsigned Imm) {
    return (Imm >> 8) * 2;
  }





  static inline unsigned getSOImmValRotate(unsigned Imm) {


    if ((Imm & ~255U) == 0) return 0;


    unsigned TZ = CountTrailingZeros_32(Imm);



    unsigned RotAmt = TZ & ~1;


    if ((rotr32(Imm, RotAmt) & ~255U) == 0)
      return (32-RotAmt)&31;



    if (Imm & 63U) {
      unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
      unsigned RotAmt2 = TZ2 & ~1;
      if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
        return (32-RotAmt2)&31;
    }




    return (32-RotAmt)&31;
  }




  static inline int getSOImmVal(unsigned Arg) {


    if ((Arg & ~255U) == 0) return Arg;

    unsigned RotAmt = getSOImmValRotate(Arg);


    if (rotr32(~255U, RotAmt) & Arg)
      return -1;


    return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
  }



  static inline bool isSOImmTwoPartVal(unsigned V) {

    V = rotr32(~255U, getSOImmValRotate(V)) & V;
    if (V == 0)
      return false;


    V = rotr32(~255U, getSOImmValRotate(V)) & V;
    return V == 0;
  }



  static inline unsigned getSOImmTwoPartFirst(unsigned V) {
    return rotr32(255U, getSOImmValRotate(V)) & V;
  }



  static inline unsigned getSOImmTwoPartSecond(unsigned V) {

    V = rotr32(~255U, getSOImmValRotate(V)) & V;


    ((V == (rotr32(255U, getSOImmValRotate(V)) & V)) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 211, "V == (rotr32(255U, getSOImmValRotate(V)) & V)"));
    return V;
  }



  static inline unsigned getThumbImmValShift(unsigned Imm) {


    if ((Imm & ~255U) == 0) return 0;


    return CountTrailingZeros_32(Imm);
  }



  static inline bool isThumbImmShiftedVal(unsigned V) {

    V = (~255U << getThumbImmValShift(V)) & V;
    return V == 0;
  }



  static inline unsigned getThumbImm16ValShift(unsigned Imm) {


    if ((Imm & ~65535U) == 0) return 0;


    return CountTrailingZeros_32(Imm);
  }



  static inline bool isThumbImm16ShiftedVal(unsigned V) {

    V = (~65535U << getThumbImm16ValShift(V)) & V;
    return V == 0;
  }



  static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
    return V >> getThumbImmValShift(V);
  }
  static inline int getT2SOImmValSplatVal(unsigned V) {
    unsigned u, Vs, Imm;

    if ((V & 0xffffff00) == 0)
      return V;


    Vs = ((V & 0xff) == 0) ? V >> 8 : V;

    Imm = Vs & 0xff;

    u = Imm | (Imm << 16);


    if (Vs == u)
      return (((Vs == V) ? 1 : 2) << 8) | Imm;


    if (Vs == (u | (u << 8)))
      return (3 << 8) | Imm;

    return -1;
  }





  static inline int getT2SOImmValRotateVal(unsigned V) {
    unsigned RotAmt = CountLeadingZeros_32(V);
    if (RotAmt >= 24)
      return -1;


    if ((rotr32(0xff000000U, RotAmt) & V) == V)
      return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);

    return -1;
  }





  static inline int getT2SOImmVal(unsigned Arg) {

    int Splat = getT2SOImmValSplatVal(Arg);
    if (Splat != -1)
      return Splat;


    int Rot = getT2SOImmValRotateVal(Arg);
    if (Rot != -1)
      return Rot;

    return -1;
  }

  static inline unsigned getT2SOImmValRotate(unsigned V) {
    if ((V & ~255U) == 0) return 0;

    unsigned RotAmt = CountTrailingZeros_32(V);
    return (32 - RotAmt) & 31;
  }

  static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
    unsigned V = Imm;



    if (getT2SOImmValSplatVal(V) != -1)
      return false;
    V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
    if (V == 0)
      return false;


    if (getT2SOImmVal(V) != -1) return true;


    V = Imm;
    if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
      V &= ~0xff00ff00U;
    else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
      V &= ~0x00ff00ffU;

    if (getT2SOImmVal(V) != -1) return true;


    return false;
  }

  static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
    ((isT2SOImmTwoPartVal(Imm) && "Immedate cannot be encoded as two part immediate!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 363, "isT2SOImmTwoPartVal(Imm) && \"Immedate cannot be encoded as two part immediate!\""));


    unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;

    if (getT2SOImmVal(V) != -1) return V;


    if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
      return Imm & 0xff00ff00U;


    ((getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 374, "getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1"));
    return Imm & 0x00ff00ffU;
  }

  static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {

    Imm ^= getT2SOImmTwoPartFirst(Imm);

    ((getT2SOImmVal(Imm) != -1 && "Unable to encode second part of T2 two part SO immediate") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 383, "getT2SOImmVal(Imm) != -1 && \"Unable to encode second part of T2 two part SO immediate\""));

    return Imm;
  }
  static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
                                   unsigned IdxMode = 0) {
    ((Imm12 < (1 << 12) && "Imm too large!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 408, "Imm12 < (1 << 12) && \"Imm too large!\""));
    bool isSub = Opc == sub;
    return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
  }
  static inline unsigned getAM2Offset(unsigned AM2Opc) {
    return AM2Opc & ((1 << 12)-1);
  }
  static inline AddrOpc getAM2Op(unsigned AM2Opc) {
    return ((AM2Opc >> 12) & 1) ? sub : add;
  }
  static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
    return (ShiftOpc)((AM2Opc >> 13) & 7);
  }
  static inline unsigned getAM2IdxMode(unsigned AM2Opc) {
    return (AM2Opc >> 16);
  }
  static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
                                   unsigned IdxMode = 0) {
    bool isSub = Opc == sub;
    return ((int)isSub << 8) | Offset | (IdxMode << 9);
  }
  static inline unsigned char getAM3Offset(unsigned AM3Opc) {
    return AM3Opc & 0xFF;
  }
  static inline AddrOpc getAM3Op(unsigned AM3Opc) {
    return ((AM3Opc >> 8) & 1) ? sub : add;
  }
  static inline unsigned getAM3IdxMode(unsigned AM3Opc) {
    return (AM3Opc >> 9);
  }
  static inline AMSubMode getAM4SubMode(unsigned Mode) {
    return (AMSubMode)(Mode & 0x7);
  }

  static inline unsigned getAM4ModeImm(AMSubMode SubMode) {
    return (int)SubMode;
  }
  static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
    bool isSub = Opc == sub;
    return ((int)isSub << 8) | Offset;
  }
  static inline unsigned char getAM5Offset(unsigned AM5Opc) {
    return AM5Opc & 0xFF;
  }
  static inline AddrOpc getAM5Op(unsigned AM5Opc) {
    return ((AM5Opc >> 8) & 1) ? sub : add;
  }
  static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) {
    return (OpCmode << 8) | Val;
  }
  static inline unsigned getNEONModImmOpCmode(unsigned ModImm) {
    return (ModImm >> 8) & 0x1f;
  }
  static inline unsigned getNEONModImmVal(unsigned ModImm) {
    return ModImm & 0xff;
  }




  static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) {
    unsigned OpCmode = getNEONModImmOpCmode(ModImm);
    unsigned Imm8 = getNEONModImmVal(ModImm);
    uint64_t Val = 0;

    if (OpCmode == 0xe) {

      Val = Imm8;
      EltBits = 8;
    } else if ((OpCmode & 0xc) == 0x8) {

      unsigned ByteNum = (OpCmode & 0x6) >> 1;
      Val = Imm8 << (8 * ByteNum);
      EltBits = 16;
    } else if ((OpCmode & 0x8) == 0) {

      unsigned ByteNum = (OpCmode & 0x6) >> 1;
      Val = Imm8 << (8 * ByteNum);
      EltBits = 32;
    } else if ((OpCmode & 0xe) == 0xc) {

      unsigned ByteNum = 1 + (OpCmode & 0x1);
      Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
      EltBits = 32;
    } else if (OpCmode == 0x1e) {

      for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
        if ((ModImm >> ByteNum) & 1)
          Val |= (uint64_t)0xff << (8 * ByteNum);
      }
      EltBits = 64;
    } else {
      ((false && "Unsupported NEON immediate") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h", 572, "false && \"Unsupported NEON immediate\""));
    }
    return Val;
  }

  AMSubMode getLoadStoreMultipleSubMode(int Opcode);




  static inline float getFPImmFloat(unsigned Imm) {

    union {
      uint32_t I;
      float F;
    } FPUnion;

    uint8_t Sign = (Imm >> 7) & 0x1;
    uint8_t Exp = (Imm >> 4) & 0x7;
    uint8_t Mantissa = Imm & 0xf;






    FPUnion.I = 0;
    FPUnion.I |= Sign << 31;
    FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
    FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
    FPUnion.I |= (Exp & 0x3) << 23;
    FPUnion.I |= Mantissa << 19;
    return FPUnion.F;
  }




  static inline int getFP32Imm(const APInt &Imm) {
    uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
    int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127;
    int64_t Mantissa = Imm.getZExtValue() & 0x7fffff;



    if (Mantissa & 0x7ffff)
      return -1;
    Mantissa >>= 19;
    if ((Mantissa & 0xf) != Mantissa)
      return -1;


    if (Exp < -3 || Exp > 4)
      return -1;
    Exp = ((Exp+3) & 0x7) ^ 4;

    return ((int)Sign << 7) | (Exp << 4) | Mantissa;
  }

  static inline int getFP32Imm(const APFloat &FPImm) {
    return getFP32Imm(FPImm.bitcastToAPInt());
  }




  static inline int getFP64Imm(const APInt &Imm) {
    uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
    int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023;
    uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;



    if (Mantissa & 0xffffffffffffULL)
      return -1;
    Mantissa >>= 48;
    if ((Mantissa & 0xf) != Mantissa)
      return -1;


    if (Exp < -3 || Exp > 4)
      return -1;
    Exp = ((Exp+3) & 0x7) ^ 4;

    return ((int)Sign << 7) | (Exp << 4) | Mantissa;
  }

  static inline int getFP64Imm(const APFloat &FPImm) {
    return getFP64Imm(FPImm.bitcastToAPInt());
  }

}
}


namespace llvm {
template<typename From> struct simplify_type {
  typedef From SimpleType;


  static SimpleType &getSimplifiedValue(From &Val) { return Val; }
};

template<typename From> struct simplify_type<const From> {
  typedef const From SimpleType;
  static SimpleType &getSimplifiedValue(const From &Val) {
    return simplify_type<From>::getSimplifiedValue(static_cast<From&>(Val));
  }
};




template <typename To, typename From>
struct isa_impl {
  static inline bool doit(const From &Val) {
    return To::classof(&Val);
  }
};

template <typename To, typename From> struct isa_impl_cl {
  static inline bool doit(const From &Val) {
    return isa_impl<To, From>::doit(Val);
  }
};

template <typename To, typename From> struct isa_impl_cl<To, const From> {
  static inline bool doit(const From &Val) {
    return isa_impl<To, From>::doit(Val);
  }
};

template <typename To, typename From> struct isa_impl_cl<To, From*> {
  static inline bool doit(const From *Val) {
    return isa_impl<To, From>::doit(*Val);
  }
};

template <typename To, typename From> struct isa_impl_cl<To, const From*> {
  static inline bool doit(const From *Val) {
    return isa_impl<To, From>::doit(*Val);
  }
};

template <typename To, typename From> struct isa_impl_cl<To, const From*const> {
  static inline bool doit(const From *Val) {
    return isa_impl<To, From>::doit(*Val);
  }
};

template<typename To, typename From, typename SimpleFrom>
struct isa_impl_wrap {


  static bool doit(const From &Val) {
    return isa_impl_wrap<To, SimpleFrom,
      typename simplify_type<SimpleFrom>::SimpleType>::doit(
                          simplify_type<From>::getSimplifiedValue(Val));
  }
};

template<typename To, typename FromTy>
struct isa_impl_wrap<To, FromTy, FromTy> {

  static bool doit(const FromTy &Val) {
    return isa_impl_cl<To,FromTy>::doit(Val);
  }
};






template <class X, class Y>
inline bool isa(const Y &Val) {
  return isa_impl_wrap<X, Y, typename simplify_type<Y>::SimpleType>::doit(Val);
}





template<class To, class From> struct cast_retty;




template<class To, class From> struct cast_retty_impl {
  typedef To& ret_type;
};
template<class To, class From> struct cast_retty_impl<To, const From> {
  typedef const To &ret_type;
};

template<class To, class From> struct cast_retty_impl<To, From*> {
  typedef To* ret_type;
};

template<class To, class From> struct cast_retty_impl<To, const From*> {
  typedef const To* ret_type;
};

template<class To, class From> struct cast_retty_impl<To, const From*const> {
  typedef const To* ret_type;
};


template<class To, class From, class SimpleFrom>
struct cast_retty_wrap {



  typedef typename cast_retty<To, SimpleFrom>::ret_type ret_type;
};

template<class To, class FromTy>
struct cast_retty_wrap<To, FromTy, FromTy> {

  typedef typename cast_retty_impl<To,FromTy>::ret_type ret_type;
};

template<class To, class From>
struct cast_retty {
  typedef typename cast_retty_wrap<To, From,
                   typename simplify_type<From>::SimpleType>::ret_type ret_type;
};




template<class To, class From, class SimpleFrom> struct cast_convert_val {

  static typename cast_retty<To, From>::ret_type doit(const From &Val) {
    return cast_convert_val<To, SimpleFrom,
      typename simplify_type<SimpleFrom>::SimpleType>::doit(
                          simplify_type<From>::getSimplifiedValue(Val));
  }
};

template<class To, class FromTy> struct cast_convert_val<To,FromTy,FromTy> {

  static typename cast_retty<To, FromTy>::ret_type doit(const FromTy &Val) {
    typename cast_retty<To, FromTy>::ret_type Res2
     = (typename cast_retty<To, FromTy>::ret_type)const_cast<FromTy&>(Val);
    return Res2;
  }
};
template <class X, class Y>
inline typename cast_retty<X, Y>::ret_type cast(const Y &Val) {
  ((isa<X>(Val) && "cast<Ty>() argument of incompatible type!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Support/Casting.h", 194, "isa<X>(Val) && \"cast<Ty>() argument of incompatible type!\""));
  return cast_convert_val<X, Y,
                          typename simplify_type<Y>::SimpleType>::doit(Val);
}




template <class X, class Y>
inline typename cast_retty<X, Y*>::ret_type cast_or_null(Y *Val) {
  if (Val == 0) return 0;
  ((isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Support/Casting.h", 205, "isa<X>(Val) && \"cast_or_null<Ty>() argument of incompatible type!\""));
  return cast<X>(Val);
}
template <class X, class Y>
inline typename cast_retty<X, Y>::ret_type dyn_cast(const Y &Val) {
  return isa<X>(Val) ? cast<X, Y>(Val) : 0;
}




template <class X, class Y>
inline typename cast_retty<X, Y*>::ret_type dyn_cast_or_null(Y *Val) {
  return (Val && isa<X>(Val)) ? cast<X>(Val) : 0;
}

}


namespace llvm {
class MCAsmInfo;
class MCAsmLayout;
class MCAssembler;
class MCContext;
class MCSection;
class MCSectionData;
class MCSymbol;
class MCValue;
class raw_ostream;
class StringRef;
typedef DenseMap<const MCSectionData*, uint64_t> SectionAddrMap;



class MCExpr {
public:
  enum ExprKind {
    Binary,
    Constant,
    SymbolRef,
    Unary,
    Target
  };

private:
  ExprKind Kind;

  MCExpr(const MCExpr&);
  void operator=(const MCExpr&);

  bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler *Asm,
                          const MCAsmLayout *Layout,
                          const SectionAddrMap *Addrs) const;
protected:
  explicit MCExpr(ExprKind _Kind) : Kind(_Kind) {}

  bool EvaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm,
                                 const MCAsmLayout *Layout,
                                 const SectionAddrMap *Addrs,
                                 bool InSet) const;
public:



  ExprKind getKind() const { return Kind; }





  void print(raw_ostream &OS) const;
  void dump() const;
  bool EvaluateAsAbsolute(int64_t &Res) const;
  bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler &Asm) const;
  bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout) const;
  bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout,
                          const SectionAddrMap &Addrs) const;







  bool EvaluateAsRelocatable(MCValue &Res, const MCAsmLayout &Layout) const;





  const MCSection *FindAssociatedSection() const;



  static bool classof(const MCExpr *) { return true; }
};

inline raw_ostream &operator<<(raw_ostream &OS, const MCExpr &E) {
  E.print(OS);
  return OS;
}


class MCConstantExpr : public MCExpr {
  int64_t Value;

  explicit MCConstantExpr(int64_t _Value)
    : MCExpr(MCExpr::Constant), Value(_Value) {}

public:



  static const MCConstantExpr *Create(int64_t Value, MCContext &Ctx);





  int64_t getValue() const { return Value; }



  static bool classof(const MCExpr *E) {
    return E->getKind() == MCExpr::Constant;
  }
  static bool classof(const MCConstantExpr *) { return true; }
};







class MCSymbolRefExpr : public MCExpr {
public:
  enum VariantKind {
    VK_None,
    VK_Invalid,

    VK_GOT,
    VK_GOTOFF,
    VK_GOTPCREL,
    VK_GOTTPOFF,
    VK_INDNTPOFF,
    VK_NTPOFF,
    VK_GOTNTPOFF,
    VK_PLT,
    VK_TLSGD,
    VK_TLSLD,
    VK_TLSLDM,
    VK_TPOFF,
    VK_DTPOFF,
    VK_TLVP,

    VK_ARM_PLT,
    VK_ARM_TLSGD,
    VK_ARM_GOT,
    VK_ARM_GOTOFF,
    VK_ARM_TPOFF,
    VK_ARM_GOTTPOFF,

    VK_PPC_TOC,
    VK_PPC_DARWIN_HA16,
    VK_PPC_DARWIN_LO16,
    VK_PPC_GAS_HA16,
    VK_PPC_GAS_LO16
  };

private:

  const MCSymbol *Symbol;


  const VariantKind Kind;

  explicit MCSymbolRefExpr(const MCSymbol *_Symbol, VariantKind _Kind)
    : MCExpr(MCExpr::SymbolRef), Symbol(_Symbol), Kind(_Kind) {}

public:



  static const MCSymbolRefExpr *Create(const MCSymbol *Symbol, MCContext &Ctx) {
    return MCSymbolRefExpr::Create(Symbol, VK_None, Ctx);
  }

  static const MCSymbolRefExpr *Create(const MCSymbol *Symbol, VariantKind Kind,
                                       MCContext &Ctx);
  static const MCSymbolRefExpr *Create(StringRef Name, VariantKind Kind,
                                       MCContext &Ctx);





  const MCSymbol &getSymbol() const { return *Symbol; }

  VariantKind getKind() const { return Kind; }





  static StringRef getVariantKindName(VariantKind Kind);

  static VariantKind getVariantKindForName(StringRef Name);



  static bool classof(const MCExpr *E) {
    return E->getKind() == MCExpr::SymbolRef;
  }
  static bool classof(const MCSymbolRefExpr *) { return true; }
};


class MCUnaryExpr : public MCExpr {
public:
  enum Opcode {
    LNot,
    Minus,
    Not,
    Plus
  };

private:
  Opcode Op;
  const MCExpr *Expr;

  MCUnaryExpr(Opcode _Op, const MCExpr *_Expr)
    : MCExpr(MCExpr::Unary), Op(_Op), Expr(_Expr) {}

public:



  static const MCUnaryExpr *Create(Opcode Op, const MCExpr *Expr,
                                   MCContext &Ctx);
  static const MCUnaryExpr *CreateLNot(const MCExpr *Expr, MCContext &Ctx) {
    return Create(LNot, Expr, Ctx);
  }
  static const MCUnaryExpr *CreateMinus(const MCExpr *Expr, MCContext &Ctx) {
    return Create(Minus, Expr, Ctx);
  }
  static const MCUnaryExpr *CreateNot(const MCExpr *Expr, MCContext &Ctx) {
    return Create(Not, Expr, Ctx);
  }
  static const MCUnaryExpr *CreatePlus(const MCExpr *Expr, MCContext &Ctx) {
    return Create(Plus, Expr, Ctx);
  }






  Opcode getOpcode() const { return Op; }


  const MCExpr *getSubExpr() const { return Expr; }



  static bool classof(const MCExpr *E) {
    return E->getKind() == MCExpr::Unary;
  }
  static bool classof(const MCUnaryExpr *) { return true; }
};


class MCBinaryExpr : public MCExpr {
public:
  enum Opcode {
    Add,
    And,
    Div,
    EQ,
    GT,

    GTE,

    LAnd,
    LOr,
    LT,

    LTE,

    Mod,
    Mul,
    NE,
    Or,
    Shl,
    Shr,
    Sub,
    Xor
  };

private:
  Opcode Op;
  const MCExpr *LHS, *RHS;

  MCBinaryExpr(Opcode _Op, const MCExpr *_LHS, const MCExpr *_RHS)
    : MCExpr(MCExpr::Binary), Op(_Op), LHS(_LHS), RHS(_RHS) {}

public:



  static const MCBinaryExpr *Create(Opcode Op, const MCExpr *LHS,
                                    const MCExpr *RHS, MCContext &Ctx);
  static const MCBinaryExpr *CreateAdd(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Add, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateAnd(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(And, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateDiv(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Div, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateEQ(const MCExpr *LHS, const MCExpr *RHS,
                                      MCContext &Ctx) {
    return Create(EQ, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateGT(const MCExpr *LHS, const MCExpr *RHS,
                                      MCContext &Ctx) {
    return Create(GT, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateGTE(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(GTE, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateLAnd(const MCExpr *LHS, const MCExpr *RHS,
                                        MCContext &Ctx) {
    return Create(LAnd, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateLOr(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(LOr, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateLT(const MCExpr *LHS, const MCExpr *RHS,
                                      MCContext &Ctx) {
    return Create(LT, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateLTE(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(LTE, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateMod(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Mod, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateMul(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Mul, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateNE(const MCExpr *LHS, const MCExpr *RHS,
                                      MCContext &Ctx) {
    return Create(NE, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateOr(const MCExpr *LHS, const MCExpr *RHS,
                                      MCContext &Ctx) {
    return Create(Or, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateShl(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Shl, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateShr(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Shr, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateSub(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Sub, LHS, RHS, Ctx);
  }
  static const MCBinaryExpr *CreateXor(const MCExpr *LHS, const MCExpr *RHS,
                                       MCContext &Ctx) {
    return Create(Xor, LHS, RHS, Ctx);
  }






  Opcode getOpcode() const { return Op; }


  const MCExpr *getLHS() const { return LHS; }


  const MCExpr *getRHS() const { return RHS; }



  static bool classof(const MCExpr *E) {
    return E->getKind() == MCExpr::Binary;
  }
  static bool classof(const MCBinaryExpr *) { return true; }
};






class MCTargetExpr : public MCExpr {
  virtual void Anchor();
protected:
  MCTargetExpr() : MCExpr(Target) {}
  virtual ~MCTargetExpr() {}
public:

  virtual void PrintImpl(raw_ostream &OS) const = 0;
  virtual bool EvaluateAsRelocatableImpl(MCValue &Res,
                                         const MCAsmLayout *Layout) const = 0;
  virtual void AddValueSymbols(MCAssembler *) const = 0;
  virtual const MCSection *FindAssociatedSection() const = 0;

  static bool classof(const MCExpr *E) {
    return E->getKind() == MCExpr::Target;
  }
  static bool classof(const MCTargetExpr *) { return true; }
};

}

namespace llvm {

class ARMMCExpr : public MCTargetExpr {
public:
  enum VariantKind {
    VK_ARM_None,
    VK_ARM_HI16,
    VK_ARM_LO16
  };

private:
  const VariantKind Kind;
  const MCExpr *Expr;

  explicit ARMMCExpr(VariantKind _Kind, const MCExpr *_Expr)
    : Kind(_Kind), Expr(_Expr) {}

public:



  static const ARMMCExpr *Create(VariantKind Kind, const MCExpr *Expr,
                                      MCContext &Ctx);

  static const ARMMCExpr *CreateUpper16(const MCExpr *Expr, MCContext &Ctx) {
    return Create(VK_ARM_HI16, Expr, Ctx);
  }

  static const ARMMCExpr *CreateLower16(const MCExpr *Expr, MCContext &Ctx) {
    return Create(VK_ARM_LO16, Expr, Ctx);
  }






  VariantKind getKind() const { return Kind; }


  const MCExpr *getSubExpr() const { return Expr; }



  void PrintImpl(raw_ostream &OS) const;
  bool EvaluateAsRelocatableImpl(MCValue &Res,
                                 const MCAsmLayout *Layout) const;
  void AddValueSymbols(MCAssembler *) const;
  const MCSection *FindAssociatedSection() const {
    return getSubExpr()->FindAssociatedSection();
  }

  static bool classof(const MCExpr *E) {
    return E->getKind() == MCExpr::Target;
  }

  static bool classof(const ARMMCExpr *) { return true; }

};
}

namespace llvm {




struct EDInstInfo {
  uint8_t instructionType;
  uint8_t numOperands;
  uint8_t operandTypes[13];
  uint8_t operandFlags[13];
  const signed char operandOrders[2][13];
};

}
namespace llvm {
class raw_ostream;
class MCAsmInfo;
class MCInstPrinter;
class MCExpr;



class MCOperand {
  enum MachineOperandType {
    kInvalid,
    kRegister,
    kImmediate,
    kFPImmediate,
    kExpr
  };
  unsigned char Kind;

  union {
    unsigned RegVal;
    int64_t ImmVal;
    double FPImmVal;
    const MCExpr *ExprVal;
  };
public:

  MCOperand() : Kind(kInvalid), FPImmVal(0.0) {}

  bool isValid() const { return Kind != kInvalid; }
  bool isReg() const { return Kind == kRegister; }
  bool isImm() const { return Kind == kImmediate; }
  bool isFPImm() const { return Kind == kFPImmediate; }
  bool isExpr() const { return Kind == kExpr; }


  unsigned getReg() const {
    ((isReg() && "This is not a register operand!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 59, "isReg() && \"This is not a register operand!\""));
    return RegVal;
  }


  void setReg(unsigned Reg) {
    ((isReg() && "This is not a register operand!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 65, "isReg() && \"This is not a register operand!\""));
    RegVal = Reg;
  }

  int64_t getImm() const {
    ((isImm() && "This is not an immediate") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 70, "isImm() && \"This is not an immediate\""));
    return ImmVal;
  }
  void setImm(int64_t Val) {
    ((isImm() && "This is not an immediate") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 74, "isImm() && \"This is not an immediate\""));
    ImmVal = Val;
  }

  double getFPImm() const {
    ((isFPImm() && "This is not an FP immediate") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 79, "isFPImm() && \"This is not an FP immediate\""));
    return FPImmVal;
  }

  void setFPImm(double Val) {
    ((isFPImm() && "This is not an FP immediate") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 84, "isFPImm() && \"This is not an FP immediate\""));
    FPImmVal = Val;
  }

  const MCExpr *getExpr() const {
    ((isExpr() && "This is not an expression") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 89, "isExpr() && \"This is not an expression\""));
    return ExprVal;
  }
  void setExpr(const MCExpr *Val) {
    ((isExpr() && "This is not an expression") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCInst.h", 93, "isExpr() && \"This is not an expression\""));
    ExprVal = Val;
  }

  static MCOperand CreateReg(unsigned Reg) {
    MCOperand Op;
    Op.Kind = kRegister;
    Op.RegVal = Reg;
    return Op;
  }
  static MCOperand CreateImm(int64_t Val) {
    MCOperand Op;
    Op.Kind = kImmediate;
    Op.ImmVal = Val;
    return Op;
  }
  static MCOperand CreateFPImm(double Val) {
    MCOperand Op;
    Op.Kind = kFPImmediate;
    Op.FPImmVal = Val;
    return Op;
  }
  static MCOperand CreateExpr(const MCExpr *Val) {
    MCOperand Op;
    Op.Kind = kExpr;
    Op.ExprVal = Val;
    return Op;
  }

  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
  void dump() const;
};




class MCInst {
  unsigned Opcode;
  SmallVector<MCOperand, 8> Operands;
public:
  MCInst() : Opcode(0) {}

  void setOpcode(unsigned Op) { Opcode = Op; }

  unsigned getOpcode() const { return Opcode; }

  const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
  MCOperand &getOperand(unsigned i) { return Operands[i]; }
  unsigned getNumOperands() const { return Operands.size(); }

  void addOperand(const MCOperand &Op) {
    Operands.push_back(Op);
  }

  void clear() { Operands.clear(); }
  size_t size() { return Operands.size(); }

  typedef SmallVector<MCOperand, 8>::iterator iterator;
  iterator begin() { return Operands.begin(); }
  iterator end() { return Operands.end(); }
  iterator insert(iterator I, const MCOperand &Op) {
    return Operands.insert(I, Op);
  }

  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
  void dump() const;




  void dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI = 0,
                   const MCInstPrinter *Printer = 0,
                   StringRef Separator = " ") const;
};

inline raw_ostream& operator<<(raw_ostream &OS, const MCOperand &MO) {
  MO.print(OS, 0);
  return OS;
}

inline raw_ostream& operator<<(raw_ostream &OS, const MCInst &MI) {
  MI.print(OS, 0);
  return OS;
}

}

namespace llvm {
class SectionKind {
  enum Kind {

    Metadata,


    Text,




    ReadOnly,







           Mergeable1ByteCString,


           Mergeable2ByteCString,


           Mergeable4ByteCString,




        MergeableConst,



            MergeableConst4,



            MergeableConst8,



            MergeableConst16,
           ThreadBSS,


           ThreadData,





           BSS,



               BSSLocal,


               BSSExtern,




           Common,




           DataRel,





               DataRelLocal,




                   DataNoRel,







           ReadOnlyWithRel,






               ReadOnlyWithRelLocal

  } K : 8;
public:

  bool isMetadata() const { return K == Metadata; }
  bool isText() const { return K == Text; }

  bool isReadOnly() const {
    return K == ReadOnly || isMergeableCString() ||
           isMergeableConst();
  }

  bool isMergeableCString() const {
    return K == Mergeable1ByteCString || K == Mergeable2ByteCString ||
           K == Mergeable4ByteCString;
  }
  bool isMergeable1ByteCString() const { return K == Mergeable1ByteCString; }
  bool isMergeable2ByteCString() const { return K == Mergeable2ByteCString; }
  bool isMergeable4ByteCString() const { return K == Mergeable4ByteCString; }

  bool isMergeableConst() const {
    return K == MergeableConst || K == MergeableConst4 ||
           K == MergeableConst8 || K == MergeableConst16;
  }
  bool isMergeableConst4() const { return K == MergeableConst4; }
  bool isMergeableConst8() const { return K == MergeableConst8; }
  bool isMergeableConst16() const { return K == MergeableConst16; }

  bool isWriteable() const {
    return isThreadLocal() || isGlobalWriteableData();
  }

  bool isThreadLocal() const {
    return K == ThreadData || K == ThreadBSS;
  }

  bool isThreadBSS() const { return K == ThreadBSS; }
  bool isThreadData() const { return K == ThreadData; }

  bool isGlobalWriteableData() const {
    return isBSS() || isCommon() || isDataRel() || isReadOnlyWithRel();
  }

  bool isBSS() const { return K == BSS || K == BSSLocal || K == BSSExtern; }
  bool isBSSLocal() const { return K == BSSLocal; }
  bool isBSSExtern() const { return K == BSSExtern; }

  bool isCommon() const { return K == Common; }

  bool isDataRel() const {
    return K == DataRel || K == DataRelLocal || K == DataNoRel;
  }

  bool isDataRelLocal() const {
    return K == DataRelLocal || K == DataNoRel;
  }

  bool isDataNoRel() const { return K == DataNoRel; }

  bool isReadOnlyWithRel() const {
    return K == ReadOnlyWithRel || K == ReadOnlyWithRelLocal;
  }

  bool isReadOnlyWithRelLocal() const {
    return K == ReadOnlyWithRelLocal;
  }
private:
  static SectionKind get(Kind K) {
    SectionKind Res;
    Res.K = K;
    return Res;
  }
public:

  static SectionKind getMetadata() { return get(Metadata); }
  static SectionKind getText() { return get(Text); }
  static SectionKind getReadOnly() { return get(ReadOnly); }
  static SectionKind getMergeable1ByteCString() {
    return get(Mergeable1ByteCString);
  }
  static SectionKind getMergeable2ByteCString() {
    return get(Mergeable2ByteCString);
  }
  static SectionKind getMergeable4ByteCString() {
    return get(Mergeable4ByteCString);
  }
  static SectionKind getMergeableConst() { return get(MergeableConst); }
  static SectionKind getMergeableConst4() { return get(MergeableConst4); }
  static SectionKind getMergeableConst8() { return get(MergeableConst8); }
  static SectionKind getMergeableConst16() { return get(MergeableConst16); }
  static SectionKind getThreadBSS() { return get(ThreadBSS); }
  static SectionKind getThreadData() { return get(ThreadData); }
  static SectionKind getBSS() { return get(BSS); }
  static SectionKind getBSSLocal() { return get(BSSLocal); }
  static SectionKind getBSSExtern() { return get(BSSExtern); }
  static SectionKind getCommon() { return get(Common); }
  static SectionKind getDataRel() { return get(DataRel); }
  static SectionKind getDataRelLocal() { return get(DataRelLocal); }
  static SectionKind getDataNoRel() { return get(DataNoRel); }
  static SectionKind getReadOnlyWithRel() { return get(ReadOnlyWithRel); }
  static SectionKind getReadOnlyWithRelLocal(){
    return get(ReadOnlyWithRelLocal);
  }
};

}
namespace llvm {
  class MCSymbol;

class MachineLocation {
private:
  bool IsRegister;
  unsigned Register;
  int Offset;
public:
  enum {


    VirtualFP = ~0U
  };
  MachineLocation()
    : IsRegister(false), Register(0), Offset(0) {}
  explicit MachineLocation(unsigned R)
    : IsRegister(true), Register(R), Offset(0) {}
  MachineLocation(unsigned R, int O)
    : IsRegister(false), Register(R), Offset(O) {}

  bool operator==(const MachineLocation &Other) const {
      return IsRegister == Other.IsRegister && Register == Other.Register &&
        Offset == Other.Offset;
  }


  bool isReg() const { return IsRegister; }
  unsigned getReg() const { return Register; }
  int getOffset() const { return Offset; }
  void setIsRegister(bool Is) { IsRegister = Is; }
  void setRegister(unsigned R) { Register = R; }
  void setOffset(int O) { Offset = O; }
  void set(unsigned R) {
    IsRegister = true;
    Register = R;
    Offset = 0;
  }
  void set(unsigned R, int O) {
    IsRegister = false;
    Register = R;
    Offset = O;
  }


  void dump();

};



class MachineMove {
private:


  MCSymbol *Label;


  MachineLocation Destination, Source;
public:
  MachineMove() : Label(0) {}

  MachineMove(MCSymbol *label, const MachineLocation &D,
              const MachineLocation &S)
  : Label(label), Destination(D), Source(S) {}


  MCSymbol *getLabel() const { return Label; }
  const MachineLocation &getDestination() const { return Destination; }
  const MachineLocation &getSource() const { return Source; }
};

}
namespace llvm {
  class format_object_base;
  template <typename T>
  class SmallVectorImpl;





class raw_ostream {
private:

  void operator=(const raw_ostream &);
  raw_ostream(const raw_ostream &);
  char *OutBufStart, *OutBufEnd, *OutBufCur;

  enum BufferKind {
    Unbuffered = 0,
    InternalBuffer,
    ExternalBuffer
  } BufferMode;

public:

  enum Colors {
    BLACK=0,
    RED,
    GREEN,
    YELLOW,
    BLUE,
    MAGENTA,
    CYAN,
    WHITE,
    SAVEDCOLOR
  };

  explicit raw_ostream(bool unbuffered=false)
    : BufferMode(unbuffered ? Unbuffered : InternalBuffer) {

    OutBufStart = OutBufEnd = OutBufCur = 0;
  }

  virtual ~raw_ostream();


  uint64_t tell() const { return current_pos() + GetNumBytesInBuffer(); }







  void SetBuffered();



  void SetBufferSize(size_t Size) {
    flush();
    SetBufferAndMode(new char[Size], Size, InternalBuffer);
  }

  size_t GetBufferSize() const {


    if (BufferMode != Unbuffered && OutBufStart == 0)
      return preferred_buffer_size();


    return OutBufEnd - OutBufStart;
  }





  void SetUnbuffered() {
    flush();
    SetBufferAndMode(0, 0, Unbuffered);
  }

  size_t GetNumBytesInBuffer() const {
    return OutBufCur - OutBufStart;
  }





  void flush() {
    if (OutBufCur != OutBufStart)
      flush_nonempty();
  }

  raw_ostream &operator<<(char C) {
    if (OutBufCur >= OutBufEnd)
      return write(C);
    *OutBufCur++ = C;
    return *this;
  }

  raw_ostream &operator<<(unsigned char C) {
    if (OutBufCur >= OutBufEnd)
      return write(C);
    *OutBufCur++ = C;
    return *this;
  }

  raw_ostream &operator<<(signed char C) {
    if (OutBufCur >= OutBufEnd)
      return write(C);
    *OutBufCur++ = C;
    return *this;
  }

  raw_ostream &operator<<(StringRef Str) {

    size_t Size = Str.size();


    if (OutBufCur+Size > OutBufEnd)
      return write(Str.data(), Size);

    memcpy(OutBufCur, Str.data(), Size);
    OutBufCur += Size;
    return *this;
  }

  raw_ostream &operator<<(const char *Str) {



    return this->operator<<(StringRef(Str));
  }

  raw_ostream &operator<<(const std::string &Str) {

    return write(Str.data(), Str.length());
  }

  raw_ostream &operator<<(unsigned long N);
  raw_ostream &operator<<(long N);
  raw_ostream &operator<<(unsigned long long N);
  raw_ostream &operator<<(long long N);
  raw_ostream &operator<<(const void *P);
  raw_ostream &operator<<(unsigned int N) {
    return this->operator<<(static_cast<unsigned long>(N));
  }

  raw_ostream &operator<<(int N) {
    return this->operator<<(static_cast<long>(N));
  }

  raw_ostream &operator<<(double N);


  raw_ostream &write_hex(unsigned long long N);



  raw_ostream &write_escaped(StringRef Str, bool UseHexEscapes = false);

  raw_ostream &write(unsigned char C);
  raw_ostream &write(const char *Ptr, size_t Size);


  raw_ostream &operator<<(const format_object_base &Fmt);


  raw_ostream &indent(unsigned NumSpaces);
  virtual raw_ostream &changeColor(enum Colors, bool = false, bool = false) {
    return *this; }



  virtual raw_ostream &resetColor() { return *this; }




  virtual bool is_displayed() const { return false; }





private:
  virtual void write_impl(const char *Ptr, size_t Size) = 0;


  virtual void handle();



  virtual uint64_t current_pos() const = 0;

protected:




  void SetBuffer(char *BufferStart, size_t Size) {
    SetBufferAndMode(BufferStart, Size, ExternalBuffer);
  }



  virtual size_t preferred_buffer_size() const;



  const char *getBufferStart() const { return OutBufStart; }




private:

  void SetBufferAndMode(char *BufferStart, size_t Size, BufferKind Mode);




  void flush_nonempty();



  void copy_to_buffer(const char *Ptr, size_t Size);
};







class raw_fd_ostream : public raw_ostream {
  int FD;
  bool ShouldClose;



  bool Error;



  bool UseAtomicWrites;

  uint64_t pos;


  virtual void write_impl(const char *Ptr, size_t Size);



  virtual uint64_t current_pos() const { return pos; }


  virtual size_t preferred_buffer_size() const;



  void error_detected() { Error = true; }

public:

  enum {


    F_Excl = 1,




    F_Append = 2,



    F_Binary = 4
  };
  raw_fd_ostream(const char *Filename, std::string &ErrorInfo,
                 unsigned Flags = 0);



  raw_fd_ostream(int fd, bool shouldClose, bool unbuffered=false);

  ~raw_fd_ostream();



  void close();



  uint64_t seek(uint64_t off);







  void SetUseAtomicWrites(bool Value) {
    UseAtomicWrites = Value;
  }

  virtual raw_ostream &changeColor(enum Colors colors, bool bold=false,
                                   bool bg=false);
  virtual raw_ostream &resetColor();

  virtual bool is_displayed() const;





  bool has_error() const {
    return Error;
  }
  void clear_error() {
    Error = false;
  }
};



raw_ostream &outs();



raw_ostream &errs();



raw_ostream &nulls();







class raw_string_ostream : public raw_ostream {
  std::string &OS;


  virtual void write_impl(const char *Ptr, size_t Size);



  virtual uint64_t current_pos() const { return OS.size(); }
public:
  explicit raw_string_ostream(std::string &O) : OS(O) {}
  ~raw_string_ostream();



  std::string& str() {
    flush();
    return OS;
  }
};




class raw_svector_ostream : public raw_ostream {
  SmallVectorImpl<char> &OS;


  virtual void write_impl(const char *Ptr, size_t Size);



  virtual uint64_t current_pos() const;
public:




  explicit raw_svector_ostream(SmallVectorImpl<char> &O);
  ~raw_svector_ostream();




  void resync();



  StringRef str();
};


class raw_null_ostream : public raw_ostream {

  virtual void write_impl(const char *Ptr, size_t size);



  virtual uint64_t current_pos() const;

public:
  explicit raw_null_ostream() {}
  ~raw_null_ostream();
};

}



namespace llvm {
class MCAsmLayout;
class MCAssembler;
class MCFixup;
class MCFragment;
class MCSymbol;
class MCSymbolData;
class MCSymbolRefExpr;
class MCValue;
class raw_ostream;
class MCObjectWriter {
  MCObjectWriter(const MCObjectWriter &);
  void operator=(const MCObjectWriter &);

protected:
  raw_ostream &OS;

  unsigned IsLittleEndian : 1;

protected:
  MCObjectWriter(raw_ostream &_OS, bool _IsLittleEndian)
    : OS(_OS), IsLittleEndian(_IsLittleEndian) {}

public:
  virtual ~MCObjectWriter();

  bool isLittleEndian() const { return IsLittleEndian; }

  raw_ostream &getStream() { return OS; }
  virtual void ExecutePostLayoutBinding(MCAssembler &Asm,
                                        const MCAsmLayout &Layout) = 0;







  virtual void RecordRelocation(const MCAssembler &Asm,
                                const MCAsmLayout &Layout,
                                const MCFragment *Fragment,
                                const MCFixup &Fixup, MCValue Target,
                                uint64_t &FixedValue) = 0;






  bool
  IsSymbolRefDifferenceFullyResolved(const MCAssembler &Asm,
                                     const MCSymbolRefExpr *A,
                                     const MCSymbolRefExpr *B,
                                     bool InSet) const;

  virtual bool
  IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
                                         const MCSymbolData &DataA,
                                         const MCFragment &FB,
                                         bool InSet,
                                         bool IsPCRel) const;







  virtual void WriteObject(MCAssembler &Asm,
                           const MCAsmLayout &Layout) = 0;





  void Write8(uint8_t Value) {
    OS << char(Value);
  }

  void WriteLE16(uint16_t Value) {
    Write8(uint8_t(Value >> 0));
    Write8(uint8_t(Value >> 8));
  }

  void WriteLE32(uint32_t Value) {
    WriteLE16(uint16_t(Value >> 0));
    WriteLE16(uint16_t(Value >> 16));
  }

  void WriteLE64(uint64_t Value) {
    WriteLE32(uint32_t(Value >> 0));
    WriteLE32(uint32_t(Value >> 32));
  }

  void WriteBE16(uint16_t Value) {
    Write8(uint8_t(Value >> 8));
    Write8(uint8_t(Value >> 0));
  }

  void WriteBE32(uint32_t Value) {
    WriteBE16(uint16_t(Value >> 16));
    WriteBE16(uint16_t(Value >> 0));
  }

  void WriteBE64(uint64_t Value) {
    WriteBE32(uint32_t(Value >> 32));
    WriteBE32(uint32_t(Value >> 0));
  }

  void Write16(uint16_t Value) {
    if (IsLittleEndian)
      WriteLE16(Value);
    else
      WriteBE16(Value);
  }

  void Write32(uint32_t Value) {
    if (IsLittleEndian)
      WriteLE32(Value);
    else
      WriteBE32(Value);
  }

  void Write64(uint64_t Value) {
    if (IsLittleEndian)
      WriteLE64(Value);
    else
      WriteBE64(Value);
  }

  void WriteZeros(unsigned N) {
    const char Zeros[16] = { 0 };

    for (unsigned i = 0, e = N / 16; i != e; ++i)
      OS << StringRef(Zeros, 16);

    OS << StringRef(Zeros, N % 16);
  }

  void WriteBytes(StringRef Str, unsigned ZeroFillSize = 0) {
    (((ZeroFillSize == 0 || Str.size () <= ZeroFillSize) && "data size greater than fill size, unexpected large write will occur") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCObjectWriter.h", 180, "(ZeroFillSize == 0 || Str.size () <= ZeroFillSize) && \"data size greater than fill size, unexpected large write will occur\""));

    OS << Str;
    if (ZeroFillSize)
      WriteZeros(ZeroFillSize - Str.size());
  }




  static void EncodeSLEB128(int64_t Value, raw_ostream &OS);

  static void EncodeULEB128(uint64_t Value, raw_ostream &OS);
};

MCObjectWriter *createWinCOFFObjectWriter(raw_ostream &OS, bool is64Bit);

}

namespace llvm {




enum {
  LLVMDebugVersion = (11 << 16),
  LLVMDebugVersion10 = (10 << 16),
  LLVMDebugVersion9 = (9 << 16),
  LLVMDebugVersion8 = (8 << 16),
  LLVMDebugVersion7 = (7 << 16),
  LLVMDebugVersion6 = (6 << 16),
  LLVMDebugVersion5 = (5 << 16),
  LLVMDebugVersion4 = (4 << 16),
  LLVMDebugVersionMask = 0xffff0000
};

namespace dwarf {
enum llvm_dwarf_constants {

  DW_TAG_invalid = ~0U,

  DW_TAG_auto_variable = 0x100,
  DW_TAG_arg_variable = 0x101,
  DW_TAG_return_variable = 0x102,
  DW_TAG_vector_type = 0x103,

  DW_TAG_user_base = 0x1000,

  DW_CIE_VERSION = 1,
  DW_CIE_ID = 0xffffffff
};

enum dwarf_constants {
  DWARF_VERSION = 2,


  DW_TAG_array_type = 0x01,
  DW_TAG_class_type = 0x02,
  DW_TAG_entry_point = 0x03,
  DW_TAG_enumeration_type = 0x04,
  DW_TAG_formal_parameter = 0x05,
  DW_TAG_imported_declaration = 0x08,
  DW_TAG_label = 0x0a,
  DW_TAG_lexical_block = 0x0b,
  DW_TAG_member = 0x0d,
  DW_TAG_pointer_type = 0x0f,
  DW_TAG_reference_type = 0x10,
  DW_TAG_compile_unit = 0x11,
  DW_TAG_string_type = 0x12,
  DW_TAG_structure_type = 0x13,
  DW_TAG_subroutine_type = 0x15,
  DW_TAG_typedef = 0x16,
  DW_TAG_union_type = 0x17,
  DW_TAG_unspecified_parameters = 0x18,
  DW_TAG_variant = 0x19,
  DW_TAG_common_block = 0x1a,
  DW_TAG_common_inclusion = 0x1b,
  DW_TAG_inheritance = 0x1c,
  DW_TAG_inlined_subroutine = 0x1d,
  DW_TAG_module = 0x1e,
  DW_TAG_ptr_to_member_type = 0x1f,
  DW_TAG_set_type = 0x20,
  DW_TAG_subrange_type = 0x21,
  DW_TAG_with_stmt = 0x22,
  DW_TAG_access_declaration = 0x23,
  DW_TAG_base_type = 0x24,
  DW_TAG_catch_block = 0x25,
  DW_TAG_const_type = 0x26,
  DW_TAG_constant = 0x27,
  DW_TAG_enumerator = 0x28,
  DW_TAG_file_type = 0x29,
  DW_TAG_friend = 0x2a,
  DW_TAG_namelist = 0x2b,
  DW_TAG_namelist_item = 0x2c,
  DW_TAG_packed_type = 0x2d,
  DW_TAG_subprogram = 0x2e,
  DW_TAG_template_type_parameter = 0x2f,
  DW_TAG_template_value_parameter = 0x30,
  DW_TAG_thrown_type = 0x31,
  DW_TAG_try_block = 0x32,
  DW_TAG_variant_part = 0x33,
  DW_TAG_variable = 0x34,
  DW_TAG_volatile_type = 0x35,
  DW_TAG_dwarf_procedure = 0x36,
  DW_TAG_restrict_type = 0x37,
  DW_TAG_interface_type = 0x38,
  DW_TAG_namespace = 0x39,
  DW_TAG_imported_module = 0x3a,
  DW_TAG_unspecified_type = 0x3b,
  DW_TAG_partial_unit = 0x3c,
  DW_TAG_imported_unit = 0x3d,
  DW_TAG_condition = 0x3f,
  DW_TAG_shared_type = 0x40,
  DW_TAG_type_unit = 0x41,
  DW_TAG_rvalue_reference_type = 0x42,
  DW_TAG_template_alias = 0x43,
  DW_TAG_MIPS_loop = 0x4081,
  DW_TAG_format_label = 0x4101,
  DW_TAG_function_template = 0x4102,
  DW_TAG_class_template = 0x4103,
  DW_TAG_GNU_template_template_param = 0x4106,
  DW_TAG_GNU_template_parameter_pack = 0x4107,
  DW_TAG_GNU_formal_parameter_pack = 0x4108,
  DW_TAG_lo_user = 0x4080,
  DW_TAG_hi_user = 0xffff,


  DW_CHILDREN_no = 0x00,
  DW_CHILDREN_yes = 0x01,


  DW_AT_sibling = 0x01,
  DW_AT_location = 0x02,
  DW_AT_name = 0x03,
  DW_AT_ordering = 0x09,
  DW_AT_byte_size = 0x0b,
  DW_AT_bit_offset = 0x0c,
  DW_AT_bit_size = 0x0d,
  DW_AT_stmt_list = 0x10,
  DW_AT_low_pc = 0x11,
  DW_AT_high_pc = 0x12,
  DW_AT_language = 0x13,
  DW_AT_discr = 0x15,
  DW_AT_discr_value = 0x16,
  DW_AT_visibility = 0x17,
  DW_AT_import = 0x18,
  DW_AT_string_length = 0x19,
  DW_AT_common_reference = 0x1a,
  DW_AT_comp_dir = 0x1b,
  DW_AT_const_value = 0x1c,
  DW_AT_containing_type = 0x1d,
  DW_AT_default_value = 0x1e,
  DW_AT_inline = 0x20,
  DW_AT_is_optional = 0x21,
  DW_AT_lower_bound = 0x22,
  DW_AT_producer = 0x25,
  DW_AT_prototyped = 0x27,
  DW_AT_return_addr = 0x2a,
  DW_AT_start_scope = 0x2c,
  DW_AT_bit_stride = 0x2e,
  DW_AT_upper_bound = 0x2f,
  DW_AT_abstract_origin = 0x31,
  DW_AT_accessibility = 0x32,
  DW_AT_address_class = 0x33,
  DW_AT_artificial = 0x34,
  DW_AT_base_types = 0x35,
  DW_AT_calling_convention = 0x36,
  DW_AT_count = 0x37,
  DW_AT_data_member_location = 0x38,
  DW_AT_decl_column = 0x39,
  DW_AT_decl_file = 0x3a,
  DW_AT_decl_line = 0x3b,
  DW_AT_declaration = 0x3c,
  DW_AT_discr_list = 0x3d,
  DW_AT_encoding = 0x3e,
  DW_AT_external = 0x3f,
  DW_AT_frame_base = 0x40,
  DW_AT_friend = 0x41,
  DW_AT_identifier_case = 0x42,
  DW_AT_macro_info = 0x43,
  DW_AT_namelist_item = 0x44,
  DW_AT_priority = 0x45,
  DW_AT_segment = 0x46,
  DW_AT_specification = 0x47,
  DW_AT_static_link = 0x48,
  DW_AT_type = 0x49,
  DW_AT_use_location = 0x4a,
  DW_AT_variable_parameter = 0x4b,
  DW_AT_virtuality = 0x4c,
  DW_AT_vtable_elem_location = 0x4d,
  DW_AT_allocated = 0x4e,
  DW_AT_associated = 0x4f,
  DW_AT_data_location = 0x50,
  DW_AT_byte_stride = 0x51,
  DW_AT_entry_pc = 0x52,
  DW_AT_use_UTF8 = 0x53,
  DW_AT_extension = 0x54,
  DW_AT_ranges = 0x55,
  DW_AT_trampoline = 0x56,
  DW_AT_call_column = 0x57,
  DW_AT_call_file = 0x58,
  DW_AT_call_line = 0x59,
  DW_AT_description = 0x5a,
  DW_AT_binary_scale = 0x5b,
  DW_AT_decimal_scale = 0x5c,
  DW_AT_small = 0x5d,
  DW_AT_decimal_sign = 0x5e,
  DW_AT_digit_count = 0x5f,
  DW_AT_picture_string = 0x60,
  DW_AT_mutable = 0x61,
  DW_AT_threads_scaled = 0x62,
  DW_AT_explicit = 0x63,
  DW_AT_object_pointer = 0x64,
  DW_AT_endianity = 0x65,
  DW_AT_elemental = 0x66,
  DW_AT_pure = 0x67,
  DW_AT_recursive = 0x68,
  DW_AT_signature = 0x69,
  DW_AT_main_subprogram = 0x6a,
  DW_AT_data_bit_offset = 0x6b,
  DW_AT_const_expr = 0x6c,
  DW_AT_enum_class = 0x6d,
  DW_AT_linkage_name = 0x6e,
  DW_AT_MIPS_loop_begin = 0x2002,
  DW_AT_MIPS_tail_loop_begin = 0x2003,
  DW_AT_MIPS_epilog_begin = 0x2004,
  DW_AT_MIPS_loop_unroll_factor = 0x2005,
  DW_AT_MIPS_software_pipeline_depth = 0x2006,
  DW_AT_MIPS_linkage_name = 0x2007,
  DW_AT_MIPS_stride = 0x2008,
  DW_AT_MIPS_abstract_name = 0x2009,
  DW_AT_MIPS_clone_origin = 0x200a,
  DW_AT_MIPS_has_inlines = 0x200b,
  DW_AT_MIPS_stride_byte = 0x200c,
  DW_AT_MIPS_stride_elem = 0x200d,
  DW_AT_MIPS_ptr_dopetype = 0x200e,
  DW_AT_MIPS_allocatable_dopetype = 0x200f,
  DW_AT_MIPS_assumed_shape_dopetype = 0x2010,
  DW_AT_sf_names = 0x2101,
  DW_AT_src_info = 0x2102,
  DW_AT_mac_info = 0x2103,
  DW_AT_src_coords = 0x2104,
  DW_AT_body_begin = 0x2105,
  DW_AT_body_end = 0x2106,
  DW_AT_GNU_vector = 0x2107,
  DW_AT_GNU_template_name = 0x2110,
  DW_AT_MIPS_assumed_size = 0x2011,
  DW_AT_lo_user = 0x2000,
  DW_AT_hi_user = 0x3fff,


  DW_AT_APPLE_optimized = 0x3fe1,
  DW_AT_APPLE_flags = 0x3fe2,
  DW_AT_APPLE_isa = 0x3fe3,
  DW_AT_APPLE_block = 0x3fe4,
  DW_AT_APPLE_major_runtime_vers = 0x3fe5,
  DW_AT_APPLE_runtime_class = 0x3fe6,
  DW_AT_APPLE_omit_frame_ptr = 0x3fe7,
  DW_AT_APPLE_property_name = 0x3fe8,
  DW_AT_APPLE_property_getter = 0x3fe9,
  DW_AT_APPLE_property_setter = 0x3fea,
  DW_AT_APPLE_property_attribute = 0x3feb,
  DW_AT_APPLE_objc_complete_type = 0x3fec,


  DW_FORM_addr = 0x01,
  DW_FORM_block2 = 0x03,
  DW_FORM_block4 = 0x04,
  DW_FORM_data2 = 0x05,
  DW_FORM_data4 = 0x06,
  DW_FORM_data8 = 0x07,
  DW_FORM_string = 0x08,
  DW_FORM_block = 0x09,
  DW_FORM_block1 = 0x0a,
  DW_FORM_data1 = 0x0b,
  DW_FORM_flag = 0x0c,
  DW_FORM_sdata = 0x0d,
  DW_FORM_strp = 0x0e,
  DW_FORM_udata = 0x0f,
  DW_FORM_ref_addr = 0x10,
  DW_FORM_ref1 = 0x11,
  DW_FORM_ref2 = 0x12,
  DW_FORM_ref4 = 0x13,
  DW_FORM_ref8 = 0x14,
  DW_FORM_ref_udata = 0x15,
  DW_FORM_indirect = 0x16,
  DW_FORM_sec_offset = 0x17,
  DW_FORM_exprloc = 0x18,
  DW_FORM_flag_present = 0x19,
  DW_FORM_ref_sig8 = 0x20,


  DW_OP_addr = 0x03,
  DW_OP_deref = 0x06,
  DW_OP_const1u = 0x08,
  DW_OP_const1s = 0x09,
  DW_OP_const2u = 0x0a,
  DW_OP_const2s = 0x0b,
  DW_OP_const4u = 0x0c,
  DW_OP_const4s = 0x0d,
  DW_OP_const8u = 0x0e,
  DW_OP_const8s = 0x0f,
  DW_OP_constu = 0x10,
  DW_OP_consts = 0x11,
  DW_OP_dup = 0x12,
  DW_OP_drop = 0x13,
  DW_OP_over = 0x14,
  DW_OP_pick = 0x15,
  DW_OP_swap = 0x16,
  DW_OP_rot = 0x17,
  DW_OP_xderef = 0x18,
  DW_OP_abs = 0x19,
  DW_OP_and = 0x1a,
  DW_OP_div = 0x1b,
  DW_OP_minus = 0x1c,
  DW_OP_mod = 0x1d,
  DW_OP_mul = 0x1e,
  DW_OP_neg = 0x1f,
  DW_OP_not = 0x20,
  DW_OP_or = 0x21,
  DW_OP_plus = 0x22,
  DW_OP_plus_uconst = 0x23,
  DW_OP_shl = 0x24,
  DW_OP_shr = 0x25,
  DW_OP_shra = 0x26,
  DW_OP_xor = 0x27,
  DW_OP_skip = 0x2f,
  DW_OP_bra = 0x28,
  DW_OP_eq = 0x29,
  DW_OP_ge = 0x2a,
  DW_OP_gt = 0x2b,
  DW_OP_le = 0x2c,
  DW_OP_lt = 0x2d,
  DW_OP_ne = 0x2e,
  DW_OP_lit0 = 0x30,
  DW_OP_lit1 = 0x31,
  DW_OP_lit2 = 0x32,
  DW_OP_lit3 = 0x33,
  DW_OP_lit4 = 0x34,
  DW_OP_lit5 = 0x35,
  DW_OP_lit6 = 0x36,
  DW_OP_lit7 = 0x37,
  DW_OP_lit8 = 0x38,
  DW_OP_lit9 = 0x39,
  DW_OP_lit10 = 0x3a,
  DW_OP_lit11 = 0x3b,
  DW_OP_lit12 = 0x3c,
  DW_OP_lit13 = 0x3d,
  DW_OP_lit14 = 0x3e,
  DW_OP_lit15 = 0x3f,
  DW_OP_lit16 = 0x40,
  DW_OP_lit17 = 0x41,
  DW_OP_lit18 = 0x42,
  DW_OP_lit19 = 0x43,
  DW_OP_lit20 = 0x44,
  DW_OP_lit21 = 0x45,
  DW_OP_lit22 = 0x46,
  DW_OP_lit23 = 0x47,
  DW_OP_lit24 = 0x48,
  DW_OP_lit25 = 0x49,
  DW_OP_lit26 = 0x4a,
  DW_OP_lit27 = 0x4b,
  DW_OP_lit28 = 0x4c,
  DW_OP_lit29 = 0x4d,
  DW_OP_lit30 = 0x4e,
  DW_OP_lit31 = 0x4f,
  DW_OP_reg0 = 0x50,
  DW_OP_reg1 = 0x51,
  DW_OP_reg2 = 0x52,
  DW_OP_reg3 = 0x53,
  DW_OP_reg4 = 0x54,
  DW_OP_reg5 = 0x55,
  DW_OP_reg6 = 0x56,
  DW_OP_reg7 = 0x57,
  DW_OP_reg8 = 0x58,
  DW_OP_reg9 = 0x59,
  DW_OP_reg10 = 0x5a,
  DW_OP_reg11 = 0x5b,
  DW_OP_reg12 = 0x5c,
  DW_OP_reg13 = 0x5d,
  DW_OP_reg14 = 0x5e,
  DW_OP_reg15 = 0x5f,
  DW_OP_reg16 = 0x60,
  DW_OP_reg17 = 0x61,
  DW_OP_reg18 = 0x62,
  DW_OP_reg19 = 0x63,
  DW_OP_reg20 = 0x64,
  DW_OP_reg21 = 0x65,
  DW_OP_reg22 = 0x66,
  DW_OP_reg23 = 0x67,
  DW_OP_reg24 = 0x68,
  DW_OP_reg25 = 0x69,
  DW_OP_reg26 = 0x6a,
  DW_OP_reg27 = 0x6b,
  DW_OP_reg28 = 0x6c,
  DW_OP_reg29 = 0x6d,
  DW_OP_reg30 = 0x6e,
  DW_OP_reg31 = 0x6f,
  DW_OP_breg0 = 0x70,
  DW_OP_breg1 = 0x71,
  DW_OP_breg2 = 0x72,
  DW_OP_breg3 = 0x73,
  DW_OP_breg4 = 0x74,
  DW_OP_breg5 = 0x75,
  DW_OP_breg6 = 0x76,
  DW_OP_breg7 = 0x77,
  DW_OP_breg8 = 0x78,
  DW_OP_breg9 = 0x79,
  DW_OP_breg10 = 0x7a,
  DW_OP_breg11 = 0x7b,
  DW_OP_breg12 = 0x7c,
  DW_OP_breg13 = 0x7d,
  DW_OP_breg14 = 0x7e,
  DW_OP_breg15 = 0x7f,
  DW_OP_breg16 = 0x80,
  DW_OP_breg17 = 0x81,
  DW_OP_breg18 = 0x82,
  DW_OP_breg19 = 0x83,
  DW_OP_breg20 = 0x84,
  DW_OP_breg21 = 0x85,
  DW_OP_breg22 = 0x86,
  DW_OP_breg23 = 0x87,
  DW_OP_breg24 = 0x88,
  DW_OP_breg25 = 0x89,
  DW_OP_breg26 = 0x8a,
  DW_OP_breg27 = 0x8b,
  DW_OP_breg28 = 0x8c,
  DW_OP_breg29 = 0x8d,
  DW_OP_breg30 = 0x8e,
  DW_OP_breg31 = 0x8f,
  DW_OP_regx = 0x90,
  DW_OP_fbreg = 0x91,
  DW_OP_bregx = 0x92,
  DW_OP_piece = 0x93,
  DW_OP_deref_size = 0x94,
  DW_OP_xderef_size = 0x95,
  DW_OP_nop = 0x96,
  DW_OP_push_object_address = 0x97,
  DW_OP_call2 = 0x98,
  DW_OP_call4 = 0x99,
  DW_OP_call_ref = 0x9a,
  DW_OP_form_tls_address = 0x9b,
  DW_OP_call_frame_cfa = 0x9c,
  DW_OP_bit_piece = 0x9d,
  DW_OP_implicit_value = 0x9e,
  DW_OP_stack_value = 0x9f,
  DW_OP_lo_user = 0xe0,
  DW_OP_hi_user = 0xff,


  DW_ATE_address = 0x01,
  DW_ATE_boolean = 0x02,
  DW_ATE_complex_float = 0x03,
  DW_ATE_float = 0x04,
  DW_ATE_signed = 0x05,
  DW_ATE_signed_char = 0x06,
  DW_ATE_unsigned = 0x07,
  DW_ATE_unsigned_char = 0x08,
  DW_ATE_imaginary_float = 0x09,
  DW_ATE_packed_decimal = 0x0a,
  DW_ATE_numeric_string = 0x0b,
  DW_ATE_edited = 0x0c,
  DW_ATE_signed_fixed = 0x0d,
  DW_ATE_unsigned_fixed = 0x0e,
  DW_ATE_decimal_float = 0x0f,
  DW_ATE_UTF = 0x10,
  DW_ATE_lo_user = 0x80,
  DW_ATE_hi_user = 0xff,


  DW_DS_unsigned = 0x01,
  DW_DS_leading_overpunch = 0x02,
  DW_DS_trailing_overpunch = 0x03,
  DW_DS_leading_separate = 0x04,
  DW_DS_trailing_separate = 0x05,


  DW_END_default = 0x00,
  DW_END_big = 0x01,
  DW_END_little = 0x02,
  DW_END_lo_user = 0x40,
  DW_END_hi_user = 0xff,


  DW_ACCESS_public = 0x01,
  DW_ACCESS_protected = 0x02,
  DW_ACCESS_private = 0x03,


  DW_VIS_local = 0x01,
  DW_VIS_exported = 0x02,
  DW_VIS_qualified = 0x03,


  DW_VIRTUALITY_none = 0x00,
  DW_VIRTUALITY_virtual = 0x01,
  DW_VIRTUALITY_pure_virtual = 0x02,


  DW_LANG_C89 = 0x0001,
  DW_LANG_C = 0x0002,
  DW_LANG_Ada83 = 0x0003,
  DW_LANG_C_plus_plus = 0x0004,
  DW_LANG_Cobol74 = 0x0005,
  DW_LANG_Cobol85 = 0x0006,
  DW_LANG_Fortran77 = 0x0007,
  DW_LANG_Fortran90 = 0x0008,
  DW_LANG_Pascal83 = 0x0009,
  DW_LANG_Modula2 = 0x000a,
  DW_LANG_Java = 0x000b,
  DW_LANG_C99 = 0x000c,
  DW_LANG_Ada95 = 0x000d,
  DW_LANG_Fortran95 = 0x000e,
  DW_LANG_PLI = 0x000f,
  DW_LANG_ObjC = 0x0010,
  DW_LANG_ObjC_plus_plus = 0x0011,
  DW_LANG_UPC = 0x0012,
  DW_LANG_D = 0x0013,
  DW_LANG_Python = 0x0014,
  DW_LANG_lo_user = 0x8000,
  DW_LANG_hi_user = 0xffff,


  DW_ID_case_sensitive = 0x00,
  DW_ID_up_case = 0x01,
  DW_ID_down_case = 0x02,
  DW_ID_case_insensitive = 0x03,


  DW_CC_normal = 0x01,
  DW_CC_program = 0x02,
  DW_CC_nocall = 0x03,
  DW_CC_lo_user = 0x40,
  DW_CC_hi_user = 0xff,


  DW_INL_not_inlined = 0x00,
  DW_INL_inlined = 0x01,
  DW_INL_declared_not_inlined = 0x02,
  DW_INL_declared_inlined = 0x03,


  DW_ORD_row_major = 0x00,
  DW_ORD_col_major = 0x01,


  DW_DSC_label = 0x00,
  DW_DSC_range = 0x01,


  DW_LNS_extended_op = 0x00,
  DW_LNS_copy = 0x01,
  DW_LNS_advance_pc = 0x02,
  DW_LNS_advance_line = 0x03,
  DW_LNS_set_file = 0x04,
  DW_LNS_set_column = 0x05,
  DW_LNS_negate_stmt = 0x06,
  DW_LNS_set_basic_block = 0x07,
  DW_LNS_const_add_pc = 0x08,
  DW_LNS_fixed_advance_pc = 0x09,
  DW_LNS_set_prologue_end = 0x0a,
  DW_LNS_set_epilogue_begin = 0x0b,
  DW_LNS_set_isa = 0x0c,


  DW_LNE_end_sequence = 0x01,
  DW_LNE_set_address = 0x02,
  DW_LNE_define_file = 0x03,
  DW_LNE_set_discriminator = 0x04,
  DW_LNE_lo_user = 0x80,
  DW_LNE_hi_user = 0xff,


  DW_MACINFO_define = 0x01,
  DW_MACINFO_undef = 0x02,
  DW_MACINFO_start_file = 0x03,
  DW_MACINFO_end_file = 0x04,
  DW_MACINFO_vendor_ext = 0xff,


  DW_CFA_extended = 0x00,
  DW_CFA_nop = 0x00,
  DW_CFA_advance_loc = 0x40,
  DW_CFA_offset = 0x80,
  DW_CFA_restore = 0xc0,
  DW_CFA_set_loc = 0x01,
  DW_CFA_advance_loc1 = 0x02,
  DW_CFA_advance_loc2 = 0x03,
  DW_CFA_advance_loc4 = 0x04,
  DW_CFA_offset_extended = 0x05,
  DW_CFA_restore_extended = 0x06,
  DW_CFA_undefined = 0x07,
  DW_CFA_same_value = 0x08,
  DW_CFA_register = 0x09,
  DW_CFA_remember_state = 0x0a,
  DW_CFA_restore_state = 0x0b,
  DW_CFA_def_cfa = 0x0c,
  DW_CFA_def_cfa_register = 0x0d,
  DW_CFA_def_cfa_offset = 0x0e,
  DW_CFA_def_cfa_expression = 0x0f,
  DW_CFA_expression = 0x10,
  DW_CFA_offset_extended_sf = 0x11,
  DW_CFA_def_cfa_sf = 0x12,
  DW_CFA_def_cfa_offset_sf = 0x13,
  DW_CFA_val_offset = 0x14,
  DW_CFA_val_offset_sf = 0x15,
  DW_CFA_val_expression = 0x16,
  DW_CFA_MIPS_advance_loc8 = 0x1d,
  DW_CFA_GNU_window_save = 0x2d,
  DW_CFA_GNU_args_size = 0x2e,
  DW_CFA_lo_user = 0x1c,
  DW_CFA_hi_user = 0x3f,

  DW_EH_PE_absptr = 0x00,
  DW_EH_PE_omit = 0xff,
  DW_EH_PE_uleb128 = 0x01,
  DW_EH_PE_udata2 = 0x02,
  DW_EH_PE_udata4 = 0x03,
  DW_EH_PE_udata8 = 0x04,
  DW_EH_PE_sleb128 = 0x09,
  DW_EH_PE_sdata2 = 0x0A,
  DW_EH_PE_sdata4 = 0x0B,
  DW_EH_PE_sdata8 = 0x0C,
  DW_EH_PE_signed = 0x08,
  DW_EH_PE_pcrel = 0x10,
  DW_EH_PE_textrel = 0x20,
  DW_EH_PE_datarel = 0x30,
  DW_EH_PE_funcrel = 0x40,
  DW_EH_PE_aligned = 0x50,
  DW_EH_PE_indirect = 0x80,


  DW_APPLE_PROPERTY_readonly = 0x01,
  DW_APPLE_PROPERTY_readwrite = 0x02,
  DW_APPLE_PROPERTY_assign = 0x04,
  DW_APPLE_PROPERTY_retain = 0x08,
  DW_APPLE_PROPERTY_copy = 0x10,
  DW_APPLE_PROPERTY_nonatomic = 0x20
};



const char *TagString(unsigned Tag);



const char *ChildrenString(unsigned Children);



const char *AttributeString(unsigned Attribute);



const char *FormEncodingString(unsigned Encoding);



const char *OperationEncodingString(unsigned Encoding);



const char *AttributeEncodingString(unsigned Encoding);



const char *DecimalSignString(unsigned Sign);



const char *EndianityString(unsigned Endian);



const char *AccessibilityString(unsigned Access);



const char *VisibilityString(unsigned Visibility);



const char *VirtualityString(unsigned Virtuality);



const char *LanguageString(unsigned Language);



const char *CaseString(unsigned Case);



const char *ConventionString(unsigned Convention);



const char *InlineCodeString(unsigned Code);



const char *ArrayOrderString(unsigned Order);



const char *DiscriminantString(unsigned Discriminant);



const char *LNStandardString(unsigned Standard);



const char *LNExtendedString(unsigned Encoding);



const char *MacinfoString(unsigned Encoding);



const char *CallFrameString(unsigned Encoding);
}

}


namespace llvm {
  class MCContext;
  class MCExpr;
  class MCSection;
  class MCSectionData;
  class MCStreamer;
  class MCSymbol;
  class MCObjectStreamer;
  class raw_ostream;






  class MCDwarfFile {


    StringRef Name;


    unsigned DirIndex;

  private:
    friend class MCContext;
    MCDwarfFile(StringRef name, unsigned dirIndex)
      : Name(name), DirIndex(dirIndex) {}

    MCDwarfFile(const MCDwarfFile&);
    void operator=(const MCDwarfFile&);
  public:

    StringRef getName() const { return Name; }


    unsigned getDirIndex() const { return DirIndex; }



    void print(raw_ostream &OS) const;


    void dump() const;
  };

  inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfFile){
    DwarfFile.print(OS);
    return OS;
  }



  class MCDwarfLoc {

    unsigned FileNum;

    unsigned Line;

    unsigned Column;

    unsigned Flags;

    unsigned Isa;

    unsigned Discriminator;
  private:
    friend class MCContext;
    friend class MCLineEntry;
    MCDwarfLoc(unsigned fileNum, unsigned line, unsigned column, unsigned flags,
               unsigned isa, unsigned discriminator)
      : FileNum(fileNum), Line(line), Column(column), Flags(flags), Isa(isa),
        Discriminator(discriminator) {}




  public:

    unsigned getFileNum() const { return FileNum; }


    unsigned getLine() const { return Line; }


    unsigned getColumn() const { return Column; }


    unsigned getFlags() const { return Flags; }


    unsigned getIsa() const { return Isa; }


    unsigned getDiscriminator() const { return Discriminator; }


    void setFileNum(unsigned fileNum) { FileNum = fileNum; }


    void setLine(unsigned line) { Line = line; }


    void setColumn(unsigned column) { Column = column; }


    void setFlags(unsigned flags) { Flags = flags; }


    void setIsa(unsigned isa) { Isa = isa; }


    void setDiscriminator(unsigned discriminator) {
      Discriminator = discriminator;
    }
  };






  class MCLineEntry : public MCDwarfLoc {
    MCSymbol *Label;

  private:



  public:

    MCLineEntry(MCSymbol *label, const MCDwarfLoc loc) : MCDwarfLoc(loc),
                Label(label) {}

    MCSymbol *getLabel() const { return Label; }




    static void Make(MCStreamer *MCOS, const MCSection *Section);
  };





  class MCLineSection {

  private:
    MCLineSection(const MCLineSection&);
    void operator=(const MCLineSection&);

  public:


    MCLineSection() {}


    void addLineEntry(const MCLineEntry &LineEntry) {
      MCLineEntries.push_back(LineEntry);
    }

    typedef std::vector<MCLineEntry> MCLineEntryCollection;
    typedef MCLineEntryCollection::iterator iterator;
    typedef MCLineEntryCollection::const_iterator const_iterator;

  private:
    MCLineEntryCollection MCLineEntries;

  public:
    const MCLineEntryCollection *getMCLineEntries() const {
      return &MCLineEntries;
    }
  };

  class MCDwarfFileTable {
  public:



    static void Emit(MCStreamer *MCOS);
  };

  class MCDwarfLineAddr {
  public:

    static void Encode(int64_t LineDelta, uint64_t AddrDelta, raw_ostream &OS);


    static void Emit(MCStreamer *MCOS,
                     int64_t LineDelta,uint64_t AddrDelta);


    static void Write(MCObjectWriter *OW,
                      int64_t LineDelta, uint64_t AddrDelta);
  };

  class MCCFIInstruction {
  public:
    enum OpType { SameValue, Remember, Restore, Move, RelMove };
  private:
    OpType Operation;
    MCSymbol *Label;

    MachineLocation Destination;
    MachineLocation Source;
  public:
    MCCFIInstruction(OpType Op, MCSymbol *L)
      : Operation(Op), Label(L) {
      ((Op == Remember || Op == Restore) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCDwarf.h", 242, "Op == Remember || Op == Restore"));
    }
    MCCFIInstruction(OpType Op, MCSymbol *L, unsigned Register)
      : Operation(Op), Label(L), Destination(Register) {
      ((Op == SameValue) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCDwarf.h", 246, "Op == SameValue"));
    }
    MCCFIInstruction(MCSymbol *L, const MachineLocation &D,
                     const MachineLocation &S)
      : Operation(Move), Label(L), Destination(D), Source(S) {
    }
    MCCFIInstruction(OpType Op, MCSymbol *L, const MachineLocation &D,
                     const MachineLocation &S)
      : Operation(Op), Label(L), Destination(D), Source(S) {
      ((Op == RelMove) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/MC/MCDwarf.h", 255, "Op == RelMove"));
    }
    OpType getOperation() const { return Operation; }
    MCSymbol *getLabel() const { return Label; }
    const MachineLocation &getDestination() const { return Destination; }
    const MachineLocation &getSource() const { return Source; }
  };

  struct MCDwarfFrameInfo {
    MCDwarfFrameInfo() : Begin(0), End(0), Personality(0), Lsda(0),
                         Function(0), Instructions(), PersonalityEncoding(),
                         LsdaEncoding(0), CompactUnwindEncoding(0) {}
    MCSymbol *Begin;
    MCSymbol *End;
    const MCSymbol *Personality;
    const MCSymbol *Lsda;
    const MCSymbol *Function;
    std::vector<MCCFIInstruction> Instructions;
    unsigned PersonalityEncoding;
    unsigned LsdaEncoding;
    uint32_t CompactUnwindEncoding;
  };

  class MCDwarfFrameEmitter {
  public:



    static void Emit(MCStreamer &streamer, bool usingCFI,
                     bool isEH);
    static void EmitAdvanceLoc(MCStreamer &Streamer, uint64_t AddrDelta);
    static void EncodeAdvanceLoc(uint64_t AddrDelta, raw_ostream &OS);
  };
}

namespace llvm {

template <typename T>
struct AlignmentCalcImpl {
  char x;
  T t;
private:
  AlignmentCalcImpl() {}
};
template <typename T>
struct AlignOf {
  enum { Alignment =
         static_cast<unsigned int>(sizeof(AlignmentCalcImpl<T>) - sizeof(T)) };

  enum { Alignment_GreaterEqual_2Bytes = Alignment >= 2 ? 1 : 0 };
  enum { Alignment_GreaterEqual_4Bytes = Alignment >= 4 ? 1 : 0 };
  enum { Alignment_GreaterEqual_8Bytes = Alignment >= 8 ? 1 : 0 };
  enum { Alignment_GreaterEqual_16Bytes = Alignment >= 16 ? 1 : 0 };

  enum { Alignment_LessEqual_2Bytes = Alignment <= 2 ? 1 : 0 };
  enum { Alignment_LessEqual_4Bytes = Alignment <= 4 ? 1 : 0 };
  enum { Alignment_LessEqual_8Bytes = Alignment <= 8 ? 1 : 0 };
  enum { Alignment_LessEqual_16Bytes = Alignment <= 16 ? 1 : 0 };

};





template <typename T>
static inline unsigned alignOf() { return AlignOf<T>::Alignment; }

}







namespace llvm {
template <typename T> struct ReferenceAdder { typedef T& result; };
template <typename T> struct ReferenceAdder<T&> { typedef T result; };

class MallocAllocator {
public:
  MallocAllocator() {}
  ~MallocAllocator() {}

  void Reset() {}

  void *Allocate(size_t Size, size_t ) { return malloc(Size); }

  template <typename T>
  T *Allocate() { return static_cast<T*>(malloc(sizeof(T))); }

  template <typename T>
  T *Allocate(size_t Num) {
    return static_cast<T*>(malloc(sizeof(T)*Num));
  }

  void Deallocate(const void *Ptr) { free(const_cast<void*>(Ptr)); }

  void PrintStats() const {}
};



class MemSlab {
public:
  size_t Size;
  MemSlab *NextPtr;
};






class SlabAllocator {
public:
  virtual ~SlabAllocator();
  virtual MemSlab *Allocate(size_t Size) = 0;
  virtual void Deallocate(MemSlab *Slab) = 0;
};




class MallocSlabAllocator : public SlabAllocator {


  MallocAllocator Allocator;

public:
  MallocSlabAllocator() : Allocator() { }
  virtual ~MallocSlabAllocator();
  virtual MemSlab *Allocate(size_t Size);
  virtual void Deallocate(MemSlab *Slab);
};





class BumpPtrAllocator {
  BumpPtrAllocator(const BumpPtrAllocator &);
  void operator=(const BumpPtrAllocator &);



  size_t SlabSize;



  size_t SizeThreshold;




  SlabAllocator &Allocator;



  MemSlab *CurSlab;



  char *CurPtr;



  char *End;



  size_t BytesAllocated;




  static char *AlignPtr(char *Ptr, size_t Alignment);



  void StartNewSlab();



  void DeallocateSlabs(MemSlab *Slab);

  static MallocSlabAllocator DefaultSlabAllocator;

  template<typename T> friend class SpecificBumpPtrAllocator;
public:
  BumpPtrAllocator(size_t size = 4096, size_t threshold = 4096,
                   SlabAllocator &allocator = DefaultSlabAllocator);
  ~BumpPtrAllocator();



  void Reset();



  void *Allocate(size_t Size, size_t Alignment);



  template <typename T>
  T *Allocate() {
    return static_cast<T*>(Allocate(sizeof(T),AlignOf<T>::Alignment));
  }



  template <typename T>
  T *Allocate(size_t Num) {
    return static_cast<T*>(Allocate(Num * sizeof(T), AlignOf<T>::Alignment));
  }



  template <typename T>
  T *Allocate(size_t Num, size_t Alignment) {

    size_t EltSize = (sizeof(T)+Alignment-1)&(-Alignment);
    return static_cast<T*>(Allocate(Num * EltSize, Alignment));
  }

  void Deallocate(const void * ) {}

  unsigned GetNumSlabs() const;

  void PrintStats() const;


  size_t getTotalMemory() const;
};




template <typename T>
class SpecificBumpPtrAllocator {
  BumpPtrAllocator Allocator;
public:
  SpecificBumpPtrAllocator(size_t size = 4096, size_t threshold = 4096,
              SlabAllocator &allocator = BumpPtrAllocator::DefaultSlabAllocator)
    : Allocator(size, threshold, allocator) {}

  ~SpecificBumpPtrAllocator() {
    DestroyAll();
  }




  void DestroyAll() {
    MemSlab *Slab = Allocator.CurSlab;
    while (Slab) {
      char *End = Slab == Allocator.CurSlab ? Allocator.CurPtr :
                                              (char *)Slab + Slab->Size;
      for (char *Ptr = (char*)(Slab+1); Ptr < End; Ptr += sizeof(T)) {
        Ptr = Allocator.AlignPtr(Ptr, alignOf<T>());
        if (Ptr + sizeof(T) <= End)
          reinterpret_cast<T*>(Ptr)->~T();
      }
      Slab = Slab->NextPtr;
    }
    Allocator.Reset();
  }


  T *Allocate(size_t num = 1) {
    return Allocator.Allocate<T>(num);
  }
};

}

inline void *operator new(size_t Size, llvm::BumpPtrAllocator &Allocator) {
  struct S {
    char c;
    union {
      double D;
      long double LD;
      long long L;
      void *P;
    } x;
  };
  return Allocator.Allocate(Size, std::min((size_t)llvm::NextPowerOf2(Size),
                                           __builtin_offsetof(S, x)));
}

inline void operator delete(void *, llvm::BumpPtrAllocator &) {}


namespace llvm {
  template<typename ValueT>
  class StringMapConstIterator;
  template<typename ValueT>
  class StringMapIterator;
  template<typename ValueTy>
  class StringMapEntry;




template<typename ValueTy>
class StringMapEntryInitializer {
public:
  template <typename InitTy>
  static void Initialize(StringMapEntry<ValueTy> &T, InitTy InitVal) {
    T.second = InitVal;
  }
};



class StringMapEntryBase {
  unsigned StrLen;
public:
  explicit StringMapEntryBase(unsigned Len) : StrLen(Len) {}

  unsigned getKeyLength() const { return StrLen; }
};



class StringMapImpl {
public:


  struct ItemBucket {


    unsigned FullHashValue;


    StringMapEntryBase *Item;
  };

protected:
  ItemBucket *TheTable;
  unsigned NumBuckets;
  unsigned NumItems;
  unsigned NumTombstones;
  unsigned ItemSize;
protected:
  explicit StringMapImpl(unsigned itemSize) : ItemSize(itemSize) {

    TheTable = 0;
    NumBuckets = 0;
    NumItems = 0;
    NumTombstones = 0;
  }
  StringMapImpl(unsigned InitSize, unsigned ItemSize);
  void RehashTable();






  unsigned LookupBucketFor(StringRef Key);




  int FindKey(StringRef Key) const;



  void RemoveKey(StringMapEntryBase *V);



  StringMapEntryBase *RemoveKey(StringRef Key);
private:
  void init(unsigned Size);
public:
  static StringMapEntryBase *getTombstoneVal() {
    return (StringMapEntryBase*)-1;
  }

  unsigned getNumBuckets() const { return NumBuckets; }
  unsigned getNumItems() const { return NumItems; }

  bool empty() const { return NumItems == 0; }
  unsigned size() const { return NumItems; }
};




template<typename ValueTy>
class StringMapEntry : public StringMapEntryBase {
public:
  ValueTy second;

  explicit StringMapEntry(unsigned strLen)
    : StringMapEntryBase(strLen), second() {}
  StringMapEntry(unsigned strLen, const ValueTy &V)
    : StringMapEntryBase(strLen), second(V) {}

  StringRef getKey() const {
    return StringRef(getKeyData(), getKeyLength());
  }

  const ValueTy &getValue() const { return second; }
  ValueTy &getValue() { return second; }

  void setValue(const ValueTy &V) { second = V; }




  const char *getKeyData() const {return reinterpret_cast<const char*>(this+1);}

  StringRef first() const { return StringRef(getKeyData(), getKeyLength()); }



  template<typename AllocatorTy, typename InitType>
  static StringMapEntry *Create(const char *KeyStart, const char *KeyEnd,
                                AllocatorTy &Allocator,
                                InitType InitVal) {
    unsigned KeyLength = static_cast<unsigned>(KeyEnd-KeyStart);





    unsigned AllocSize = static_cast<unsigned>(sizeof(StringMapEntry))+
      KeyLength+1;
    unsigned Alignment = alignOf<StringMapEntry>();

    StringMapEntry *NewItem =
      static_cast<StringMapEntry*>(Allocator.Allocate(AllocSize,Alignment));


    new (NewItem) StringMapEntry(KeyLength);


    char *StrBuffer = const_cast<char*>(NewItem->getKeyData());
    memcpy(StrBuffer, KeyStart, KeyLength);
    StrBuffer[KeyLength] = 0;


    StringMapEntryInitializer<ValueTy>::Initialize(*NewItem, InitVal);
    return NewItem;
  }

  template<typename AllocatorTy>
  static StringMapEntry *Create(const char *KeyStart, const char *KeyEnd,
                                AllocatorTy &Allocator) {
    return Create(KeyStart, KeyEnd, Allocator, 0);
  }



  template<typename InitType>
  static StringMapEntry *Create(const char *KeyStart, const char *KeyEnd,
                                InitType InitVal) {
    MallocAllocator A;
    return Create(KeyStart, KeyEnd, A, InitVal);
  }

  static StringMapEntry *Create(const char *KeyStart, const char *KeyEnd) {
    return Create(KeyStart, KeyEnd, ValueTy());
  }



  static StringMapEntry &GetStringMapEntryFromValue(ValueTy &V) {
    StringMapEntry *EPtr = 0;
    char *Ptr = reinterpret_cast<char*>(&V) -
                  (reinterpret_cast<char*>(&EPtr->second) -
                   reinterpret_cast<char*>(EPtr));
    return *reinterpret_cast<StringMapEntry*>(Ptr);
  }
  static const StringMapEntry &GetStringMapEntryFromValue(const ValueTy &V) {
    return GetStringMapEntryFromValue(const_cast<ValueTy&>(V));
  }



  static StringMapEntry &GetStringMapEntryFromKeyData(const char *KeyData) {
    char *Ptr = const_cast<char*>(KeyData) - sizeof(StringMapEntry<ValueTy>);
    return *reinterpret_cast<StringMapEntry*>(Ptr);
  }




  template<typename AllocatorTy>
  void Destroy(AllocatorTy &Allocator) {

    this->~StringMapEntry();
    Allocator.Deallocate(this);
  }


  void Destroy() {
    MallocAllocator A;
    Destroy(A);
  }
};






template<typename ValueTy, typename AllocatorTy = MallocAllocator>
class StringMap : public StringMapImpl {
  AllocatorTy Allocator;
  typedef StringMapEntry<ValueTy> MapEntryTy;
public:
  StringMap() : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {}
  explicit StringMap(unsigned InitialSize)
    : StringMapImpl(InitialSize, static_cast<unsigned>(sizeof(MapEntryTy))) {}

  explicit StringMap(AllocatorTy A)
    : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))), Allocator(A) {}

  explicit StringMap(const StringMap &RHS)
    : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {
    ((RHS.empty() && "Copy ctor from non-empty stringmap not implemented yet!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringMap.h", 253, "RHS.empty() && \"Copy ctor from non-empty stringmap not implemented yet!\""));

    (void)RHS;
  }
  void operator=(const StringMap &RHS) {
    ((RHS.empty() && "assignment from non-empty stringmap not implemented yet!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringMap.h", 258, "RHS.empty() && \"assignment from non-empty stringmap not implemented yet!\""));

    (void)RHS;
    clear();
  }

  typedef typename ReferenceAdder<AllocatorTy>::result AllocatorRefTy;
  typedef typename ReferenceAdder<const AllocatorTy>::result AllocatorCRefTy;
  AllocatorRefTy getAllocator() { return Allocator; }
  AllocatorCRefTy getAllocator() const { return Allocator; }

  typedef const char* key_type;
  typedef ValueTy mapped_type;
  typedef StringMapEntry<ValueTy> value_type;
  typedef size_t size_type;

  typedef StringMapConstIterator<ValueTy> const_iterator;
  typedef StringMapIterator<ValueTy> iterator;

  iterator begin() {
    return iterator(TheTable, NumBuckets == 0);
  }
  iterator end() {
    return iterator(TheTable+NumBuckets, true);
  }
  const_iterator begin() const {
    return const_iterator(TheTable, NumBuckets == 0);
  }
  const_iterator end() const {
    return const_iterator(TheTable+NumBuckets, true);
  }

  iterator find(StringRef Key) {
    int Bucket = FindKey(Key);
    if (Bucket == -1) return end();
    return iterator(TheTable+Bucket);
  }

  const_iterator find(StringRef Key) const {
    int Bucket = FindKey(Key);
    if (Bucket == -1) return end();
    return const_iterator(TheTable+Bucket);
  }



  ValueTy lookup(StringRef Key) const {
    const_iterator it = find(Key);
    if (it != end())
      return it->second;
    return ValueTy();
  }

  ValueTy &operator[](StringRef Key) {
    return GetOrCreateValue(Key).getValue();
  }

  size_type count(StringRef Key) const {
    return find(Key) == end() ? 0 : 1;
  }




  bool insert(MapEntryTy *KeyValue) {
    unsigned BucketNo = LookupBucketFor(KeyValue->getKey());
    ItemBucket &Bucket = TheTable[BucketNo];
    if (Bucket.Item && Bucket.Item != getTombstoneVal())
      return false;

    if (Bucket.Item == getTombstoneVal())
      --NumTombstones;
    Bucket.Item = KeyValue;
    ++NumItems;
    ((NumItems + NumTombstones <= NumBuckets) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringMap.h", 331, "NumItems + NumTombstones <= NumBuckets"));

    RehashTable();
    return true;
  }


  void clear() {
    if (empty()) return;



    for (ItemBucket *I = TheTable, *E = TheTable+NumBuckets; I != E; ++I) {
      if (I->Item && I->Item != getTombstoneVal()) {
        static_cast<MapEntryTy*>(I->Item)->Destroy(Allocator);
        I->Item = 0;
      }
    }

    NumItems = 0;
    NumTombstones = 0;
  }




  template <typename InitTy>
  MapEntryTy &GetOrCreateValue(StringRef Key, InitTy Val) {
    unsigned BucketNo = LookupBucketFor(Key);
    ItemBucket &Bucket = TheTable[BucketNo];
    if (Bucket.Item && Bucket.Item != getTombstoneVal())
      return *static_cast<MapEntryTy*>(Bucket.Item);

    MapEntryTy *NewItem =
      MapEntryTy::Create(Key.begin(), Key.end(), Allocator, Val);

    if (Bucket.Item == getTombstoneVal())
      --NumTombstones;
    ++NumItems;
    ((NumItems + NumTombstones <= NumBuckets) ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/ADT/StringMap.h", 370, "NumItems + NumTombstones <= NumBuckets"));



    Bucket.Item = NewItem;

    RehashTable();
    return *NewItem;
  }

  MapEntryTy &GetOrCreateValue(StringRef Key) {
    return GetOrCreateValue(Key, ValueTy());
  }



  void remove(MapEntryTy *KeyValue) {
    RemoveKey(KeyValue);
  }

  void erase(iterator I) {
    MapEntryTy &V = *I;
    remove(&V);
    V.Destroy(Allocator);
  }

  bool erase(StringRef Key) {
    iterator I = find(Key);
    if (I == end()) return false;
    erase(I);
    return true;
  }

  ~StringMap() {
    clear();
    free(TheTable);
  }
};


template<typename ValueTy>
class StringMapConstIterator {
protected:
  StringMapImpl::ItemBucket *Ptr;
public:
  typedef StringMapEntry<ValueTy> value_type;

  explicit StringMapConstIterator(StringMapImpl::ItemBucket *Bucket,
                                  bool NoAdvance = false)
  : Ptr(Bucket) {
    if (!NoAdvance) AdvancePastEmptyBuckets();
  }

  const value_type &operator*() const {
    return *static_cast<StringMapEntry<ValueTy>*>(Ptr->Item);
  }
  const value_type *operator->() const {
    return static_cast<StringMapEntry<ValueTy>*>(Ptr->Item);
  }

  bool operator==(const StringMapConstIterator &RHS) const {
    return Ptr == RHS.Ptr;
  }
  bool operator!=(const StringMapConstIterator &RHS) const {
    return Ptr != RHS.Ptr;
  }

  inline StringMapConstIterator& operator++() {
    ++Ptr;
    AdvancePastEmptyBuckets();
    return *this;
  }
  StringMapConstIterator operator++(int) {
    StringMapConstIterator tmp = *this; ++*this; return tmp;
  }

private:
  void AdvancePastEmptyBuckets() {
    while (Ptr->Item == 0 || Ptr->Item == StringMapImpl::getTombstoneVal())
      ++Ptr;
  }
};

template<typename ValueTy>
class StringMapIterator : public StringMapConstIterator<ValueTy> {
public:
  explicit StringMapIterator(StringMapImpl::ItemBucket *Bucket,
                             bool NoAdvance = false)
    : StringMapConstIterator<ValueTy>(Bucket, NoAdvance) {
  }
  StringMapEntry<ValueTy> &operator*() const {
    return *static_cast<StringMapEntry<ValueTy>*>(this->Ptr->Item);
  }
  StringMapEntry<ValueTy> *operator->() const {
    return static_cast<StringMapEntry<ValueTy>*>(this->Ptr->Item);
  }
};

}




namespace llvm {
  class MCAsmInfo;
  class MCExpr;
  class MCSection;
  class MCSymbol;
  class MCLabel;
  class MCDwarfFile;
  class MCDwarfLoc;
  class MCObjectFileInfo;
  class MCRegisterInfo;
  class MCLineSection;
  class StringRef;
  class Twine;
  class MCSectionMachO;
  class MCSectionELF;




  class MCContext {
    MCContext(const MCContext&);
    MCContext &operator=(const MCContext&);
  public:
    typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable;
  private:


    const MCAsmInfo &MAI;


    const MCRegisterInfo &MRI;


    const MCObjectFileInfo *MOFI;





    BumpPtrAllocator Allocator;


    SymbolTable Symbols;



    StringMap<bool, BumpPtrAllocator&> UsedNames;



    unsigned NextUniqueID;


    DenseMap<unsigned, MCLabel *> Instances;


    unsigned NextInstance(int64_t LocalLabelVal);


    unsigned GetInstance(int64_t LocalLabelVal);




    char *SecureLogFile;

    raw_ostream *SecureLog;



    bool SecureLogUsed;


    std::vector<MCDwarfFile *> MCDwarfFiles;
    std::vector<StringRef> MCDwarfDirs;


    MCDwarfLoc CurrentDwarfLoc;
    bool DwarfLocSeen;




    bool AllowTemporaryLabels;



    DenseMap<const MCSection *, MCLineSection *> MCLineSections;


    std::vector<const MCSection *> MCLineSectionOrder;

    void *MachOUniquingMap, *ELFUniquingMap, *COFFUniquingMap;

    MCSymbol *CreateSymbol(StringRef Name);

  public:
    explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
                       const MCObjectFileInfo *MOFI);
    ~MCContext();

    const MCAsmInfo &getAsmInfo() const { return MAI; }

    const MCRegisterInfo &getRegisterInfo() const { return MRI; }

    const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }

    void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; }






    MCSymbol *CreateTempSymbol();



    MCSymbol *CreateDirectionalLocalSymbol(int64_t LocalLabelVal);



    MCSymbol *GetDirectionalLocalSymbol(int64_t LocalLabelVal, int bORf);






    MCSymbol *GetOrCreateSymbol(StringRef Name);
    MCSymbol *GetOrCreateSymbol(const Twine &Name);


    MCSymbol *LookupSymbol(StringRef Name) const;





    const SymbolTable &getSymbols() const {
      return Symbols;
    }
    const MCSectionMachO *getMachOSection(StringRef Segment,
                                          StringRef Section,
                                          unsigned TypeAndAttributes,
                                          unsigned Reserved2,
                                          SectionKind K);
    const MCSectionMachO *getMachOSection(StringRef Segment,
                                          StringRef Section,
                                          unsigned TypeAndAttributes,
                                          SectionKind K) {
      return getMachOSection(Segment, Section, TypeAndAttributes, 0, K);
    }

    const MCSectionELF *getELFSection(StringRef Section, unsigned Type,
                                      unsigned Flags, SectionKind Kind);

    const MCSectionELF *getELFSection(StringRef Section, unsigned Type,
                                      unsigned Flags, SectionKind Kind,
                                      unsigned EntrySize, StringRef Group);

    const MCSectionELF *CreateELFGroupSection();

    const MCSection *getCOFFSection(StringRef Section, unsigned Characteristics,
                                    int Selection, SectionKind Kind);

    const MCSection *getCOFFSection(StringRef Section, unsigned Characteristics,
                                    SectionKind Kind) {
      return getCOFFSection (Section, Characteristics, 0, Kind);
    }
    unsigned GetDwarfFile(StringRef FileName, unsigned FileNumber);

    bool isValidDwarfFileNumber(unsigned FileNumber);

    bool hasDwarfFiles() const {
      return !MCDwarfFiles.empty();
    }

    const std::vector<MCDwarfFile *> &getMCDwarfFiles() {
      return MCDwarfFiles;
    }
    const std::vector<StringRef> &getMCDwarfDirs() {
      return MCDwarfDirs;
    }

    const DenseMap<const MCSection *, MCLineSection *>
    &getMCLineSections() const {
      return MCLineSections;
    }
    const std::vector<const MCSection *> &getMCLineSectionOrder() const {
      return MCLineSectionOrder;
    }
    void addMCLineSection(const MCSection *Sec, MCLineSection *Line) {
      MCLineSections[Sec] = Line;
      MCLineSectionOrder.push_back(Sec);
    }





    void setCurrentDwarfLoc(unsigned FileNum, unsigned Line, unsigned Column,
                            unsigned Flags, unsigned Isa,
                            unsigned Discriminator) {
      CurrentDwarfLoc.setFileNum(FileNum);
      CurrentDwarfLoc.setLine(Line);
      CurrentDwarfLoc.setColumn(Column);
      CurrentDwarfLoc.setFlags(Flags);
      CurrentDwarfLoc.setIsa(Isa);
      CurrentDwarfLoc.setDiscriminator(Discriminator);
      DwarfLocSeen = true;
    }
    void ClearDwarfLocSeen() { DwarfLocSeen = false; }

    bool getDwarfLocSeen() { return DwarfLocSeen; }
    const MCDwarfLoc &getCurrentDwarfLoc() { return CurrentDwarfLoc; }



    char *getSecureLogFile() { return SecureLogFile; }
    raw_ostream *getSecureLog() { return SecureLog; }
    bool getSecureLogUsed() { return SecureLogUsed; }
    void setSecureLog(raw_ostream *Value) {
      SecureLog = Value;
    }
    void setSecureLogUsed(bool Value) {
      SecureLogUsed = Value;
    }

    void *Allocate(unsigned Size, unsigned Align = 8) {
      return Allocator.Allocate(Size, Align);
    }
    void Deallocate(void *Ptr) {
    }
  };

}
inline void *operator new(size_t Bytes, llvm::MCContext &C,
                          size_t Alignment = 16) throw () {
  return C.Allocate(Bytes, Alignment);
}






inline void operator delete(void *Ptr, llvm::MCContext &C, size_t)
              throw () {
  C.Deallocate(Ptr);
}
inline void *operator new[](size_t Bytes, llvm::MCContext& C,
                            size_t Alignment = 16) throw () {
  return C.Allocate(Bytes, Alignment);
}







inline void operator delete[](void *Ptr, llvm::MCContext &C) throw () {
  C.Deallocate(Ptr);
}
typedef void *LLVMDisasmContextRef;
typedef int (*LLVMOpInfoCallback)(void *DisInfo, uint64_t PC,
                                  uint64_t Offset, uint64_t Size,
                                  int TagType, void *TagBuf);
struct LLVMOpInfoSymbol1 {
  uint64_t Present;
  const char *Name;
  uint64_t Value;
};

struct LLVMOpInfo1 {
  struct LLVMOpInfoSymbol1 AddSymbol;
  struct LLVMOpInfoSymbol1 SubtractSymbol;
  uint64_t Value;
  uint64_t VariantKind;
};
typedef const char *(*LLVMSymbolLookupCallback)(void *DisInfo,
                                                uint64_t ReferenceValue,
      uint64_t *ReferenceType,
      uint64_t ReferencePC,
      const char **ReferenceName);
extern "C" {
LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo,
                                      int TagType, LLVMOpInfoCallback GetOpInfo,
                                      LLVMSymbolLookupCallback SymbolLookUp);




void LLVMDisasmDispose(LLVMDisasmContextRef DC);
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DC, uint8_t *Bytes,
                             uint64_t BytesSize, uint64_t PC,
                             char *OutString, size_t OutStringSize);


}

namespace llvm {

class MCInst;
class MCSubtargetInfo;
class MemoryObject;
class raw_ostream;
class MCContext;

struct EDInstInfo;



class MCDisassembler {
public:
  enum DecodeStatus {
    Fail = 0,
    SoftFail = 1,
    Success = 3
  };


  MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0),
                                               DisInfo(0), Ctx(0),
                                               STI(STI), CommentStream(0) {}

  virtual ~MCDisassembler();
  virtual DecodeStatus getInstruction(MCInst& instr,
                                       uint64_t& size,
                                       const MemoryObject &region,
                                       uint64_t address,
                                       raw_ostream &vStream,
                                       raw_ostream &cStream) const = 0;







  virtual EDInstInfo *getEDInfo() const { return (EDInstInfo*)0; }

private:




  LLVMOpInfoCallback GetOpInfo;

  LLVMSymbolLookupCallback SymbolLookUp;

  void *DisInfo;


  MCContext *Ctx;
protected:

  const MCSubtargetInfo &STI;

public:
  void setupForSymbolicDisassembly(LLVMOpInfoCallback getOpInfo,
                                   LLVMSymbolLookupCallback symbolLookUp,
                                   void *disInfo,
                                   MCContext *ctx) {
    GetOpInfo = getOpInfo;
    SymbolLookUp = symbolLookUp;
    DisInfo = disInfo;
    Ctx = ctx;
  }
  LLVMOpInfoCallback getLLVMOpInfoCallback() const { return GetOpInfo; }
  LLVMSymbolLookupCallback getLLVMSymbolLookupCallback() const {
    return SymbolLookUp;
  }
  void *getDisInfoBlock() const { return DisInfo; }
  MCContext *getMCContext() const { return Ctx; }



  mutable raw_ostream *CommentStream;
};

}
namespace llvm {

class raw_ostream;
extern bool DebugFlag;





bool isCurrentDebugType(const char *Type);





void SetCurrentDebugType(const char *Type);
extern bool EnableDebugBuffering;




raw_ostream &dbgs();
}
namespace llvm {






class MemoryObject {
public:

  virtual ~MemoryObject();




  virtual uint64_t getBase() const = 0;






  virtual uint64_t getExtent() const = 0;







  virtual int readByte(uint64_t address, uint8_t* ptr) const = 0;
  virtual int readBytes(uint64_t address,
                        uint64_t size,
                        uint8_t* buf,
                        uint64_t* copied) const;
};

}



namespace llvm {
  class AsmPrinter;
  class Module;
  class MCAssembler;
  class MCAsmBackend;
  class MCAsmInfo;
  class MCAsmParser;
  class MCCodeEmitter;
  class MCCodeGenInfo;
  class MCContext;
  class MCDisassembler;
  class MCInstrAnalysis;
  class MCInstPrinter;
  class MCInstrInfo;
  class MCRegisterInfo;
  class MCStreamer;
  class MCSubtargetInfo;
  class MCTargetAsmLexer;
  class MCTargetAsmParser;
  class TargetMachine;
  class raw_ostream;
  class formatted_raw_ostream;

  MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
                                bool isVerboseAsm,
                                bool useLoc, bool useCFI,
                                MCInstPrinter *InstPrint,
                                MCCodeEmitter *CE,
                                MCAsmBackend *TAB,
                                bool ShowInst);
  class Target {
  public:
    friend struct TargetRegistry;

    typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);

    typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
                                            StringRef TT);
    typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
                                                    Reloc::Model RM,
                                                    CodeModel::Model CM);
    typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
    typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*Info);
    typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
    typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
                                                        StringRef CPU,
                                                        StringRef Features);
    typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
                                                  StringRef TT,
                                                  StringRef CPU,
                                                  StringRef Features,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM);
    typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
                                            MCStreamer &Streamer);
    typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT);
    typedef MCTargetAsmLexer *(*MCAsmLexerCtorTy)(const Target &T,
                                                  const MCRegisterInfo &MRI,
                                                  const MCAsmInfo &MAI);
    typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
                                                    MCAsmParser &P);
    typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
                                                    const MCSubtargetInfo &STI);
    typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCSubtargetInfo &STI);
    typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
                                                  const MCSubtargetInfo &STI,
                                                  MCContext &Ctx);
    typedef MCStreamer *(*MCObjectStreamerCtorTy)(const Target &T,
                                                  StringRef TT,
                                                  MCContext &Ctx,
                                                  MCAsmBackend &TAB,
                                                  raw_ostream &_OS,
                                                  MCCodeEmitter *_Emitter,
                                                  bool RelaxAll,
                                                  bool NoExecStack);
    typedef MCStreamer *(*AsmStreamerCtorTy)(MCContext &Ctx,
                                             formatted_raw_ostream &OS,
                                             bool isVerboseAsm,
                                             bool useLoc,
                                             bool useCFI,
                                             MCInstPrinter *InstPrint,
                                             MCCodeEmitter *CE,
                                             MCAsmBackend *TAB,
                                             bool ShowInst);

  private:


    Target *Next;



    TripleMatchQualityFnTy TripleMatchQualityFn;


    const char *Name;


    const char *ShortDesc;


    bool HasJIT;



    MCAsmInfoCtorFnTy MCAsmInfoCtorFn;



    MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;



    MCInstrInfoCtorFnTy MCInstrInfoCtorFn;



    MCInstrAnalysisCtorFnTy MCInstrAnalysisCtorFn;



    MCRegInfoCtorFnTy MCRegInfoCtorFn;



    MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;



    TargetMachineCtorTy TargetMachineCtorFn;



    MCAsmBackendCtorTy MCAsmBackendCtorFn;



    MCAsmLexerCtorTy MCAsmLexerCtorFn;



    MCAsmParserCtorTy MCAsmParserCtorFn;



    AsmPrinterCtorTy AsmPrinterCtorFn;



    MCDisassemblerCtorTy MCDisassemblerCtorFn;



    MCInstPrinterCtorTy MCInstPrinterCtorFn;



    MCCodeEmitterCtorTy MCCodeEmitterCtorFn;



    MCObjectStreamerCtorTy MCObjectStreamerCtorFn;



    AsmStreamerCtorTy AsmStreamerCtorFn;

  public:
    Target() : AsmStreamerCtorFn(llvm::createAsmStreamer) {}





    const Target *getNext() const { return Next; }


    const char *getName() const { return Name; }


    const char *getShortDescription() const { return ShortDesc; }






    bool hasJIT() const { return HasJIT; }


    bool hasTargetMachine() const { return TargetMachineCtorFn != 0; }


    bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != 0; }


    bool hasMCAsmLexer() const { return MCAsmLexerCtorFn != 0; }


    bool hasMCAsmParser() const { return MCAsmParserCtorFn != 0; }


    bool hasAsmPrinter() const { return AsmPrinterCtorFn != 0; }


    bool hasMCDisassembler() const { return MCDisassemblerCtorFn != 0; }


    bool hasMCInstPrinter() const { return MCInstPrinterCtorFn != 0; }


    bool hasMCCodeEmitter() const { return MCCodeEmitterCtorFn != 0; }


    bool hasMCObjectStreamer() const { return MCObjectStreamerCtorFn != 0; }


    bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; }
    MCAsmInfo *createMCAsmInfo(StringRef Triple) const {
      if (!MCAsmInfoCtorFn)
        return 0;
      return MCAsmInfoCtorFn(*this, Triple);
    }



    MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
                                       CodeModel::Model CM) const {
      if (!MCCodeGenInfoCtorFn)
        return 0;
      return MCCodeGenInfoCtorFn(Triple, RM, CM);
    }



    MCInstrInfo *createMCInstrInfo() const {
      if (!MCInstrInfoCtorFn)
        return 0;
      return MCInstrInfoCtorFn();
    }



    MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const {
      if (!MCInstrAnalysisCtorFn)
        return 0;
      return MCInstrAnalysisCtorFn(Info);
    }



    MCRegisterInfo *createMCRegInfo(StringRef Triple) const {
      if (!MCRegInfoCtorFn)
        return 0;
      return MCRegInfoCtorFn(Triple);
    }
    MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
                                           StringRef Features) const {
      if (!MCSubtargetInfoCtorFn)
        return 0;
      return MCSubtargetInfoCtorFn(Triple, CPU, Features);
    }
    TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
                               StringRef Features,
                               Reloc::Model RM = Reloc::Default,
                               CodeModel::Model CM = CodeModel::Default) const {
      if (!TargetMachineCtorFn)
        return 0;
      return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM);
    }





    MCAsmBackend *createMCAsmBackend(StringRef Triple) const {
      if (!MCAsmBackendCtorFn)
        return 0;
      return MCAsmBackendCtorFn(*this, Triple);
    }



    MCTargetAsmLexer *createMCAsmLexer(const MCRegisterInfo &MRI,
                                       const MCAsmInfo &MAI) const {
      if (!MCAsmLexerCtorFn)
        return 0;
      return MCAsmLexerCtorFn(*this, MRI, MAI);
    }





    MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,
                                         MCAsmParser &Parser) const {
      if (!MCAsmParserCtorFn)
        return 0;
      return MCAsmParserCtorFn(STI, Parser);
    }



    AsmPrinter *createAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) const{
      if (!AsmPrinterCtorFn)
        return 0;
      return AsmPrinterCtorFn(TM, Streamer);
    }

    MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const {
      if (!MCDisassemblerCtorFn)
        return 0;
      return MCDisassemblerCtorFn(*this, STI);
    }

    MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
                                       const MCAsmInfo &MAI,
                                       const MCSubtargetInfo &STI) const {
      if (!MCInstPrinterCtorFn)
        return 0;
      return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, STI);
    }



    MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
                                       const MCSubtargetInfo &STI,
                                       MCContext &Ctx) const {
      if (!MCCodeEmitterCtorFn)
        return 0;
      return MCCodeEmitterCtorFn(II, STI, Ctx);
    }
    MCStreamer *createMCObjectStreamer(StringRef TT, MCContext &Ctx,
                                       MCAsmBackend &TAB,
                                       raw_ostream &_OS,
                                       MCCodeEmitter *_Emitter,
                                       bool RelaxAll,
                                       bool NoExecStack) const {
      if (!MCObjectStreamerCtorFn)
        return 0;
      return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter,
                                    RelaxAll, NoExecStack);
    }


    MCStreamer *createAsmStreamer(MCContext &Ctx,
                                  formatted_raw_ostream &OS,
                                  bool isVerboseAsm,
                                  bool useLoc,
                                  bool useCFI,
                                  MCInstPrinter *InstPrint,
                                  MCCodeEmitter *CE,
                                  MCAsmBackend *TAB,
                                  bool ShowInst) const {

      return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI,
                               InstPrint, CE, TAB, ShowInst);
    }


  };


  struct TargetRegistry {
    class iterator {
      const Target *Current;
      explicit iterator(Target *T) : Current(T) {}
      friend struct TargetRegistry;
    public:
      iterator(const iterator &I) : Current(I.Current) {}
      iterator() : Current(0) {}

      bool operator==(const iterator &x) const {
        return Current == x.Current;
      }
      bool operator!=(const iterator &x) const {
        return !operator==(x);
      }


      iterator &operator++() {
        ((Current && "Cannot increment end iterator!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Support/TargetRegistry.h", 460, "Current && \"Cannot increment end iterator!\""));
        Current = Current->getNext();
        return *this;
      }
      iterator operator++(int) {
        iterator tmp = *this;
        ++*this;
        return tmp;
      }

      const Target &operator*() const {
        ((Current && "Cannot dereference end iterator!") ? (void)0 : __assert(__func__, "/home/peter/fbp4/hammer/lib/clang/libllvmarmdisassembler/../../../contrib/llvm/include/llvm/Support/TargetRegistry.h", 471, "Current && \"Cannot dereference end iterator!\""));
        return *Current;
      }

      const Target *operator->() const {
        return &operator*();
      }
    };



    static void printRegisteredTargetsForVersion();




    static iterator begin();

    static iterator end() { return iterator(); }






    static const Target *lookupTarget(const std::string &Triple,
                                      std::string &Error);






    static const Target *getClosestTargetForJIT(std::string &Error);
    static void RegisterTarget(Target &T,
                               const char *Name,
                               const char *ShortDesc,
                               Target::TripleMatchQualityFnTy TQualityFn,
                               bool HasJIT = false);
    static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {

      if (!T.MCAsmInfoCtorFn)
        T.MCAsmInfoCtorFn = Fn;
    }
    static void RegisterMCCodeGenInfo(Target &T,
                                     Target::MCCodeGenInfoCtorFnTy Fn) {

      if (!T.MCCodeGenInfoCtorFn)
        T.MCCodeGenInfoCtorFn = Fn;
    }
    static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) {

      if (!T.MCInstrInfoCtorFn)
        T.MCInstrInfoCtorFn = Fn;
    }



    static void RegisterMCInstrAnalysis(Target &T,
                                        Target::MCInstrAnalysisCtorFnTy Fn) {

      if (!T.MCInstrAnalysisCtorFn)
        T.MCInstrAnalysisCtorFn = Fn;
    }
    static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {

      if (!T.MCRegInfoCtorFn)
        T.MCRegInfoCtorFn = Fn;
    }
    static void RegisterMCSubtargetInfo(Target &T,
                                        Target::MCSubtargetInfoCtorFnTy Fn) {

      if (!T.MCSubtargetInfoCtorFn)
        T.MCSubtargetInfoCtorFn = Fn;
    }
    static void RegisterTargetMachine(Target &T,
                                      Target::TargetMachineCtorTy Fn) {

      if (!T.TargetMachineCtorFn)
        T.TargetMachineCtorFn = Fn;
    }
    static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) {
      if (!T.MCAsmBackendCtorFn)
        T.MCAsmBackendCtorFn = Fn;
    }
    static void RegisterMCAsmLexer(Target &T, Target::MCAsmLexerCtorTy Fn) {
      if (!T.MCAsmLexerCtorFn)
        T.MCAsmLexerCtorFn = Fn;
    }
    static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) {
      if (!T.MCAsmParserCtorFn)
        T.MCAsmParserCtorFn = Fn;
    }
    static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) {

      if (!T.AsmPrinterCtorFn)
        T.AsmPrinterCtorFn = Fn;
    }
    static void RegisterMCDisassembler(Target &T,
                                       Target::MCDisassemblerCtorTy Fn) {
      if (!T.MCDisassemblerCtorFn)
        T.MCDisassemblerCtorFn = Fn;
    }
    static void RegisterMCInstPrinter(Target &T,
                                      Target::MCInstPrinterCtorTy Fn) {
      if (!T.MCInstPrinterCtorFn)
        T.MCInstPrinterCtorFn = Fn;
    }
    static void RegisterMCCodeEmitter(Target &T,
                                      Target::MCCodeEmitterCtorTy Fn) {
      if (!T.MCCodeEmitterCtorFn)
        T.MCCodeEmitterCtorFn = Fn;
    }
    static void RegisterMCObjectStreamer(Target &T,
                                         Target::MCObjectStreamerCtorTy Fn) {
      if (!T.MCObjectStreamerCtorFn)
        T.MCObjectStreamerCtorFn = Fn;
    }
    static void RegisterAsmStreamer(Target &T, Target::AsmStreamerCtorTy Fn) {
      if (T.AsmStreamerCtorFn == createAsmStreamer)
        T.AsmStreamerCtorFn = Fn;
    }


  };
  template<Triple::ArchType TargetArchType = Triple::InvalidArch,
           bool HasJIT = false>
  struct RegisterTarget {
    RegisterTarget(Target &T, const char *Name, const char *Desc) {
      TargetRegistry::RegisterTarget(T, Name, Desc,
                                     &getTripleMatchQuality,
                                     HasJIT);
    }

    static unsigned getTripleMatchQuality(const std::string &TT) {
      if (Triple(TT).getArch() == TargetArchType)
        return 20;
      return 0;
    }
  };
  template<class MCAsmInfoImpl>
  struct RegisterMCAsmInfo {
    RegisterMCAsmInfo(Target &T) {
      TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
    }
  private:
    static MCAsmInfo *Allocator(const Target &T, StringRef TT) {
      return new MCAsmInfoImpl(T, TT);
    }

  };
  struct RegisterMCAsmInfoFn {
    RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
      TargetRegistry::RegisterMCAsmInfo(T, Fn);
    }
  };
  template<class MCCodeGenInfoImpl>
  struct RegisterMCCodeGenInfo {
    RegisterMCCodeGenInfo(Target &T) {
      TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
    }
  private:
    static MCCodeGenInfo *Allocator(StringRef TT,
                                    Reloc::Model RM, CodeModel::Model CM) {
      return new MCCodeGenInfoImpl();
    }
  };
  struct RegisterMCCodeGenInfoFn {
    RegisterMCCodeGenInfoFn(Target &T, Target::MCCodeGenInfoCtorFnTy Fn) {
      TargetRegistry::RegisterMCCodeGenInfo(T, Fn);
    }
  };
  template<class MCInstrInfoImpl>
  struct RegisterMCInstrInfo {
    RegisterMCInstrInfo(Target &T) {
      TargetRegistry::RegisterMCInstrInfo(T, &Allocator);
    }
  private:
    static MCInstrInfo *Allocator() {
      return new MCInstrInfoImpl();
    }
  };
  struct RegisterMCInstrInfoFn {
    RegisterMCInstrInfoFn(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
      TargetRegistry::RegisterMCInstrInfo(T, Fn);
    }
  };
  template<class MCInstrAnalysisImpl>
  struct RegisterMCInstrAnalysis {
    RegisterMCInstrAnalysis(Target &T) {
      TargetRegistry::RegisterMCInstrAnalysis(T, &Allocator);
    }
  private:
    static MCInstrAnalysis *Allocator(const MCInstrInfo *Info) {
      return new MCInstrAnalysisImpl(Info);
    }
  };
  struct RegisterMCInstrAnalysisFn {
    RegisterMCInstrAnalysisFn(Target &T, Target::MCInstrAnalysisCtorFnTy Fn) {
      TargetRegistry::RegisterMCInstrAnalysis(T, Fn);
    }
  };
  template<class MCRegisterInfoImpl>
  struct RegisterMCRegInfo {
    RegisterMCRegInfo(Target &T) {
      TargetRegistry::RegisterMCRegInfo(T, &Allocator);
    }
  private:
    static MCRegisterInfo *Allocator(StringRef TT) {
      return new MCRegisterInfoImpl();
    }
  };
  struct RegisterMCRegInfoFn {
    RegisterMCRegInfoFn(Target &T, Target::MCRegInfoCtorFnTy Fn) {
      TargetRegistry::RegisterMCRegInfo(T, Fn);
    }
  };
  template<class MCSubtargetInfoImpl>
  struct RegisterMCSubtargetInfo {
    RegisterMCSubtargetInfo(Target &T) {
      TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
    }
  private:
    static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
                                      StringRef FS) {
      return new MCSubtargetInfoImpl();
    }
  };
  struct RegisterMCSubtargetInfoFn {
    RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
      TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
    }
  };
  template<class TargetMachineImpl>
  struct RegisterTargetMachine {
    RegisterTargetMachine(Target &T) {
      TargetRegistry::RegisterTargetMachine(T, &Allocator);
    }

  private:
    static TargetMachine *Allocator(const Target &T, StringRef TT,
                                    StringRef CPU, StringRef FS,
                                    Reloc::Model RM,
                                    CodeModel::Model CM) {
      return new TargetMachineImpl(T, TT, CPU, FS, RM, CM);
    }
  };
  template<class MCAsmBackendImpl>
  struct RegisterMCAsmBackend {
    RegisterMCAsmBackend(Target &T) {
      TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
    }

  private:
    static MCAsmBackend *Allocator(const Target &T, StringRef Triple) {
      return new MCAsmBackendImpl(T, Triple);
    }
  };
  template<class MCAsmLexerImpl>
  struct RegisterMCAsmLexer {
    RegisterMCAsmLexer(Target &T) {
      TargetRegistry::RegisterMCAsmLexer(T, &Allocator);
    }

  private:
    static MCTargetAsmLexer *Allocator(const Target &T,
                                       const MCRegisterInfo &MRI,
                                       const MCAsmInfo &MAI) {
      return new MCAsmLexerImpl(T, MRI, MAI);
    }
  };
  template<class MCAsmParserImpl>
  struct RegisterMCAsmParser {
    RegisterMCAsmParser(Target &T) {
      TargetRegistry::RegisterMCAsmParser(T, &Allocator);
    }

  private:
    static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) {
      return new MCAsmParserImpl(STI, P);
    }
  };
  template<class AsmPrinterImpl>
  struct RegisterAsmPrinter {
    RegisterAsmPrinter(Target &T) {
      TargetRegistry::RegisterAsmPrinter(T, &Allocator);
    }

  private:
    static AsmPrinter *Allocator(TargetMachine &TM, MCStreamer &Streamer) {
      return new AsmPrinterImpl(TM, Streamer);
    }
  };
  template<class MCCodeEmitterImpl>
  struct RegisterMCCodeEmitter {
    RegisterMCCodeEmitter(Target &T) {
      TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);
    }

  private:
    static MCCodeEmitter *Allocator(const MCInstrInfo &II,
                                    const MCSubtargetInfo &STI,
                                    MCContext &Ctx) {
      return new MCCodeEmitterImpl();
    }
  };

}


using namespace llvm;

typedef MCDisassembler::DecodeStatus DecodeStatus;

namespace {

class ARMDisassembler : public MCDisassembler {
public:


  ARMDisassembler(const MCSubtargetInfo &STI) :
    MCDisassembler(STI) {
  }

  ~ARMDisassembler() {
  }


  DecodeStatus getInstruction(MCInst &instr,
                              uint64_t &size,
                              const MemoryObject &region,
                              uint64_t address,
                              raw_ostream &vStream,
                              raw_ostream &cStream) const;


  EDInstInfo *getEDInfo() const;
private:
};


class ThumbDisassembler : public MCDisassembler {
public:


  ThumbDisassembler(const MCSubtargetInfo &STI) :
    MCDisassembler(STI) {
  }

  ~ThumbDisassembler() {
  }


  DecodeStatus getInstruction(MCInst &instr,
                              uint64_t &size,
                              const MemoryObject &region,
                              uint64_t address,
                              raw_ostream &vStream,
                              raw_ostream &cStream) const;


  EDInstInfo *getEDInfo() const;
private:
  mutable std::vector<unsigned> ITBlock;
  DecodeStatus AddThumbPredicate(MCInst&) const;
  void UpdateThumbVFPPredicate(MCInst&) const;
};
}

static bool Check(DecodeStatus &Out, DecodeStatus In) {
  switch (In) {
    case MCDisassembler::Success:

      return true;
    case MCDisassembler::SoftFail:
      Out = In;
      return true;
    case MCDisassembler::Fail:
      Out = In;
      return false;
  }
  return false;
}




static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);
static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
                                               unsigned RegNo, uint64_t Address,
                                               const void *Decoder);
static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);
static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);
static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
                                                unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder);
static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                   uint64_t Address, const void *Decoder);

static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);

static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
                                                  unsigned Insn,
                                                  uint64_t Address,
                                                  const void *Decoder);
static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);

static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
                                                  unsigned Insn,
                                                  uint64_t Adddress,
                                                  const void *Decoder);
static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder);

static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
                               uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);






namespace llvm {


static uint32_t fieldFromInstruction32(uint32_t insn, unsigned startBit, unsigned numBits)
{
  ((startBit + numBits <= 32 && "Instruction field out of bounds!") ? (void)0 : __assert(__func__, "./ARMGenDisassemblerTables.inc.h", 17, "startBit + numBits <= 32 && \"Instruction field out of bounds!\""));

  uint32_t fieldMask;

  if (numBits == 32)
    fieldMask = (uint32_t)-1;
  else
    fieldMask = ((1 << numBits) - 1) << startBit;

  return (insn & fieldMask) >> startBit;
}

static MCDisassembler::DecodeStatus decodeARMInstruction32(MCInst &MI, uint32_t insn, uint64_t Address, const void *Decoder, const MCSubtargetInfo &STI) {
  unsigned tmp = 0;
  (void)tmp;
  MCDisassembler::DecodeStatus S = MCDisassembler::Success;
(void)S;
  uint64_t Bits = STI.getFeatureBits();

  switch (fieldFromInstruction32(insn, 25, 3)) {
  case 0:

    switch (fieldFromInstruction32(insn, 21, 1)) {
    case 0:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 4, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 22, 2)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(31);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(32);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          case 1:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(439);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(440);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          case 2:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(24);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(25);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          case 3:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(312);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(313);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 7, 1)) {
          case 0:

            switch (fieldFromInstruction32(insn, 22, 2)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(33);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(441);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(26);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(314);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 5, 2)) {
            case 0:

              switch (fieldFromInstruction32(insn, 22, 2)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 12, 4) == 0) {
                  MI.setOpcode(244);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 20, 1);
                  if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 20, 1) == 0) {
                  MI.setOpcode(479);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 2:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                  MI.setOpcode(483);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 20, 1);
                  if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 3:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                  MI.setOpcode(356);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 20, 1);
                  if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(421);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(183);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 2:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(174);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(188);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 3:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(412);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(193);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            }
            break;
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 22, 2)) {
        case 0:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:

            switch (fieldFromInstruction32(insn, 5, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 0, 5)) {
              case 0:

                switch (fieldFromInstruction32(insn, 16, 2)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 28, 4) == 15) {
                    MI.setOpcode(123);
                    if (!Check(S, DecodeCPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 18, 2) == 0 && fieldFromInstruction32(insn, 10, 6) == 0 && fieldFromInstruction32(insn, 6, 3) == 0) {
                    MI.setOpcode(317);
                    tmp = fieldFromInstruction32(insn, 9, 1);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    return S;
                  }
                  break;
                }
                break;
              default:
                break;
              }

              switch (fieldFromInstruction32(insn, 4, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 6, 2)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 16, 4) == 15) {
                    MI.setOpcode(240);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 2:
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                    MI.setOpcode(326);
                    if (!Check(S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 3:
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                    MI.setOpcode(327);
                    if (!Check(S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 6, 6)) {
                case 1:
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(273);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 2:
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(443);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              default:
                break;
              }

              switch (fieldFromInstruction32(insn, 16, 2)) {
              case 2:

                switch (fieldFromInstruction32(insn, 28, 4)) {
                case 15:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 18, 2) == 0 && fieldFromInstruction32(insn, 6, 3) == 0) {
                    MI.setOpcode(122);
                    if (!Check(S, DecodeCPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  else
                    if (!(Bits & ARM::ModeThumb)) {
                      MI.setOpcode(124);
                      if (!Check(S, DecodeCPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  break;
                }
                break;
              }
              break;
              break;
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 6, 2)) {
              case 2:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps) &&
                    fieldFromInstruction32(insn, 4, 1) == 0) {
                  MI.setOpcode(338);
                  if (!Check(S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 3:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps) &&
                    fieldFromInstruction32(insn, 4, 1) == 0) {
                  MI.setOpcode(339);
                  if (!Check(S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 4, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 12, 4)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 5, 7) == 0) {
                  MI.setOpcode(466);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(467);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                    if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 12, 4) == 0 && fieldFromInstruction32(insn, 7, 1) == 0) {
                MI.setOpcode(468);
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 4, 1)) {
          case 0:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 5, 3)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 16, 4) == 15) {
                  MI.setOpcode(241);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 4:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(331);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 5:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(335);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 6:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(332);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 7:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(336);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 12, 4)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 5, 7) == 0) {
                  MI.setOpcode(118);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(119);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                    if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 7, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 0 && fieldFromInstruction32(insn, 5, 2) == 2) {
                  MI.setOpcode(277);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 12, 4) == 0) {
                  MI.setOpcode(120);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                  tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                  if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 20, 1) == 0 && fieldFromInstruction32(insn, 8, 4) == 0 && fieldFromInstruction32(insn, 5, 2) == 0) {
                MI.setOpcode(444);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          }
          break;
        case 2:

          switch (fieldFromInstruction32(insn, 4, 1)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(253);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(254);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 7, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(255);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15 && fieldFromInstruction32(insn, 5, 2) == 0) {
                  MI.setOpcode(414);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15 && fieldFromInstruction32(insn, 5, 2) == 0 && fieldFromInstruction32(insn, 0, 4) == 15) {
                  MI.setOpcode(176);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            }
            break;
          }
          break;
        case 3:

          switch (fieldFromInstruction32(insn, 4, 1)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(84);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(85);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 7, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(86);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15 && fieldFromInstruction32(insn, 5, 2) == 0) {
                  MI.setOpcode(415);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15 && fieldFromInstruction32(insn, 5, 2) == 0 && fieldFromInstruction32(insn, 0, 4) == 15) {
                  MI.setOpcode(177);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            }
            break;
          }
          break;
        default:
          break;
        }

        switch (fieldFromInstruction32(insn, 4, 4)) {
        case 11:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(418);
              if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(180);
              if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 13:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
              MI.setOpcode(173);
              if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(185);
              if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 15:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
              MI.setOpcode(411);
              if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(190);
              if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
        break;
      }
      break;
    case 1:

      switch (fieldFromInstruction32(insn, 4, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 2)) {
        case 0:

          switch (fieldFromInstruction32(insn, 22, 1)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(129);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(130);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          case 1:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(301);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(302);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 22, 1)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(16);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(17);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          case 1:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 7) == 0) {
              MI.setOpcode(305);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(306);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          }
          break;
        case 2:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:

            switch (fieldFromInstruction32(insn, 5, 3)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 8, 8) == 240) {
                MI.setOpcode(242);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 8, 12) == 4095) {
                MI.setOpcode(103);
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 4:

              switch (fieldFromInstruction32(insn, 22, 1)) {
              case 0:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(340);
                  if (!Check(S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(354);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 5:

              switch (fieldFromInstruction32(insn, 22, 1)) {
              case 0:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(360);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(358);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 6:

              switch (fieldFromInstruction32(insn, 22, 1)) {
              case 0:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(341);
                  if (!Check(S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(355);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 7:

              switch (fieldFromInstruction32(insn, 22, 1)) {
              case 0:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(361);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV5TEOps)) {
                  MI.setOpcode(359);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 22, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 12, 4)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 5, 7) == 0) {
                  MI.setOpcode(460);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(461);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                    if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 12, 4)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 5, 7) == 0) {
                  MI.setOpcode(114);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(115);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                    if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            }
            break;
          }
          break;
        case 3:

          switch (fieldFromInstruction32(insn, 22, 1)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 5, 16) == 1920 && fieldFromInstruction32(insn, 0, 4) == 14) {
              MI.setOpcode(219);
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else

              switch (fieldFromInstruction32(insn, 5, 7)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 16, 4) == 0) {
                  MI.setOpcode(230);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 20, 1);
                  if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(231);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 20, 1);
                    if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              default:
                break;
              }

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 16, 4) == 0) {
                MI.setOpcode(232);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 16, 4)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 5, 7) == 0) {
                MI.setOpcode(248);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              else
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(249);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                  if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 20, 1);
                  if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              break;
            }
            break;
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 7, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 22, 3)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(131);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
              tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
              if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(303);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
              tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
              if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 2:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(18);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
              tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
              if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 3:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(307);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
              tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
              if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 4:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 5, 2)) {
              case 0:

                switch (fieldFromInstruction32(insn, 8, 12)) {
                case 4095:

                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV4TOps) &&
                      fieldFromInstruction32(insn, 0, 4) == 14) {
                    MI.setOpcode(105);
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  else

                    if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV4TOps) &&
                        fieldFromInstruction32(insn, 28, 4) == 14) {
                      MI.setOpcode(102);
                      tmp = fieldFromInstruction32(insn, 0, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    else
                      if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV4TOps)) {
                        MI.setOpcode(106);
                        tmp = fieldFromInstruction32(insn, 0, 4);
                        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        tmp = fieldFromInstruction32(insn, 28, 4);
                        if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        return S;
                      }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 8, 12)) {
                case 4095:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 28, 4) == 14) {
                    MI.setOpcode(89);
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  else
                    if (!(Bits & ARM::ModeThumb)) {
                      MI.setOpcode(90);
                      tmp = fieldFromInstruction32(insn, 0, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 28, 4);
                      if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  break;
                }
                break;
              case 2:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 0) {
                  MI.setOpcode(280);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 3:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(87);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 8, 12) << 4);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 12, 4) == 0) {
                MI.setOpcode(462);
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          case 5:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 5, 2)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 16, 4) == 15 && fieldFromInstruction32(insn, 8, 4) == 15) {
                  MI.setOpcode(112);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 2:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 0) {
                  MI.setOpcode(278);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 3:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 12) == 0) {
                  MI.setOpcode(325);
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 12, 4) == 0) {
                MI.setOpcode(116);
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
                tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
                if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          case 6:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 16, 4) == 0) {
              MI.setOpcode(233);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
              tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
              if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 7:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 16, 4) == 0) {
              MI.setOpcode(250);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 2) << 5);
              tmp |= (fieldFromInstruction32(insn, 8, 4) << 8);
              if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 5, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 22, 3)) {
            case 0:
              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                MI.setOpcode(210);
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                  fieldFromInstruction32(insn, 20, 1) == 0) {
                MI.setOpcode(212);
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 2:
              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                MI.setOpcode(481);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                MI.setOpcode(330);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 20, 1);
                if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 6:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15) {
                  MI.setOpcode(416);
                  if (!Check(S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15 && fieldFromInstruction32(insn, 0, 4) == 15) {
                  MI.setOpcode(178);
                  if (!Check(S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            case 7:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15) {
                  MI.setOpcode(417);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 8, 4) == 15 && fieldFromInstruction32(insn, 0, 4) == 15) {
                  MI.setOpcode(179);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 24, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 22, 1)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 8, 4) == 0) {
                    MI.setOpcode(420);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 4);
                    if (!Check(S, DecodePostIdxReg(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(419);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 8, 4) << 4);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 8);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              case 1:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(422);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 24, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 22, 1)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 8, 4) == 0) {
                    MI.setOpcode(182);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 4);
                    if (!Check(S, DecodePostIdxReg(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(181);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 8, 4) << 4);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 8);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              case 1:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(184);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 24, 1) == 1) {
                MI.setOpcode(175);
                if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 24, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 22, 1)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 8, 4) == 0) {
                    MI.setOpcode(187);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 4);
                    if (!Check(S, DecodePostIdxReg(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(186);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 8, 4) << 4);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 8);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              case 1:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(189);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) &&
                  fieldFromInstruction32(insn, 24, 1) == 1) {
                MI.setOpcode(413);
                if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 24, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 22, 1)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) &&
                      fieldFromInstruction32(insn, 8, 4) == 0) {
                    MI.setOpcode(192);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 4);
                    if (!Check(S, DecodePostIdxReg(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:
                  if (!(Bits & ARM::ModeThumb)) {
                    MI.setOpcode(191);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 8, 4) << 4);
                    tmp |= (fieldFromInstruction32(insn, 23, 1) << 8);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              case 1:
                if (!(Bits & ARM::ModeThumb)) {
                  MI.setOpcode(194);
                  if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            }
            break;
          }
          break;
        }
        break;
      }
      break;
    }
    break;
  case 1:

    switch (fieldFromInstruction32(insn, 21, 1)) {
    case 0:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 22, 2)) {
        case 0:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(30);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        case 1:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(438);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        case 2:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(23);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        case 3:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(311);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        default:
          break;
        }

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 16, 5) == 15) {
          MI.setOpcode(29);
          tmp = fieldFromInstruction32(insn, 12, 4);
          if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = 0;
          tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
          tmp |= (fieldFromInstruction32(insn, 22, 2) << 12);
          MI.addOperand(MCOperand::CreateImm(tmp));
          tmp = fieldFromInstruction32(insn, 28, 4);
          if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        break;
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 22, 2)) {
        case 0:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops)) {
              MI.setOpcode(227);
              if (!Check(S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 12, 4) == 0) {
              MI.setOpcode(465);
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 12);
              if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops)) {
              MI.setOpcode(221);
              if (!Check(S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 12, 4) == 0) {
              MI.setOpcode(117);
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 12);
              if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 2:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(252);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        case 3:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(83);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        }
        break;
      }
      break;
    case 1:

      switch (fieldFromInstruction32(insn, 23, 2)) {
      case 0:

        switch (fieldFromInstruction32(insn, 22, 1)) {
        case 0:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(128);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        case 1:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(300);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 22, 1)) {
        case 0:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(15);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        case 1:
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(304);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 12);
            if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 1);
            if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        }
        break;
      case 2:

        switch (fieldFromInstruction32(insn, 12, 4)) {
        case 0:

          switch (fieldFromInstruction32(insn, 22, 1)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 20, 1) == 1) {
              MI.setOpcode(459);
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 12);
              if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 1:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 20, 1) == 1) {
              MI.setOpcode(113);
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 12);
              if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 15:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:

            switch (fieldFromInstruction32(insn, 0, 12)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                  fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 16, 4) == 0) {
                MI.setOpcode(251);
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                  fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 16, 4) == 0) {
                MI.setOpcode(1910);
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 2:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                  fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 16, 4) == 0) {
                MI.setOpcode(1908);
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 3:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                  fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 16, 4) == 0) {
                MI.setOpcode(1909);
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 4:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                  fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 16, 4) == 0) {
                MI.setOpcode(318);
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            default:
              break;
            }

            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV7Ops) &&
                fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 16, 4) == 0 && fieldFromInstruction32(insn, 4, 8) == 15) {
              MI.setOpcode(125);
              tmp = fieldFromInstruction32(insn, 0, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(243);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 12);
                if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
            break;
          }
          break;
        }
        break;
      case 3:

        switch (fieldFromInstruction32(insn, 16, 4)) {
        case 0:

          switch (fieldFromInstruction32(insn, 22, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(226);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 12);
              if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(247);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 12);
              if (!Check(S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 20, 1);
              if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 15:

          switch (fieldFromInstruction32(insn, 4, 12)) {
          case 2292:

            if ((Bits & ARM::ModeThumb) && (Bits & ARM::FeatureDB) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 20, 1) == 1) {
              MI.setOpcode(1951);
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2293:

            if ((Bits & ARM::ModeThumb) && (Bits & ARM::FeatureDB) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 20, 1) == 1) {
              MI.setOpcode(1950);
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2294:

            if ((Bits & ARM::ModeThumb) && (Bits & ARM::FeatureThumb2) && (Bits & ARM::FeatureDB) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 22, 1) == 0 && fieldFromInstruction32(insn, 20, 1) == 1) {
              MI.setOpcode(1955);
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        }
        break;
      }
      break;
    }
    break;
  case 2:

    switch (fieldFromInstruction32(insn, 20, 3)) {
    case 0:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(426);
          if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      case 1:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(430);
          tmp = fieldFromInstruction32(insn, 12, 4);
          if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = 0;
          tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
          tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
          tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
          if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 28, 4);
          if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      }
      break;
    case 1:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(197);
          if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      case 1:

        if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV7Ops) && (Bits & ARM::FeatureMP) &&
            fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 12, 4) == 15) {
          MI.setOpcode(267);
          tmp = 0;
          tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
          tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
          tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
          if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(202);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
            tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
            if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 2:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(424);
          if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      case 1:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(428);
          if (!Check(S, DecodeSTRPreImm(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      }
      break;
    case 3:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(195);
          if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      case 1:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(199);
          if (!Check(S, DecodeLDRPreImm(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      }
      break;
    case 4:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(403);
          if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      case 1:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(407);
          tmp = fieldFromInstruction32(insn, 12, 4);
          if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = 0;
          tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
          tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
          tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
          if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 28, 4);
          if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      }
      break;
    case 5:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV7Ops) &&
            fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 12, 4) == 15) {
          MI.setOpcode(271);
          tmp = 0;
          tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
          tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
          tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
          if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(167);
            if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 12, 4) == 15) {
          MI.setOpcode(269);
          tmp = 0;
          tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
          tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
          tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
          if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(171);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 12) << 0);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
            tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
            if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 6:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(401);
          if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      case 1:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(405);
          if (!Check(S, DecodeSTRPreImm(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      }
      break;
    case 7:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(165);
          if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      case 1:

        if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV7Ops) &&
            fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 23, 1) == 0 && fieldFromInstruction32(insn, 0, 20) == 1044511) {
          MI.setOpcode(111);
          return S;
        }
        else

          switch (fieldFromInstruction32(insn, 4, 16)) {
          case 65284:

            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::FeatureDB) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(127);
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 65285:

            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::FeatureDB) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(126);
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 65286:

            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::FeatureDB) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(135);
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          default:
            break;
          }
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(169);
            if (!Check(S, DecodeLDRPreImm(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    }
    break;
  case 3:

    switch (fieldFromInstruction32(insn, 21, 2)) {
    case 0:

      switch (fieldFromInstruction32(insn, 20, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 24, 1)) {
        case 0:

          if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
              fieldFromInstruction32(insn, 23, 1) == 1 && fieldFromInstruction32(insn, 4, 8) == 251) {
            MI.setOpcode(316);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          else

            switch (fieldFromInstruction32(insn, 4, 6)) {
            case 7:

              switch (fieldFromInstruction32(insn, 23, 1)) {
              case 1:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 16, 4) == 15) {
                  MI.setOpcode(449);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 10, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(446);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 10, 2);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            default:
              break;
            }

            switch (fieldFromInstruction32(insn, 4, 3)) {
            case 1:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 23, 1) == 1) {
                MI.setOpcode(265);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 7, 5);
                MI.addOperand(MCOperand::CreateImm(tmp));
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 5:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 23, 1) == 1) {
                MI.setOpcode(266);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 7, 5);
                MI.addOperand(MCOperand::CreateImm(tmp));
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            default:
              break;
            }
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(427);
              if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 4, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(433);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
              tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
              if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:

            switch (fieldFromInstruction32(insn, 5, 3)) {
            case 0:

              switch (fieldFromInstruction32(insn, 23, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 12, 4) == 15) {
                  MI.setOpcode(352);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(328);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 8, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 12, 4) == 15) {
                  MI.setOpcode(491);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(492);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 8, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 23, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 12, 4) == 15) {
                  MI.setOpcode(353);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(329);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 8, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            case 2:

              switch (fieldFromInstruction32(insn, 23, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 12, 4) == 15) {
                  MI.setOpcode(362);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(342);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 8, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            case 3:

              switch (fieldFromInstruction32(insn, 23, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 12, 4) == 15) {
                  MI.setOpcode(363);
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(343);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 8, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            }
            break;
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 24, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 4, 8)) {
          case 241:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(308);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 243:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(310);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 245:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(374);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 247:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(375);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 249:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(309);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 255:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 23, 1) == 0) {
              MI.setOpcode(376);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          default:
            break;
          }
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(198);
            if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 4, 1)) {
          case 0:

            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV7Ops) && (Bits & ARM::FeatureMP) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 12, 4) == 15) {
              MI.setOpcode(268);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
              tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
              if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(203);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
                tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
                if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          }
          break;
        }
        break;
      }
      break;
    case 1:

      switch (fieldFromInstruction32(insn, 4, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 20, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 24, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(425);
              if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(429);
              if (!Check(S, DecodeSTRPreReg(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 24, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(196);
              if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(200);
              if (!Check(S, DecodeLDRPreReg(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 23, 2)) {
        case 0:

          switch (fieldFromInstruction32(insn, 5, 7)) {
          case 120:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(274);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(319);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 121:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(276);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(321);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 122:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(279);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(322);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 123:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(281);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(323);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 124:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(275);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(320);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 127:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(282);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(324);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 5, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(372);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 5);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 6, 1) << 5);
              tmp |= (fieldFromInstruction32(insn, 7, 5) << 0);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:

            switch (fieldFromInstruction32(insn, 6, 4)) {
            case 1:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 16, 4) == 15) {
                  MI.setOpcode(448);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 10, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(445);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 10, 2);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 16, 4) == 15) {
                  MI.setOpcode(450);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 10, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(447);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 10, 2);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            case 12:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 10, 2) == 3) {
                  MI.setOpcode(373);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 16, 4) == 15 && fieldFromInstruction32(insn, 10, 2) == 3) {
                  MI.setOpcode(284);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            case 14:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 16, 5) == 31 && fieldFromInstruction32(insn, 10, 2) == 3) {
                MI.setOpcode(285);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          }
          break;
        case 3:

          if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
              fieldFromInstruction32(insn, 5, 2) == 2) {
            MI.setOpcode(315);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 4);
            if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 7, 5);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 16, 5);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      }
      break;
    case 2:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 20, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 4, 6)) {
          case 7:

            switch (fieldFromInstruction32(insn, 23, 1)) {
            case 1:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 16, 4) == 15) {
                MI.setOpcode(502);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 10, 2);
                MI.addOperand(MCOperand::CreateImm(tmp));
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              else
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                  MI.setOpcode(499);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 10, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              break;
            }
            break;
          default:
            break;
          }
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(404);
            if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 23, 1)) {
          case 0:

            switch (fieldFromInstruction32(insn, 4, 8)) {
            case 241:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(469);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(471);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 245:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(495);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 247:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(496);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 249:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(470);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 255:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(497);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          default:
            break;
          }

          if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV7Ops) &&
              fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 12, 4) == 15 && fieldFromInstruction32(insn, 4, 1) == 0) {
            MI.setOpcode(272);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
            tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
            if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(168);
              if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 4, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 20, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(410);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
              tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
              if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 12, 4) == 15) {
              MI.setOpcode(270);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
              tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
              if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            else
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(172);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 7) << 5);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 13);
                tmp |= (fieldFromInstruction32(insn, 23, 1) << 12);
                if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 5, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 23, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 7, 1) == 0) {
                  MI.setOpcode(333);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 8, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 7, 1)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                      fieldFromInstruction32(insn, 12, 4) == 15) {
                    MI.setOpcode(350);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 8, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  else
                    if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                      MI.setOpcode(346);
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 0, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 8, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 12, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 28, 4);
                      if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  break;
                }
                break;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                  fieldFromInstruction32(insn, 0, 4) == 15) {
                MI.setOpcode(81);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 5) << 0);
                tmp |= (fieldFromInstruction32(insn, 16, 5) << 5);
                if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              else
                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops)) {
                  MI.setOpcode(82);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 7, 5) << 0);
                  tmp |= (fieldFromInstruction32(insn, 16, 5) << 5);
                  if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              break;
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 23, 1) == 0 && fieldFromInstruction32(insn, 7, 1) == 0) {
                MI.setOpcode(334);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 7, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 23, 1)) {
                case 0:

                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                      fieldFromInstruction32(insn, 12, 4) == 15) {
                    MI.setOpcode(351);
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 8, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  else
                    if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                      MI.setOpcode(347);
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 0, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 8, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 12, 4);
                      if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 28, 4);
                      if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  break;
                }
                break;
              }
              break;
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 7, 1)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 23, 1) == 0 && fieldFromInstruction32(insn, 20, 1) == 0) {
                MI.setOpcode(344);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 23, 1) == 0 && fieldFromInstruction32(insn, 20, 1) == 1) {
                MI.setOpcode(348);
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 7, 1)) {
            case 0:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 23, 1) == 0 && fieldFromInstruction32(insn, 20, 1) == 0) {
                MI.setOpcode(345);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            case 1:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 23, 1) == 0 && fieldFromInstruction32(insn, 20, 1) == 1) {
                MI.setOpcode(349);
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          }
          break;
        }
        break;
      }
      break;
    case 3:

      switch (fieldFromInstruction32(insn, 4, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 20, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 24, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(402);
              if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(406);
              if (!Check(S, DecodeSTRPreReg(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 24, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(166);
              if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(170);
              if (!Check(S, DecodeLDRPreReg(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 23, 2)) {
        case 0:

          switch (fieldFromInstruction32(insn, 5, 7)) {
          case 120:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(485);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(473);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 121:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(487);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(475);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 122:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(488);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(476);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 123:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(489);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(477);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 124:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(486);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(474);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 127:

            switch (fieldFromInstruction32(insn, 20, 1)) {
            case 0:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(490);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if (!(Bits & ARM::ModeThumb)) {
                MI.setOpcode(478);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 5, 1)) {
          case 0:
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(493);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 5);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 6, 1) << 5);
              tmp |= (fieldFromInstruction32(insn, 7, 5) << 0);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:

            switch (fieldFromInstruction32(insn, 6, 4)) {
            case 1:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 16, 4) == 15) {
                  MI.setOpcode(501);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 10, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(498);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 10, 2);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                    fieldFromInstruction32(insn, 16, 4) == 15) {
                  MI.setOpcode(503);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 10, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                else
                  if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops)) {
                    MI.setOpcode(500);
                    tmp = fieldFromInstruction32(insn, 12, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 0, 4);
                    if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 10, 2);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    tmp = fieldFromInstruction32(insn, 28, 4);
                    if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                break;
              }
              break;
            case 12:

              switch (fieldFromInstruction32(insn, 20, 1)) {
              case 0:

                if (!(Bits & ARM::ModeThumb) &&
                    fieldFromInstruction32(insn, 10, 2) == 3) {
                  MI.setOpcode(494);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 4);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops) &&
                    fieldFromInstruction32(insn, 16, 4) == 15 && fieldFromInstruction32(insn, 10, 2) == 3) {
                  MI.setOpcode(283);
                  tmp = fieldFromInstruction32(insn, 12, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 0, 4);
                  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 28, 4);
                  if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            case 14:

              if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6Ops) &&
                  fieldFromInstruction32(insn, 16, 5) == 31 && fieldFromInstruction32(insn, 10, 2) == 3) {
                MI.setOpcode(286);
                tmp = fieldFromInstruction32(insn, 12, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 0, 4);
                if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 28, 4);
                if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
              break;
            }
            break;
          }
          break;
        case 3:

          switch (fieldFromInstruction32(insn, 5, 2)) {
          case 2:
            if (!(Bits & ARM::ModeThumb) && (Bits & ARM::HasV6T2Ops)) {
              MI.setOpcode(472);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 7, 5);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 16, 5);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 3:

            if (!(Bits & ARM::ModeThumb) &&
                fieldFromInstruction32(insn, 28, 4) == 14 && fieldFromInstruction32(insn, 7, 14) == 16317 && fieldFromInstruction32(insn, 0, 4) == 14) {
              MI.setOpcode(464);
              return S;
            }
            break;
          }
          break;
        }
        break;
      }
      break;
    }
    break;
  case 4:

    switch (fieldFromInstruction32(insn, 20, 5)) {
    case 0:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(393);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 28, 4);
        if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 0, 16);
        if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 1:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(287);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(156);
          tmp = fieldFromInstruction32(insn, 16, 4);
          if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 28, 4);
          if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 0, 16);
          if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 2:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(394);
        if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 3:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(288);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(157);
          if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 4:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(364);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    case 6:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(365);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    case 8:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(397);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 28, 4);
        if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 0, 16);
        if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 9:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(291);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(160);
          tmp = fieldFromInstruction32(insn, 16, 4);
          if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 28, 4);
          if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 0, 16);
          if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 10:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(398);
        if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 11:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(292);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(162);
          if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 12:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(368);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    case 14:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(369);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    case 16:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(395);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 28, 4);
        if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 0, 16);
        if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 17:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(289);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(158);
          tmp = fieldFromInstruction32(insn, 16, 4);
          if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 28, 4);
          if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 0, 16);
          if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 18:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(396);
        if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 19:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(290);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(159);
          if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 20:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(366);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    case 22:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(367);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    case 24:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(399);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 28, 4);
        if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        tmp = fieldFromInstruction32(insn, 0, 16);
        if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 25:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(293);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(163);
          tmp = fieldFromInstruction32(insn, 16, 4);
          if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 28, 4);
          if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 0, 16);
          if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 26:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(400);
        if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 27:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 0, 16) == 2560) {
        MI.setOpcode(294);
        tmp = fieldFromInstruction32(insn, 16, 4);
        if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(164);
          if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    case 28:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(370);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    case 30:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 15 && fieldFromInstruction32(insn, 5, 15) == 26664) {
        MI.setOpcode(371);
        tmp = fieldFromInstruction32(insn, 0, 5);
        MI.addOperand(MCOperand::CreateImm(tmp));
        return S;
      }
      break;
    }
    break;
  case 5:

    switch (fieldFromInstruction32(insn, 24, 1)) {
    case 0:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(108);
        if (!Check(S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    case 1:

      if (!(Bits & ARM::ModeThumb) &&
          fieldFromInstruction32(insn, 28, 4) == 14) {
        MI.setOpcode(88);
        if (!Check(S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
      else
        if (!(Bits & ARM::ModeThumb)) {
          MI.setOpcode(94);
          if (!Check(S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
      break;
    default:
      break;
    }

    if (!(Bits & ARM::ModeThumb) &&
        fieldFromInstruction32(insn, 28, 4) == 15) {
      MI.setOpcode(91);
      tmp = 0;
      tmp |= (fieldFromInstruction32(insn, 0, 24) << 1);
      tmp |= (fieldFromInstruction32(insn, 24, 1) << 0);
      MI.addOperand(MCOperand::CreateImm(tmp));
      return S;
    }
    break;
    break;
  case 6:

    switch (fieldFromInstruction32(insn, 20, 3)) {
    case 0:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 1)) {
        case 1:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(382);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(390);
              if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(381);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(389);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 1:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 1)) {
        case 1:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(145);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(153);
              if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(144);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(152);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 2:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(383);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(391);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(384);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(392);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 3:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(146);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(154);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(147);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(155);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 4:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 1)) {
        case 0:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(209);
            tmp = fieldFromInstruction32(insn, 8, 4);
            if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 4, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(208);
              tmp = fieldFromInstruction32(insn, 8, 4);
              if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 4, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        case 1:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(378);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(386);
              if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(377);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(385);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 5:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 1)) {
        case 0:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(239);
            tmp = fieldFromInstruction32(insn, 8, 4);
            if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 4, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(238);
              tmp = fieldFromInstruction32(insn, 8, 4);
              if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 4, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        case 1:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(141);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(149);
              if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(140);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(148);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 6:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(379);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(387);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(380);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(388);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    case 7:

      switch (fieldFromInstruction32(insn, 24, 1)) {
      case 0:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(142);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(150);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      case 1:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(143);
          if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(151);
            if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      }
      break;
    }
    break;
  case 7:

    switch (fieldFromInstruction32(insn, 24, 1)) {
    case 0:

      switch (fieldFromInstruction32(insn, 4, 1)) {
      case 0:

        if (!(Bits & ARM::ModeThumb) &&
            fieldFromInstruction32(insn, 28, 4) == 15) {
          MI.setOpcode(110);
          tmp = fieldFromInstruction32(insn, 8, 4);
          if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
          tmp = fieldFromInstruction32(insn, 20, 4);
          MI.addOperand(MCOperand::CreateImm(tmp));
          tmp = fieldFromInstruction32(insn, 12, 4);
          MI.addOperand(MCOperand::CreateImm(tmp));
          tmp = fieldFromInstruction32(insn, 16, 4);
          MI.addOperand(MCOperand::CreateImm(tmp));
          tmp = fieldFromInstruction32(insn, 0, 4);
          MI.addOperand(MCOperand::CreateImm(tmp));
          tmp = fieldFromInstruction32(insn, 5, 3);
          MI.addOperand(MCOperand::CreateImm(tmp));
          return S;
        }
        else
          if (!(Bits & ARM::ModeThumb)) {
            MI.setOpcode(109);
            tmp = fieldFromInstruction32(insn, 8, 4);
            if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 20, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 12, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 16, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 0, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 5, 3);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 28, 4);
            if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 20, 1)) {
        case 0:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(207);
            tmp = fieldFromInstruction32(insn, 8, 4);
            if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 21, 3);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 16, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 0, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 5, 3);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(206);
              tmp = fieldFromInstruction32(insn, 8, 4);
              if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 21, 3);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 0, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 5, 3);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        case 1:

          if (!(Bits & ARM::ModeThumb) &&
              fieldFromInstruction32(insn, 28, 4) == 15) {
            MI.setOpcode(237);
            tmp = fieldFromInstruction32(insn, 12, 4);
            if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 8, 4);
            if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 21, 3);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 16, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 0, 4);
            MI.addOperand(MCOperand::CreateImm(tmp));
            tmp = fieldFromInstruction32(insn, 5, 3);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          else
            if (!(Bits & ARM::ModeThumb)) {
              MI.setOpcode(236);
              tmp = fieldFromInstruction32(insn, 12, 4);
              if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 8, 4);
              if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 21, 3);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 16, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 0, 4);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 5, 3);
              MI.addOperand(MCOperand::CreateImm(tmp));
              tmp = fieldFromInstruction32(insn, 28, 4);
              if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          break;
        }
        break;
      }
      break;
    case 1:
      if (!(Bits & ARM::ModeThumb)) {
        MI.setOpcode(442);
        tmp = fieldFromInstruction32(insn, 0, 24);
        MI.addOperand(MCOperand::CreateImm(tmp));
        tmp = fieldFromInstruction32(insn, 28, 4);
        if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
        return S;
      }
    }
    break;
  }

  return MCDisassembler::Fail;
}

static MCDisassembler::DecodeStatus decodeNEONDataInstruction32(MCInst &MI, uint32_t insn, uint64_t Address, const void *Decoder, const MCSubtargetInfo &STI) {
  unsigned tmp = 0;
  (void)tmp;
  MCDisassembler::DecodeStatus S = MCDisassembler::Success;
(void)S;
  uint64_t Bits = STI.getFeatureBits();

  switch (fieldFromInstruction32(insn, 4, 1)) {
  case 0:

    switch (fieldFromInstruction32(insn, 20, 2)) {
    case 0:

      switch (fieldFromInstruction32(insn, 8, 4)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(753);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(748);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(562);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(759);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(754);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(565);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1448);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1443);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(569);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1454);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1449);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(572);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 2:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(765);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(760);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1825);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(771);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(766);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1828);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 3:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(642);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(637);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1832);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(648);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(643);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1835);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 4:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1542);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1535);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(559);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1550);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1543);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1424);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 5:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1462);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1455);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(506);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1470);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1463);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(509);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 6:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1060);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1055);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1822);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1066);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1061);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1514);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 7:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(535);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(530);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(524);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(541);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(536);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(527);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 8:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(582);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(575);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1088);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1845);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1838);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1091);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 9:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 484:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1106);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 486:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1132);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 484:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1101);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 486:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1127);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 10:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1256);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1114);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1259);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1117);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 12:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1174);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1177);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 13:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 484:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(573);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 486:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1249);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 23, 9) == 484) {
            MI.setOpcode(574);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 14:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(597);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(598);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1167);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(613);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(614);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 15:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 484:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1053);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 486:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1253);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 23, 9) == 484) {
            MI.setOpcode(1054);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      }
      break;
    case 1:

      switch (fieldFromInstruction32(insn, 8, 4)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(750);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(752);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(561);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1098);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(756);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(758);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(564);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1100);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1445);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1447);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(568);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1451);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1453);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(571);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 2:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(762);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(764);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1824);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1083);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(768);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(770);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1827);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1085);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 3:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(639);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(641);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1831);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1290);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(645);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(647);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1834);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 4:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1539);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1541);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(558);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1124);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1547);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1549);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1423);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1126);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 5:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1459);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1461);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(505);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1467);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1469);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(508);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 6:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1057);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1059);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1821);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1109);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1063);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1065);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1513);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1111);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 7:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(532);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(534);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(523);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1294);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(538);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(540);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(526);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 8:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(579);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(581);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1087);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1186);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1842);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1844);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1090);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1188);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 9:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1103);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1105);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1292);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1129);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1131);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 10:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1254);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1113);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1169);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1257);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1116);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1171);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 11:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1302);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1304);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1296);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1306);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1329);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1331);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 12:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 485:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1173);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 487:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1176);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 485:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1298);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          case 487:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1300);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 13:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 23, 9) == 485) {
            MI.setOpcode(1308);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 485:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1325);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          case 487:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1327);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 3);
              if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 3, 1) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      }
      break;
    case 2:

      switch (fieldFromInstruction32(insn, 8, 4)) {
      case 0:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(749);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(751);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(560);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1097);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(755);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(757);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(563);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1099);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1444);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1446);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(567);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1095);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1450);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1452);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(570);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1096);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 2:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(761);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(763);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1823);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1082);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(767);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(769);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1826);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1084);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 3:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(638);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(640);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1830);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1289);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(644);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(646);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1833);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 4:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1537);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1540);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(557);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1123);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1545);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1548);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1422);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1125);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 5:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1457);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1460);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(504);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1121);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1465);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1468);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(507);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1122);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 6:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1056);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1058);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1820);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1108);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1062);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1064);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1512);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1110);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 7:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(531);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(533);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(522);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1293);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(537);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(539);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(525);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 8:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(577);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(580);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1086);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1185);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1840);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1843);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1089);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1187);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 9:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1102);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1104);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1291);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1183);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1128);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1130);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 1) {
            MI.setOpcode(1184);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 4);
            if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 5, 1);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          break;
        }
        break;
      case 10:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1255);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1112);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1168);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 0) {
            MI.setOpcode(1258);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 487:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1115);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1170);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 11:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1301);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1303);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1295);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1305);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1328);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1330);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 12:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 485:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1172);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 487:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1175);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 485:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1297);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          case 487:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1299);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        }
        break;
      case 13:

        switch (fieldFromInstruction32(insn, 23, 9)) {
        case 484:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1836);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1837);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 485:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1307);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1324);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 0, 4);
              if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 5, 1);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
          }
          break;
        case 486:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(528);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(529);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 487:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 6, 1) == 1) {
            MI.setOpcode(1326);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 0, 4);
            if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 5, 1);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          break;
        }
        break;
      case 14:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 23, 9) == 486) {
            MI.setOpcode(635);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        case 1:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 23, 9) == 486) {
            MI.setOpcode(636);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      case 15:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 23, 9)) {
          case 484:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1067);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 486:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1260);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 1:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 23, 9) == 484) {
            MI.setOpcode(1068);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            return S;
          }
          break;
        }
        break;
      }
      break;
    case 3:

      switch (fieldFromInstruction32(insn, 23, 9)) {
      case 484:

        switch (fieldFromInstruction32(insn, 8, 4)) {
        case 4:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1536);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1538);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 5:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1456);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1458);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 8:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(576);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(578);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 485:

        switch (fieldFromInstruction32(insn, 6, 1)) {
        case 0:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 8, 2) == 0) {
            MI.setOpcode(738);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 10, 2);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          else

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 8, 1) == 0) {
              MI.setOpcode(737);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 9, 3);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
            else
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(739);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
          break;
        case 1:

          if ((Bits & ARM::FeatureNEON) &&
              fieldFromInstruction32(insn, 8, 2) == 0) {
            MI.setOpcode(741);
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
            tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = 0;
            tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
            tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
            if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
            tmp = fieldFromInstruction32(insn, 10, 2);
            MI.addOperand(MCOperand::CreateImm(tmp));
            return S;
          }
          else

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 8, 1) == 0) {
              MI.setOpcode(740);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 9, 3);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
            else
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(742);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 8, 4);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
          break;
        }
        break;
      case 486:

        switch (fieldFromInstruction32(insn, 8, 4)) {
        case 4:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1544);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1546);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 5:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1464);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1466);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 8:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1839);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1841);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        }
        break;
      case 487:

        switch (fieldFromInstruction32(insn, 8, 4)) {
        case 0:

          switch (fieldFromInstruction32(insn, 16, 4)) {
          case 0:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1439);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1442);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1434);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1436);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(656);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(649);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(634);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(627);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1846);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1847);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1880);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1883);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 4:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1437);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1440);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1433);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1435);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 5:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(653);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(655);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(631);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(633);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 6:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1878);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1881);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 8:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1438);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1441);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 9:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(651);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(654);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(629);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(632);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 10:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1879);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1882);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 16, 4)) {
          case 0:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1431);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1432);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(612);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(605);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(664);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(657);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1898);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1901);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1904);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1907);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 5:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(609);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(611);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(661);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(663);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 6:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1896);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1899);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1902);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1905);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 9:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(607);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(610);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(659);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(662);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 10:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1897);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1900);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1903);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1906);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 2:

          switch (fieldFromInstruction32(insn, 16, 4)) {
          case 0:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1242);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1237);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1248);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1243);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(678);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(671);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1144);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1311);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1314);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1317);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 4:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1239);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1241);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1245);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1247);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 5:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(675);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(677);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 6:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1143);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1310);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1313);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1316);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 8:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1238);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1240);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1244);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1246);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 9:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(673);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(676);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 10:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1142);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1309);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1312);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1315);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 3:

          switch (fieldFromInstruction32(insn, 16, 4)) {
          case 1:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(551);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(546);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1209);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1210);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 6, 2) == 0) {
              MI.setOpcode(1520);
              if (!Check(S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 5:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(548);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(550);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1205);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1206);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 6:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 6, 2) == 0) {
              MI.setOpcode(1518);
              if (!Check(S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 9:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(547);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(549);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1207);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1208);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 10:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 6, 2) == 0) {
              MI.setOpcode(1519);
              if (!Check(S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 4:

          switch (fieldFromInstruction32(insn, 16, 4)) {
          case 0:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(670);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(665);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(684);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(679);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 4:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(667);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(669);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(681);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(683);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 8:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(666);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(668);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(680);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(682);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 9:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(650);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(652);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(628);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(630);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 11:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1425);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1428);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1490);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1493);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 5:

          switch (fieldFromInstruction32(insn, 6, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 16, 4)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(693);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 9:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(606);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 11:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1426);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 16, 4)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(694);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 9:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(608);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 11:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1427);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 16, 4)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1195);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 9:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(658);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 11:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1491);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 16, 4)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1196);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 9:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(660);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 11:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1492);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 6:

          switch (fieldFromInstruction32(insn, 16, 4)) {
          case 0:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1230);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1225);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1236);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1231);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 4:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1227);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1229);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1233);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1235);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 6:

            if ((Bits & ARM::FeatureNEON) && (Bits & ARM::FeatureFP16) &&
                fieldFromInstruction32(insn, 6, 2) == 0) {
              MI.setOpcode(701);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 8:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1226);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1228);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1232);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1234);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 9:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(672);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(674);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 11:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(711);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(712);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(713);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(714);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 7:

          switch (fieldFromInstruction32(insn, 16, 4)) {
          case 0:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1272);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1267);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1323);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1318);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 4:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1269);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1271);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1320);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1322);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 6:

            if ((Bits & ARM::FeatureNEON) && (Bits & ARM::FeatureFP16) &&
                fieldFromInstruction32(insn, 6, 2) == 0) {
              MI.setOpcode(710);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 8:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1268);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1270);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1319);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1321);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 9:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(544);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(545);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1204);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1203);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 11:

            switch (fieldFromInstruction32(insn, 6, 2)) {
            case 0:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(702);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(703);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 2:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(704);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 3:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(705);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 8:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1848);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1855);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 9:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1849);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1856);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 10:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1851);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1858);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 11:

          switch (fieldFromInstruction32(insn, 6, 1)) {
          case 0:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1853);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          case 1:
            if ((Bits & ARM::FeatureNEON)) {
              MI.setOpcode(1860);
              if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
          }
          break;
        case 12:

          switch (fieldFromInstruction32(insn, 6, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 16, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 17, 1)) {
              case 0:

                if ((Bits & ARM::FeatureNEON) &&
                    fieldFromInstruction32(insn, 18, 1) == 1) {
                  MI.setOpcode(729);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 19, 1);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  return S;
                }
                break;
              case 1:
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(727);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 18, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  return S;
                }
              }
              break;
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(731);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 17, 3);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 16, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 17, 1)) {
              case 0:

                if ((Bits & ARM::FeatureNEON) &&
                    fieldFromInstruction32(insn, 18, 1) == 1) {
                  MI.setOpcode(730);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 19, 1);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  return S;
                }
                break;
              case 1:
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(728);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 18, 2);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  return S;
                }
              }
              break;
            case 1:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(732);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 17, 3);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
            }
            break;
          }
          break;
        }
        break;
      }
      break;
    }
    break;
  case 1:

    switch (fieldFromInstruction32(insn, 6, 1)) {
    case 0:

      switch (fieldFromInstruction32(insn, 23, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 8, 4)) {
        case 0:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1280);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1288);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1277);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1285);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1275);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1283);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1274);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1282);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(583);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(735);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(585);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(595);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1219);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(593);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1217);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(591);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 2:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1413);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1421);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1410);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1418);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1408);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1416);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1407);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1415);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 3:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(620);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(626);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(617);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(623);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(616);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(622);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 4:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1380);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1396);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1377);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1393);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1375);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1391);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1374);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1390);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 5:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1339);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1347);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1336);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1344);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1334);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1342);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1333);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1341);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 6:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1074);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1080);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1071);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1077);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1070);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1076);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 7:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(515);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(521);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(512);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(518);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(511);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(517);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 8:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1889);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(604);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1886);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(601);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1885);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(600);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 9:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1194);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1181);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1191);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1190);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 10:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1263);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1266);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1261);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1264);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1262);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1265);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 11:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1252);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 1:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1250);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1251);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 13:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1093);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1179);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1119);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 14:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 243) {
              MI.setOpcode(552);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 243) {
              MI.setOpcode(554);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 15:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1429);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1494);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 7, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 25, 7)) {
          case 121:

            switch (fieldFromInstruction32(insn, 8, 4)) {
            case 0:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1561);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1569);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1558);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1566);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1556);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1564);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1593);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1601);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1590);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1598);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1588);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1596);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              }
              break;
            case 2:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1481);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1489);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1478);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1486);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1476);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1484);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              }
              break;
            case 3:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1503);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1511);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1500);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1508);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1498);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1506);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              }
              break;
            case 4:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 24, 1) == 1 && fieldFromInstruction32(insn, 19, 1) == 1) {
                    MI.setOpcode(1609);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 3);
                    if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 24, 1) == 1) {
                    MI.setOpcode(1606);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                }
                break;
              case 1:

                if ((Bits & ARM::FeatureNEON) &&
                    fieldFromInstruction32(insn, 24, 1) == 1) {
                  MI.setOpcode(1604);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 5);
                  if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            case 5:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1534);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1581);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1531);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1578);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1529);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1576);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    return S;
                  }
                }
                break;
              }
              break;
            case 6:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 24, 1) == 1 && fieldFromInstruction32(insn, 19, 1) == 1) {
                    MI.setOpcode(1372);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 3);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    return S;
                  }
                  break;
                case 1:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 24, 1) == 1) {
                    MI.setOpcode(1369);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 4);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    return S;
                  }
                  break;
                }
                break;
              case 1:

                if ((Bits & ARM::FeatureNEON) &&
                    fieldFromInstruction32(insn, 24, 1) == 1) {
                  MI.setOpcode(1367);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 5);
                  MI.addOperand(MCOperand::CreateImm(tmp));
                  return S;
                }
                break;
              }
              break;
            case 7:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1364);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1388);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1361);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1385);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1359);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1383);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    MI.addOperand(MCOperand::CreateImm(tmp));
                    return S;
                  }
                }
                break;
              }
              break;
            case 8:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1553);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1405);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1552);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1404);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1551);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1403);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              }
              break;
            case 9:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1399);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1402);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1398);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1401);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1397);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1400);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              }
              break;
            case 10:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    switch (fieldFromInstruction32(insn, 19, 1)) {
                    case 1:

                      if ((Bits & ARM::FeatureNEON) &&
                          fieldFromInstruction32(insn, 16, 3) == 0) {
                        MI.setOpcode(1138);
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                        if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                        if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        return S;
                      }
                      else
                        if ((Bits & ARM::FeatureNEON)) {
                          MI.setOpcode(1523);
                          tmp = 0;
                          tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                          tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                          if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                          tmp = 0;
                          tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                          tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                          if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                          tmp = fieldFromInstruction32(insn, 16, 3);
                          MI.addOperand(MCOperand::CreateImm(tmp));
                          return S;
                        }
                      break;
                    }
                    break;
                  case 1:

                    switch (fieldFromInstruction32(insn, 19, 1)) {
                    case 1:

                      if ((Bits & ARM::FeatureNEON) &&
                          fieldFromInstruction32(insn, 16, 3) == 0) {
                        MI.setOpcode(1141);
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                        if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                        if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        return S;
                      }
                      else
                        if ((Bits & ARM::FeatureNEON)) {
                          MI.setOpcode(1526);
                          tmp = 0;
                          tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                          tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                          if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                          tmp = 0;
                          tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                          tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                          if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                          tmp = fieldFromInstruction32(insn, 16, 3);
                          MI.addOperand(MCOperand::CreateImm(tmp));
                          return S;
                        }
                      break;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 16, 4) == 0) {
                      MI.setOpcode(1137);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    else
                      if ((Bits & ARM::FeatureNEON)) {
                        MI.setOpcode(1522);
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                        if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                        if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        tmp = fieldFromInstruction32(insn, 16, 4);
                        MI.addOperand(MCOperand::CreateImm(tmp));
                        return S;
                      }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 16, 4) == 0) {
                      MI.setOpcode(1140);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    else
                      if ((Bits & ARM::FeatureNEON)) {
                        MI.setOpcode(1525);
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                        if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        tmp = 0;
                        tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                        tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                        if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                        tmp = fieldFromInstruction32(insn, 16, 4);
                        MI.addOperand(MCOperand::CreateImm(tmp));
                        return S;
                      }
                    break;
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 16, 5) == 0) {
                    MI.setOpcode(1136);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  else
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1521);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 5);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                  break;
                case 1:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 16, 5) == 0) {
                    MI.setOpcode(1139);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  else
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1524);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 5);
                      MI.addOperand(MCOperand::CreateImm(tmp));
                      return S;
                    }
                  break;
                }
                break;
              }
              break;
            case 14:

              switch (fieldFromInstruction32(insn, 5, 1)) {
              case 0:

                if ((Bits & ARM::FeatureNEON) &&
                    fieldFromInstruction32(insn, 19, 3) == 0) {
                  MI.setOpcode(1159);
                  if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              case 1:

                if ((Bits & ARM::FeatureNEON) &&
                    fieldFromInstruction32(insn, 19, 3) == 0) {
                  MI.setOpcode(1153);
                  if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              default:
                break;
              }

              switch (fieldFromInstruction32(insn, 24, 1)) {
              case 0:
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(715);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 6);
                  if (!Check(S, DecodeVCVTImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(717);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 6);
                  if (!Check(S, DecodeVCVTImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
              break;
            case 15:

              switch (fieldFromInstruction32(insn, 24, 1)) {
              case 0:
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(706);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 6);
                  if (!Check(S, DecodeVCVTImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              case 1:
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(708);
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = 0;
                  tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                  tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                  if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  tmp = fieldFromInstruction32(insn, 16, 6);
                  if (!Check(S, DecodeVCVTImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
              }
              break;
            default:
              break;
            }

            switch (fieldFromInstruction32(insn, 5, 1)) {
            case 0:

              switch (fieldFromInstruction32(insn, 19, 3)) {
              case 0:

                switch (fieldFromInstruction32(insn, 8, 1)) {
                case 0:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 10, 2) == 2) {
                    MI.setOpcode(1156);
                    if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 11, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1220);
                      if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 10, 1) == 0) {
                      MI.setOpcode(1221);
                      if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                default:
                  break;
                }
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(1154);
                  if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 19, 3)) {
              case 0:

                switch (fieldFromInstruction32(insn, 8, 1)) {
                case 0:

                  if ((Bits & ARM::FeatureNEON) &&
                      fieldFromInstruction32(insn, 10, 2) == 2) {
                    MI.setOpcode(1198);
                    if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 11, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(586);
                      if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 10, 1) == 0) {
                      MI.setOpcode(587);
                      if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                default:
                  break;
                }
                if ((Bits & ARM::FeatureNEON)) {
                  MI.setOpcode(1197);
                  if (!Check(S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler::Fail;
                  return S;
                }
                break;
              }
              break;
            }
            break;
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 8, 4)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1555);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1563);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1587);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1595);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1475);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1483);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1497);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1505);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 4:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 243) {
              MI.setOpcode(1603);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 6);
              if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 5:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1528);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1575);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
            }
            break;
          case 6:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 243) {
              MI.setOpcode(1366);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = fieldFromInstruction32(insn, 16, 6);
              MI.addOperand(MCOperand::CreateImm(tmp));
              return S;
            }
            break;
          case 7:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1358);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1382);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = fieldFromInstruction32(insn, 16, 6);
                MI.addOperand(MCOperand::CreateImm(tmp));
                return S;
              }
            }
            break;
          }
          break;
        }
        break;
      }
      break;
    case 1:

      switch (fieldFromInstruction32(insn, 23, 1)) {
      case 0:

        switch (fieldFromInstruction32(insn, 8, 4)) {
        case 0:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1273);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1281);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1279);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1287);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1278);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1286);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1276);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1284);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 1:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(584);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(736);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(590);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(596);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1224);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(594);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1218);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(592);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 2:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1406);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1414);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1412);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1420);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1411);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1419);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1409);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1417);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 3:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(615);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(621);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(619);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(625);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(618);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(624);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 4:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1373);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1389);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1379);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1395);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1378);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1394);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1376);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1392);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 5:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1332);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1340);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1338);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1346);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1337);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1345);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 3:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1335);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1343);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 6:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1069);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1075);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1073);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1079);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1072);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1078);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 7:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(510);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(516);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(514);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(520);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(513);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(519);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 8:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1884);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(599);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1888);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(603);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1887);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(602);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          }
          break;
        case 9:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1189);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1182);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 1:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1193);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1192);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 13:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            switch (fieldFromInstruction32(insn, 24, 8)) {
            case 242:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1094);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            case 243:
              if ((Bits & ARM::FeatureNEON)) {
                MI.setOpcode(1180);
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
                tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                tmp = 0;
                tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                return S;
              }
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1120);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 14:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 243) {
              MI.setOpcode(553);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 243) {
              MI.setOpcode(555);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        case 15:

          switch (fieldFromInstruction32(insn, 20, 2)) {
          case 0:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1430);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          case 2:

            if ((Bits & ARM::FeatureNEON) &&
                fieldFromInstruction32(insn, 24, 8) == 242) {
              MI.setOpcode(1495);
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 7, 1) << 4);
              tmp |= (fieldFromInstruction32(insn, 16, 4) << 0);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              tmp = 0;
              tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
              tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
              if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
              return S;
            }
            break;
          }
          break;
        }
        break;
      case 1:

        switch (fieldFromInstruction32(insn, 7, 1)) {
        case 0:

          switch (fieldFromInstruction32(insn, 25, 7)) {
          case 121:

            switch (fieldFromInstruction32(insn, 8, 4)) {
            case 0:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1554);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1562);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  }
                  break;
                case 1:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1560);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  case 1:
                    if ((Bits & ARM::FeatureNEON)) {
                      MI.setOpcode(1568);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 4);
                      if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                  }
                  break;
                }
                break;
              case 1:

                switch (fieldFromInstruction32(insn, 24, 1)) {
                case 0:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1559);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                case 1:
                  if ((Bits & ARM::FeatureNEON)) {
                    MI.setOpcode(1567);
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = 0;
                    tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                    tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                    if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    tmp = fieldFromInstruction32(insn, 16, 5);
                    if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                    return S;
                  }
                }
                break;
              }
              break;
            case 1:

              switch (fieldFromInstruction32(insn, 21, 1)) {
              case 0:

                switch (fieldFromInstruction32(insn, 20, 1)) {
                case 0:

                  switch (fieldFromInstruction32(insn, 24, 1)) {
                  case 0:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1586);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = fieldFromInstruction32(insn, 16, 3);
                      if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      return S;
                    }
                    break;
                  case 1:

                    if ((Bits & ARM::FeatureNEON) &&
                        fieldFromInstruction32(insn, 19, 1) == 1) {
                      MI.setOpcode(1594);
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 12, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 22, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;
                      tmp = 0;
                      tmp |= (fieldFromInstruction32(insn, 0, 4) << 0);
                      tmp |= (fieldFromInstruction32(insn, 5, 1) << 4);
                      if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler::Fail;