Index: i386/i386/mp_machdep.c =================================================================== RCS file: /home/ncvs/src/sys/i386/i386/mp_machdep.c,v retrieving revision 1.128 diff -u -r1.128 mp_machdep.c --- i386/i386/mp_machdep.c 2000/10/20 07:58:00 1.128 +++ i386/i386/mp_machdep.c 2000/11/12 15:03:47 @@ -1262,7 +1262,7 @@ } } - /* Assign interrupts on first 24 intpins on IOAPIC #0 */ + /* Assign interrupts on first 32 intpins on IOAPIC #0 */ for (x = 0; x < nintrs; x++) { int_vector = io_apic_ints[x].dst_apic_int; if (int_vector < APIC_INTMAPSIZE && @@ -1880,7 +1880,7 @@ * initialize all the SMP locks */ -/* critical region around IO APIC, apic_imen */ +/* critical region around IO APIC, imen */ struct simplelock imen_lock; /* critical region around splxx(), cpl, cml, cil, ipending */ Index: i386/i386/mpapic.c =================================================================== RCS file: /home/ncvs/src/sys/i386/i386/mpapic.c,v retrieving revision 1.42 diff -u -r1.42 mpapic.c --- i386/i386/mpapic.c 2000/09/22 23:39:51 1.42 +++ i386/i386/mpapic.c 2000/11/12 15:15:43 @@ -37,6 +37,7 @@ #include #include /* Xspuriousint() */ +#include /* imen */ /* EISA Edge/Level trigger control registers */ #define ELCR0 0x4d0 /* eisa irq 0-7 */ @@ -442,19 +443,18 @@ /* - * Print contents of apic_imen. + * Print contents of imen. */ -extern u_int apic_imen; /* keep apic_imen 'opaque' */ void imen_dump(void) { int x; printf("SMP: enabled INTs: "); - for (x = 0; x < 24; ++x) - if ((apic_imen & (1 << x)) == 0) + for (x = 0; x < 32; ++x) + if ((imen & (1 << x)) == 0) printf("%d, ", x); - printf("apic_imen: 0x%08x\n", apic_imen); + printf("imen: 0x%08x\n", imen); } Index: i386/include/asnames.h =================================================================== RCS file: /home/ncvs/src/sys/i386/include/asnames.h,v retrieving revision 1.48 diff -u -r1.48 asnames.h --- i386/include/asnames.h 2000/10/06 02:20:13 1.48 +++ i386/include/asnames.h 2000/11/12 15:16:57 @@ -150,7 +150,6 @@ #define __udatasel _udatasel #define _alltraps alltraps #define _ap_init ap_init -#define _apic_imen apic_imen #define _apic_isrbit_location apic_isrbit_location #define _apic_pin_trigger apic_pin_trigger #define _arith_invalid arith_invalid Index: i386/include/smp.h =================================================================== RCS file: /home/ncvs/src/sys/i386/include/smp.h,v retrieving revision 1.59 diff -u -r1.59 smp.h --- i386/include/smp.h 2000/09/23 12:18:05 1.59 +++ i386/include/smp.h 2000/11/12 14:21:03 @@ -78,7 +78,7 @@ extern int cpu_num_to_apic_id[]; extern int io_num_to_apic_id[]; extern int apic_id_to_logical[]; -#define APIC_INTMAPSIZE 24 +#define APIC_INTMAPSIZE 32 struct apic_intmapinfo { int ioapic; int int_pin; @@ -143,11 +143,6 @@ void io_apic_set_id __P((int, int)); int io_apic_get_id __P((int)); int ext_int_setup __P((int, int)); - -#if defined(READY) -void clr_io_apic_mask24 __P((int, u_int32_t)); -void set_io_apic_mask24 __P((int, u_int32_t)); -#endif /* READY */ void set_apic_timer __P((int)); int read_apic_timer __P((void)); Index: i386/isa/apic_ipl.h =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/apic_ipl.h,v retrieving revision 1.3 diff -u -r1.3 apic_ipl.h --- i386/isa/apic_ipl.h 1999/08/28 00:44:36 1.3 +++ i386/isa/apic_ipl.h 2000/11/12 14:00:42 @@ -28,7 +28,7 @@ #ifndef _I386_ISA_APIC_IPL_H_ #define _I386_ISA_APIC_IPL_H_ -#define NHWI 24 /* number of h/w interrupts */ -#define HWI_MASK 0x00ffffff /* bits for h/w interrupts */ +#define NHWI 32 /* number of h/w interrupts */ +#define HWI_MASK 0xffffffff /* bits for h/w interrupts */ #endif /* !_I386_ISA_APIC_IPL_H_ */ Index: i386/isa/apic_ipl.s =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/apic_ipl.s,v retrieving revision 1.30 diff -u -r1.30 apic_ipl.s --- i386/isa/apic_ipl.s 2000/09/22 23:40:03 1.30 +++ i386/isa/apic_ipl.s 2000/11/12 15:16:12 @@ -25,7 +25,6 @@ * $FreeBSD: src/sys/i386/isa/apic_ipl.s,v 1.30 2000/09/22 23:40:03 ps Exp $ */ - .data ALIGN_DATA @@ -43,6 +42,7 @@ .long vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7 .long vec8, vec9, vec10, vec11, vec12, vec13, vec14, vec15 .long vec16, vec17, vec18, vec19, vec20, vec21, vec22, vec23 + .long vec24, vec25, vec26, vec27, vec28, vec29, vec30, vec31 /* * Note: @@ -52,19 +52,12 @@ * Accessed by: * INTREN() * INTRDIS() - * MAYBE_MASK_IRQ - * MAYBE_UNMASK_IRQ * imen_dump() */ .p2align 2 /* MUST be 32bit aligned */ - .globl _apic_imen -_apic_imen: - .long HWI_MASK - + .globl _imen +_imen: .long HWI_MASK -/* - * - */ .text SUPERALIGN_TEXT @@ -118,6 +111,14 @@ BUILD_VEC(21) BUILD_VEC(22) BUILD_VEC(23) + BUILD_VEC(24) + BUILD_VEC(25) + BUILD_VEC(26) + BUILD_VEC(27) + BUILD_VEC(28) + BUILD_VEC(29) + BUILD_VEC(30) + BUILD_VEC(31) /****************************************************************************** @@ -144,7 +145,7 @@ /* * (soon to be) MP-safe function to clear ONE INT mask bit. * The passed arg is a 32bit u_int MASK. - * It sets the associated bit in _apic_imen. + * It sets the associated bit in _imen. * It sets the mask bit of the associated IO APIC register. */ ENTRY(INTREN) @@ -154,7 +155,7 @@ movl 8(%esp), %eax /* mask into %eax */ bsfl %eax, %ecx /* get pin index */ - btrl %ecx, _apic_imen /* update _apic_imen */ + btrl %ecx, _imen /* update _imen */ QUALIFY_MASK @@ -176,7 +177,7 @@ /* * (soon to be) MP-safe function to set ONE INT mask bit. * The passed arg is a 32bit u_int MASK. - * It clears the associated bit in _apic_imen. + * It clears the associated bit in _imen. * It clears the mask bit of the associated IO APIC register. */ ENTRY(INTRDIS) @@ -186,7 +187,7 @@ movl 8(%esp), %eax /* mask into %eax */ bsfl %eax, %ecx /* get pin index */ - btsl %ecx, _apic_imen /* update _apic_imen */ + btsl %ecx, _imen /* update _imen */ QUALIFY_MASK @@ -204,148 +205,6 @@ IMASK_UNLOCK /* exit critical reg */ popfl /* restore old state of EI flag */ ret - - -/****************************************************************************** - * - */ - - -/* - * void write_ioapic_mask(int apic, u_int mask); - */ - -#define _INT_MASK 0x00010000 -#define _PIN_MASK 0x00ffffff - -#define _OLD_ESI 0(%esp) -#define _OLD_EBX 4(%esp) -#define _RETADDR 8(%esp) -#define _APIC 12(%esp) -#define _MASK 16(%esp) - - ALIGN_TEXT -write_ioapic_mask: - pushl %ebx /* scratch */ - pushl %esi /* scratch */ - - movl _apic_imen, %ebx - xorl _MASK, %ebx /* %ebx = _apic_imen ^ mask */ - andl $_PIN_MASK, %ebx /* %ebx = _apic_imen & 0x00ffffff */ - jz all_done /* no change, return */ - - movl _APIC, %esi /* APIC # */ - movl _ioapic, %ecx - movl (%ecx,%esi,4), %esi /* %esi holds APIC base address */ - -next_loop: /* %ebx = diffs, %esi = APIC base */ - bsfl %ebx, %ecx /* %ecx = index if 1st/next set bit */ - jz all_done - - btrl %ecx, %ebx /* clear this bit in diffs */ - leal 16(,%ecx,2), %edx /* calculate register index */ - - movl %edx, (%esi) /* write the target register index */ - movl 16(%esi), %eax /* read the target register data */ - - btl %ecx, _MASK /* test for mask or unmask */ - jnc clear /* bit is clear */ - orl $_INT_MASK, %eax /* set mask bit */ - jmp write -clear: andl $~_INT_MASK, %eax /* clear mask bit */ - -write: movl %eax, 16(%esi) /* write the APIC register data */ - - jmp next_loop /* try another pass */ - -all_done: - popl %esi - popl %ebx - ret - -#undef _OLD_ESI -#undef _OLD_EBX -#undef _RETADDR -#undef _APIC -#undef _MASK - -#undef _PIN_MASK -#undef _INT_MASK - -#ifdef oldcode - -_INTREN: - movl _apic_imen, %eax - notl %eax /* mask = ~mask */ - andl _apic_imen, %eax /* %eax = _apic_imen & ~mask */ - - pushl %eax /* new (future) _apic_imen value */ - pushl $0 /* APIC# arg */ - call write_ioapic_mask /* modify the APIC registers */ - - addl $4, %esp /* remove APIC# arg from stack */ - popl _apic_imen /* _apic_imen |= mask */ - ret - -_INTRDIS: - movl _apic_imen, %eax - orl 4(%esp), %eax /* %eax = _apic_imen | mask */ - - pushl %eax /* new (future) _apic_imen value */ - pushl $0 /* APIC# arg */ - call write_ioapic_mask /* modify the APIC registers */ - - addl $4, %esp /* remove APIC# arg from stack */ - popl _apic_imen /* _apic_imen |= mask */ - ret - -#endif /* oldcode */ - - -#ifdef ready - -/* - * u_int read_io_apic_mask(int apic); - */ - ALIGN_TEXT -read_io_apic_mask: - ret - -/* - * Set INT mask bit for each bit set in 'mask'. - * Ignore INT mask bit for all others. - * - * void set_io_apic_mask(apic, u_int32_t bits); - */ - ALIGN_TEXT -set_io_apic_mask: - ret - -/* - * void set_ioapic_maskbit(int apic, int bit); - */ - ALIGN_TEXT -set_ioapic_maskbit: - ret - -/* - * Clear INT mask bit for each bit set in 'mask'. - * Ignore INT mask bit for all others. - * - * void clr_io_apic_mask(int apic, u_int32_t bits); - */ - ALIGN_TEXT -clr_io_apic_mask: - ret - -/* - * void clr_ioapic_maskbit(int apic, int bit); - */ - ALIGN_TEXT -clr_ioapic_maskbit: - ret - -#endif /** ready */ /****************************************************************************** * Index: i386/isa/apic_vector.s =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/apic_vector.s,v retrieving revision 1.57 diff -u -r1.57 apic_vector.s --- i386/isa/apic_vector.s 2000/10/06 02:20:17 1.57 +++ i386/isa/apic_vector.s 2000/11/12 15:23:49 @@ -66,9 +66,9 @@ #define MASK_IRQ(irq_num) \ IMASK_LOCK ; /* into critical reg */ \ - testl $IRQ_BIT(irq_num), _apic_imen ; \ + testl $IRQ_BIT(irq_num), _imen ; \ jne 7f ; /* masked, don't mask */ \ - orl $IRQ_BIT(irq_num), _apic_imen ; /* set the mask bit */ \ + orl $IRQ_BIT(irq_num), _imen ; /* set the mask bit */ \ movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \ movl REDIRIDX(irq_num), %eax ; /* get the index */ \ movl %eax, (%ecx) ; /* write the index */ \ @@ -114,16 +114,16 @@ */ #define UNMASK_IRQ(irq_num) \ IMASK_LOCK ; /* into critical reg */ \ - testl $IRQ_BIT(irq_num), _apic_imen ; \ + testl $IRQ_BIT(irq_num), _imen ; \ je 7f ; /* bit clear, not masked */ \ - andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \ - movl IOAPICADDR(irq_num),%ecx ; /* ioapic addr */ \ + andl $~IRQ_BIT(irq_num), _imen ; /* clear mask bit */ \ + movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \ movl REDIRIDX(irq_num), %eax ; /* get the index */ \ - movl %eax,(%ecx) ; /* write the index */ \ - movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ - andl $~IOART_INTMASK,%eax ; /* clear the mask */ \ - movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ -7: ; \ + movl %eax, (%ecx) ; /* write the index */ \ + movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \ + andl $~IOART_INTMASK, %eax ; /* clear the mask */ \ + movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \ +7: ; /* already unmasked */ \ IMASK_UNLOCK #ifdef APIC_INTR_DIAGNOSTIC @@ -379,7 +379,7 @@ lock btrl %eax, CNAME(resched_cpus) jnc 2f - orl $AST_PENDING+AST_RESCHED,_astpending + orl $AST_PENDING+AST_RESCHED, _astpending lock incl CNAME(want_resched_cnt) 2: @@ -565,6 +565,14 @@ FAST_INTR(21,fastintr21) FAST_INTR(22,fastintr22) FAST_INTR(23,fastintr23) + FAST_INTR(24,fastintr24) + FAST_INTR(25,fastintr25) + FAST_INTR(26,fastintr26) + FAST_INTR(27,fastintr27) + FAST_INTR(28,fastintr28) + FAST_INTR(29,fastintr29) + FAST_INTR(30,fastintr30) + FAST_INTR(31,fastintr31) #define CLKINTR_PENDING movl $1,CNAME(clkintr_pending) /* Threaded interrupts */ INTR(0,intr0, CLKINTR_PENDING) @@ -591,6 +599,14 @@ INTR(21,intr21,) INTR(22,intr22,) INTR(23,intr23,) + INTR(24,intr24,) + INTR(25,intr25,) + INTR(26,intr26,) + INTR(27,intr27,) + INTR(28,intr28,) + INTR(29,intr29,) + INTR(30,intr30,) + INTR(31,intr31,) MCOUNT_LABEL(eintr) /* @@ -667,8 +683,6 @@ .long 0 CNAME(cpustop_restartfunc): .long 0 - - .globl _apic_pin_trigger _apic_pin_trigger: Index: i386/isa/icu.h =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/icu.h,v retrieving revision 1.18 diff -u -r1.18 icu.h --- i386/isa/icu.h 1999/12/26 12:43:47 1.18 +++ i386/isa/icu.h 2000/11/12 15:16:46 @@ -47,8 +47,6 @@ #ifndef LOCORE -#ifdef APIC_IO - /* #define MP_SAFE * Note: @@ -61,40 +59,7 @@ void INTREN __P((u_int)); void INTRDIS __P((u_int)); -#else /* APIC_IO */ - -/* - * Interrupt "level" mechanism variables, masks, and macros - */ extern unsigned imen; /* interrupt mask enable */ - -#define INTREN(s) (imen &= ~(s), SET_ICUS()) -#define INTRDIS(s) (imen |= (s), SET_ICUS()) - -#if 0 -#ifdef PC98 -#define SET_ICUS() (outb(IO_ICU1 + 2, imen), outb(IU_ICU2 + 2, imen >> 8)) -#define INTRGET() ((inb(IO_ICU2) << 8 | inb(IO_ICU1)) & 0xffff) -#else /* IBM-PC */ -#define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IU_ICU2 + 1, imen >> 8)) -#define INTRGET() ((inb(IO_ICU2) << 8 | inb(IO_ICU1)) & 0xffff) -#endif /* PC98 */ -#else -/* - * XXX - IO_ICU* are defined in isa.h, not icu.h, and nothing much bothers to - * include isa.h, while too many things include icu.h. - */ -#ifdef PC98 -#define SET_ICUS() (outb(0x02, imen), outb(0x0a, imen >> 8)) -/* XXX is this correct? */ -#define INTRGET() ((inb(0x0a) << 8 | inb(0x02)) & 0xffff) -#else -#define SET_ICUS() (outb(0x21, imen), outb(0xa1, imen >> 8)) -#define INTRGET() ((inb(0xa1) << 8 | inb(0x21)) & 0xffff) -#endif -#endif - -#endif /* APIC_IO */ #endif /* LOCORE */ Index: i386/isa/icu_ipl.s =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/icu_ipl.s,v retrieving revision 1.7 diff -u -r1.7 icu_ipl.s --- i386/isa/icu_ipl.s 2000/09/07 01:32:47 1.7 +++ i386/isa/icu_ipl.s 2000/11/12 15:38:12 @@ -47,10 +47,6 @@ .globl _imen _imen: .long HWI_MASK - -/* - * - */ .text SUPERALIGN_TEXT @@ -109,3 +105,28 @@ BUILD_VEC(13) BUILD_VEC(14) BUILD_VEC(15) + +#ifdef PC98 +#define MASK_OFFSET 2 +#else +#define MASK_OFFSET 1 +#endif + +ENTRY(INTREN) + movl 4(%esp), %eax + notl %eax + andl %eax, imen + movl imen, %eax + outb %al, $(IO_ICU1 + MASK_OFFSET) + shrl $8, %eax + outb %al, $(IO_ICU2 + MASK_OFFSET) + ret + +ENTRY(INTRDIS) + movl 4(%esp), %eax + orl %eax, imen + movl imen, %eax + outb %al, $(IO_ICU1 + MASK_OFFSET) + shrl $8, %eax + outb %al, $(IO_ICU2 + MASK_OFFSET) + ret Index: i386/isa/icu_vector.s =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/icu_vector.s,v retrieving revision 1.21 diff -u -r1.21 icu_vector.s --- i386/isa/icu_vector.s 2000/10/06 02:20:18 1.21 +++ i386/isa/icu_vector.s 2000/11/12 14:00:12 @@ -71,37 +71,6 @@ MEXITCOUNT ; \ jmp doreti_next -#if 0 -; \ - ALIGN_TEXT ; \ -2: ; \ - cmpb $3,_intr_nesting_level ; /* is there enough stack? */ \ - jae 1b ; /* no, return */ \ - movl _cpl,%eax ; \ - /* XXX next line is probably unnecessary now. */ \ - movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \ - incb _intr_nesting_level ; /* ... really limit it ... */ \ - sti ; /* ... to do this as early as possible */ \ - MAYBE_POPL_ES ; /* discard most of thin frame ... */ \ - popl %fs ; \ - popl %ecx ; /* ... original %ds ... */ \ - popl %edx ; \ - xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \ - pushal ; /* build fat frame (grrr) ... */ \ - pushl %ecx ; /* ... actually %ds ... */ \ - pushl %es ; \ - pushl %fs ; \ - mov $KDSEL,%ax ; \ - mov %ax,%es ; \ - mov %ax,%fs ; \ - movl (3+8+0)*4(%esp),%ecx ; /* ... %ecx from thin frame ... */ \ - movl %ecx,(3+6)*4(%esp) ; /* ... to fat frame ... */ \ - movl (3+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \ - subl $4,%esp ; /* junk for unit number */ \ - MEXITCOUNT ; \ - jmp _doreti -#endif - /* * Slow, threaded interrupts. * Index: i386/isa/intr_machdep.h =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/intr_machdep.h,v retrieving revision 1.24 diff -u -r1.24 intr_machdep.h --- i386/isa/intr_machdep.h 2000/10/25 05:19:35 1.24 +++ i386/isa/intr_machdep.h 2000/11/12 13:54:01 @@ -168,10 +168,16 @@ IDTVEC(fastintr16), IDTVEC(fastintr17), IDTVEC(fastintr18), IDTVEC(fastintr19), IDTVEC(fastintr20), IDTVEC(fastintr21), - IDTVEC(fastintr22), IDTVEC(fastintr23); + IDTVEC(fastintr22), IDTVEC(fastintr23), + IDTVEC(fastintr24), IDTVEC(fastintr25), + IDTVEC(fastintr26), IDTVEC(fastintr27), + IDTVEC(fastintr28), IDTVEC(fastintr29), + IDTVEC(fastintr30), IDTVEC(fastintr31); inthand_t IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19), - IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23); + IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23), + IDTVEC(intr24), IDTVEC(intr25), IDTVEC(intr26), IDTVEC(intr27), + IDTVEC(intr28), IDTVEC(intr29), IDTVEC(intr30), IDTVEC(intr31); inthand_t Xinvltlb, /* TLB shootdowns */ Index: i386/isa/ithread.c =================================================================== RCS file: /home/ncvs/src/sys/i386/isa/ithread.c,v retrieving revision 1.9 diff -u -r1.9 ithread.c --- i386/isa/ithread.c 2000/11/15 22:03:26 1.9 +++ i386/isa/ithread.c 2000/11/21 05:20:38 @@ -33,8 +33,6 @@ #include "opt_auto_eoi.h" -#include "isa.h" - #include #include #include /* change this name XXX */ @@ -56,34 +54,12 @@ #include #include -#if defined(APIC_IO) -#include -#include /** FAST_HI */ -#include -#endif /* APIC_IO */ -#ifdef PC98 -#include -#include -#include -#else -#include -#endif #include -#if NISA > 0 #include -#endif #include #include -#ifdef APIC_IO -#include -#endif -#include "mca.h" -#if NMCA > 0 -#include -#endif - #include #include #include @@ -226,13 +202,8 @@ INTREN (1 << me->irq); /* reset the mask bit */ me->it_proc->p_stat = SWAIT; /* we're idle */ -#ifdef APIC_IO - CTR1(KTR_INTR, "ithd_loop pid %d: done", - me->it_proc->p_pid); -#else CTR2(KTR_INTR, "ithd_loop pid %d: done, imen=%x", me->it_proc->p_pid, imen); -#endif mi_switch(); CTR1(KTR_INTR, "ithd_loop pid %d: resumed", me->it_proc->p_pid);