under construction CPU Identification routine

FreeBSD has powerful CPU identification and initialization routines. All of non-Intel CPUs are automatically detected, and are initialized if necessary.

O Supported CPU: it might not be all.

O Contents

Identification
O Identify 486+
O Identify NexGen 586
O Check availability of cpuid instruction
O Check Cyrix/IBM CPU
O Identify IBM Blue Lightning CPU
O Identify CPU with cpuid instrcution
O Identify Cyrix CPU with device ID registers
Initializatoin
O Initialize IBM Blue Lightning CPU
O Initialize Cyrix 486 series
O Initialize Cyrix 5x86
O Initialize Cyrix 6x86
Kernel configuraiton time options
O IBM Blue Lightning CPU
O Cyrix 486 CPU
O Cyrix 5x86
O Cyrix 6x86

Identification

O Identify 486+

i80486 and newer CPUs support the aligment check. If bit 18 (AC) of EFLAGS can not be toggled, we have i80386 or NexGen 586 CPU. If AC is writable, then check whether CPU supports cpuid instruction.

O Identify NexGen 586

The NexGen 586 does not have AC bit of EFLAGS because it had designed the chip to be an 80386 clone. NexGen 586 can be distinguished from i80386 by following code: 

        movl    $0x5555, %eax
        xorl    %edx, %edx
        movl    $2, %ecx
        clc
        divl    %ecx
        jz      you_have_NexGen_586
        jmp     you_have_i80386

O Check availability of cpuid instruction

Once 486 or higher CPU is detected, we check ID bit of EFLAGS. If ID bit can be toggled, the CPU support cpuid instruction. If ID bit is readonly, we may have earlier version of i80486 or Cyrix/IBM CPU (M1 and below). On Cyrix M2, CPUID bit is enabled at reset cycle, though it is disabled on M1 and lower CPU.

O Identify Cyrix/IBM CPU

If CPU does not support cpuid, we have earlier version of i80486, Cyrix CPU (M1 or lower) or IBM Blue Lightning 486 CPU. Cyrix CPUs and IBM Blue Lightning 486 CPU can be distinguished from i80486 by following code: 

        movl    $0x5555, %eax
        xorl    %edx, %edx
        movl    $2, %ecx
        clc
        divl    %ecx
        jnc     you_have_Cyrix_Or_Blue_Lightning
        jmp     you_have_i80486
Note: Cyrix M2 support cpuid instruction, and this routine is not executed on M2.

O Identify IBM Blue Lightning CPU

It is difficult to distinguish IBM Blue Lightning CPU from Cyrix CPU. The behavior of both CPU is very similar to each other. The deference is that IBM Blue Lightning CPU supports MSR but Cyrix 486, 5x86 and 6x86 do not support it. This means that wrmsr instruction cause invalid opcode fault on Cyrix 486, 5x86 and 6x86, but does not on IBM Blue Lightning CPU. To detect invalid opcode by wrmsr, the following handler is prepared: 

        static  volatile u_int trap_by_wrmsr;

        inthand_t       bluetrap;
        asm
        ("
                .text
        _bluetrap:
                ss
                movl    $0xa8c1d, _trap_by_wrmsr
                addl    $2, (%esp)
                iret
        ");
If we have Cyrix 486, 5x86 or 6x86, the variable trap_by_wrmsr will be change by this handler. Once Cyrix CPU is detected by this method, we will check device ID register to distinguish it.

O Identify CPU with cpuid instruction

The cpuid instruction with EAX=0 provides the vendor string. The cpuid isntruction with EAX=1 provides the cpu id signature which show the model of CPU (iPentium class, iPentium Pro class and so on) and cpu feature. If vendor string show that we have Cyrix CPU, will check device ID register.

If the CPU model is lower than 4, we may have i80486 class CPU including AMD 5x86. If it is 5, we have iPentium or iPentium OverDrive Processor. If it is 6, we have iPentium Pro Processor.

O Identify Cyrix CPU with device ID registers

Firstly, we check whether CPU has device ID register. If bit 4 fo CCR3 (MAPEN0) can be toggled, the CPU has device ID registers, and we can distinguish CPU model with it. If device ID registers are not available, we have Cyrix 486S or earlier version of 486SLC/DLC. If bit 2 of CCR2 (LOCK_NW) can be toggled, we have Cyrix 486S (A step), otherwise we have Cyrix 486SLC/DLC. After getting CPU model, the variable cpu will be adjusted with the result.

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Initialization

O Initialize IBM Blue Lightning CPU

The function init_bluelightning() initialize wrmsr as follows:

If CPU_BLUELIGHTNING_FPU_OP_CACHE is set, FP operand cache is enabled. Otherwise it is disabled. FP operand cache works only with Cyrix's FPU. If CPU_BLUELIGHTNING_3X is set and CPU supports triple clock mode, triple clock mode is enabled. Otherwise, CPU runs in double clock mode. The address in rages from 0 to 640KB and from 1 to 13MB is cacheable.

O Initialize Cyrix 486 series

O Initialize Cyrix 5x86

O Initialize Cyrix 6x86

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Kernel Configuration time options

O IBM Blue Lightning CPU

options "CPU_BLUELIGHTNING_FPU_OP_CACHE"
CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM BlueLightning CPU. It works only with Cyrix FPU, and this option should not be used with Intel FPU.
options "CPU_BLUELIGHTNING_3X"
CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning CPU if CPU supports it. The default is double-clock mode on BlueLightning CPU box.

O Cyrix 486 CPU

options "CYRIX_CACHE_WORKS"
CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache flush at hold state.
options "CYRIX_CACHE_REALLY_WORKS"
CYRIX_CACHE_REALLY_WORKS enables CPU cache on Cyrix 486 CPUs without cache flush at hold state.

O Cyrix 5x86

options "CPU_BTB_EN"
CPU_BTB_EN enables branch target buffer on Cyrix 5x86. This option may crash your system bacause of CPU bug.
options "CPU_DISABLE_5X86_LSSER"
CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables reorder). This option should not be used if you use memory mapped I/O device(s).
options "CPU_FASTER_5X86_FPU"
CPU_FASTER_5X86_FPU enables faster FPU exception handler.
options "CPU_IORT=0"
CPU_IORT defines I/O clock delay time. Default vaules of I/O clock delay time on Cyrix 5x86 is 0 (no clock delay). If I/O clock delay is not zero on Cyrix 5x86, your system may become unstable because of CPU bug.
options "CPU_LOOP_EN"
CPU_LOOP_EN prevents flushing the prefetch buffer if the destination of a jump is already present in the prefetch buffer on Cyrix 5x86. This option may crash your system because of CPU bug.
options "CPU_RSTK_EN"
CPU_RSTK_EN enables return stack on Cyrix 5x86. This option may crash your system because of CPU bug.
options "CPU_SUSP_HLT"
CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU enters suspend mode following execution of HALT instruction.

O Cyrix 6x86

options "CPU_SUSP_HLT"
CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU enters suspend mode following execution of HALT instruction.
options "CPU_IORT=7"
CPU_IORT defines I/O clock delay time. Default vaules of I/O clock delay time on Cyrix 6x86 is 7 (no clock delay).
options "CYRIX_CACHE_REALLY_WORKS"
CYRIX_CACHE_REALLY_WORKS enables write-back CPU cache on Cyrix 6x86 whose revision < 2.7.

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