Index: aic7xxx/aic79xx.h
===================================================================
RCS file: /host/cvs/usr/cvs/src/sys/dev/aic7xxx/aic79xx.h,v
retrieving revision 1.24
diff -u -r1.24 aic79xx.h
--- aic7xxx/aic79xx.h	6 Jan 2005 01:42:25 -0000	1.24
+++ aic7xxx/aic79xx.h	19 Jan 2007 21:52:33 -0000
@@ -1244,6 +1244,9 @@
 	/* PCI cacheline size. */
 	u_int			  pci_cachesize;
 
+	/* PCI-X capability offset. */
+	int			  pcix_ptr;
+
 	/* IO Cell Parameters */
 	uint8_t			  iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
 
Index: aic7xxx/aic79xx_pci.c
===================================================================
RCS file: /host/cvs/usr/cvs/src/sys/dev/aic7xxx/aic79xx_pci.c,v
retrieving revision 1.24
diff -u -r1.24 aic79xx_pci.c
--- aic7xxx/aic79xx_pci.c	4 Dec 2005 02:12:40 -0000	1.24
+++ aic7xxx/aic79xx_pci.c	19 Jan 2007 21:52:33 -0000
@@ -342,7 +342,12 @@
 	error = entry->setup(ahd);
 	if (error != 0)
 		return (error);
-	
+
+	/*
+	 * Find the PCI-X cap pointer.  If we don't find it,
+	 * pcix_ptr will be 0.
+	 */
+	pci_find_extcap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr);
 	devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 	if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 		ahd->chip |= AHD_PCI;
@@ -350,6 +355,8 @@
 		ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 	} else {
 		ahd->chip |= AHD_PCIX;
+		if (ahd->pcix_ptr == 0)
+			return (ENXIO);
 	}
 	ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 
@@ -867,16 +874,16 @@
 	uint8_t		sg_split_status1[2];
 	ahd_mode_state	saved_modes;
 	u_int		i;
-	uint16_t	pcix_status;
+	uint32_t	pcix_status;
 
 	/*
 	 * Check for splits in all modes.  Modes 0 and 1
 	 * additionally have SG engine splits to look at.
 	 */
-	pcix_status = aic_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
-					  /*bytes*/2);
+	pcix_status = aic_pci_read_config(ahd->dev_softc,
+	    ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4);
 	printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
-	       ahd_name(ahd), pcix_status);
+	       ahd_name(ahd), pcix_status >> 16);
 	saved_modes = ahd_save_modes(ahd);
 	for (i = 0; i < 4; i++) {
 		ahd_set_modes(ahd, i, i);
@@ -922,8 +929,8 @@
 	/*
 	 * Clear PCI-X status bits.
 	 */
-	aic_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
-			     pcix_status, /*bytes*/2);
+	aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS,
+			     pcix_status, /*bytes*/4);
 	ahd_outb(ahd, CLRINT, CLRSPLTINT);
 	ahd_restore_modes(ahd, saved_modes);
 }
Index: pci/pcireg.h
===================================================================
RCS file: /host/cvs/usr/cvs/src/sys/dev/pci/pcireg.h,v
retrieving revision 1.56
diff -u -r1.56 pcireg.h
--- pci/pcireg.h	16 Jan 2007 17:04:42 -0000	1.56
+++ pci/pcireg.h	19 Jan 2007 21:53:56 -0000
@@ -413,21 +413,77 @@
 #define	PCIR_MSI_PENDING	0x14
 
 /* PCI-X definitions */
-#define	PCIXR_COMMAND	0x96
-#define	PCIXR_DEVADDR	0x98
-#define	PCIXM_DEVADDR_FNUM	0x0003	/* Function Number */
-#define	PCIXM_DEVADDR_DNUM	0x00F8	/* Device Number */
-#define	PCIXM_DEVADDR_BNUM	0xFF00	/* Bus Number */
-#define	PCIXR_STATUS	0x9A
-#define	PCIXM_STATUS_64BIT	0x0001	/* Active 64bit connection to device. */
-#define	PCIXM_STATUS_133CAP	0x0002	/* Device is 133MHz capable */
-#define	PCIXM_STATUS_SCDISC	0x0004	/* Split Completion Discarded */
-#define	PCIXM_STATUS_UNEXPSC	0x0008	/* Unexpected Split Completion */
-#define	PCIXM_STATUS_CMPLEXDEV	0x0010	/* Device Complexity (set == bridge) */
-#define	PCIXM_STATUS_MAXMRDBC	0x0060	/* Maximum Burst Read Count */
-#define	PCIXM_STATUS_MAXSPLITS	0x0380	/* Maximum Split Transactions */
-#define	PCIXM_STATUS_MAXCRDS	0x1C00	/* Maximum Cumulative Read Size */
-#define	PCIXM_STATUS_RCVDSCEM	0x2000	/* Received a Split Comp w/Error msg */
+
+/* For header type 0 devices */
+#define	PCIXR_COMMAND		0x2
+#define	PCIXM_COMMAND_DPERR_E		0x0001	/* Data Parity Error Recovery */
+#define	PCIXM_COMMAND_ERO		0x0002	/* Enable Relaxed Ordering */
+#define	PCIXM_COMMAND_MAX_READ		0x000c	/* Maximum Burst Read Count */
+#define	PCIXM_COMMAND_MAX_READ_512	0x0000
+#define	PCIXM_COMMAND_MAX_READ_1024	0x0004
+#define	PCIXM_COMMAND_MAX_READ_2048	0x0008
+#define	PCIXM_COMMAND_MAX_READ_4096	0x000c
+#define	PCIXM_COMMAND_MAX_SPLITS 	0x0070	/* Maximum Split Transactions */
+#define	PCIXM_COMMAND_MAX_SPLITS_1	0x0000
+#define	PCIXM_COMMAND_MAX_SPLITS_2	0x0010
+#define	PCIXM_COMMAND_MAX_SPLITS_3	0x0020
+#define	PCIXM_COMMAND_MAX_SPLITS_4	0x0030
+#define	PCIXM_COMMAND_MAX_SPLITS_8	0x0040
+#define	PCIXM_COMMAND_MAX_SPLITS_12	0x0050
+#define	PCIXM_COMMAND_MAX_SPLITS_16	0x0060
+#define	PCIXM_COMMAND_MAX_SPLITS_32	0x0070
+#define	PCIXM_COMMAND_VERSION		0x3000
+#define	PCIXR_STATUS		0x4
+#define	PCIXM_STATUS_DEVFN		0x000000FF
+#define	PCIXM_STATUS_BUS		0x0000FF00
+#define	PCIXM_STATUS_64BIT		0x00010000
+#define	PCIXM_STATUS_133CAP		0x00020000
+#define	PCIXM_STATUS_SC_DISCARDED	0x00040000
+#define	PCIXM_STATUS_UNEXP_SC		0x00080000
+#define	PCIXM_STATUS_COMPLEX_DEV	0x00100000
+#define	PCIXM_STATUS_MAX_READ		0x00600000
+#define	PCIXM_STATUS_MAX_READ_512	0x00000000
+#define	PCIXM_STATUS_MAX_READ_1024	0x00200000
+#define	PCIXM_STATUS_MAX_READ_2048	0x00400000
+#define	PCIXM_STATUS_MAX_READ_4096	0x00600000
+#define	PCIXM_STATUS_MAX_SPLITS		0x03800000
+#define	PCIXM_STATUS_MAX_SPLITS_1	0x00000000
+#define	PCIXM_STATUS_MAX_SPLITS_2	0x00800000
+#define	PCIXM_STATUS_MAX_SPLITS_3	0x01000000
+#define	PCIXM_STATUS_MAX_SPLITS_4	0x01800000
+#define	PCIXM_STATUS_MAX_SPLITS_8	0x02000000
+#define	PCIXM_STATUS_MAX_SPLITS_12	0x02800000
+#define	PCIXM_STATUS_MAX_SPLITS_16	0x03000000
+#define	PCIXM_STATUS_MAX_SPLITS_32	0x03800000
+#define	PCIXM_STATUS_MAX_CUM_READ	0x1C000000
+#define	PCIXM_STATUS_RCVD_SC_ERR	0x20000000
+#define	PCIXM_STATUS_266CAP		0x40000000
+#define	PCIXM_STATUS_533CAP		0x80000000
+
+/* For header type 1 devices (PCI-X bridges) */
+#define	PCIXR_SEC_STATUS	0x2
+#define	PCIXM_SEC_STATUS_64BIT		0x0001
+#define	PCIXM_SEC_STATUS_133CAP		0x0002
+#define	PCIXM_SEC_STATUS_SC_DISC	0x0004
+#define	PCIXM_SEC_STATUS_UNEXP_SC	0x0008
+#define	PCIXM_SEC_STATUS_SC_OVERRUN	0x0010
+#define	PCIXM_SEC_STATUS_SR_DELAYED	0x0020
+#define	PCIXM_SEC_STATUS_BUS_MODE	0x03c0
+#define	PCIXM_SEC_STATUS_VERSION	0x3000
+#define	PCIXM_SEC_STATUS_266CAP		0x4000
+#define	PCIXM_SEC_STATUS_533CAP		0x8000
+#define	PCIXR_BRIDGE_STATUS	0x4
+#define	PCIXM_BRIDGE_STATUS_DEVFN	0x000000FF
+#define	PCIXM_BRIDGE_STATUS_BUS		0x0000FF00
+#define	PCIXM_BRIDGE_STATUS_64BIT	0x00010000
+#define	PCIXM_BRIDGE_STATUS_133CAP	0x00020000
+#define	PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
+#define	PCIXM_BRIDGE_STATUS_UNEXP_SC	0x00080000
+#define	PCIXM_BRIDGE_STATUS_SC_OVERRUN	0x00100000
+#define	PCIXM_BRIDGE_STATUS_SR_DELAYED	0x00200000
+#define	PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
+#define	PCIXM_BRIDGE_STATUS_266CAP	0x40000000
+#define	PCIXM_BRIDGE_STATUS_533CAP	0x80000000
 
 /* HT (HyperTransport) Capability definitions */
 #define	PCIR_HT_COMMAND		0x2