Index: fixup_pci.c
===================================================================
RCS file: /usr/cvs/src/sys/dev/pci/fixup_pci.c,v
retrieving revision 1.6
diff -u -r1.6 fixup_pci.c
--- fixup_pci.c	30 May 2004 17:57:41 -0000	1.6
+++ fixup_pci.c	19 May 2006 15:14:26 -0000
@@ -51,6 +51,7 @@
 
 static int	fixup_pci_probe(device_t dev);
 static void	fixwsc_natoma(device_t dev);
+static void	fixc1_nforce2(device_t dev);
 
 static device_method_t fixup_pci_methods[] = {
     /* Device interface */
@@ -76,6 +77,9 @@
     case 0x12378086:		/* Intel 82440FX (Natoma) */
 	fixwsc_natoma(dev);
 	break;
+    case 0x01e010de:		/* nVidia nForce2 */
+	fixc1_nforce2(dev);
+	break;
     }
     return(ENXIO);
 }
@@ -100,3 +104,37 @@
     }
 #endif
 }
+
+/*
+ * Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work
+ * around a hang that is triggered when the CPU generates a very fast
+ * CONNECT/HALT cycle sequence.  Specifically, the hang can result in
+ * the lapic timer being stopped.
+ *
+ * This requires changing the value for config register at offset 0x6c
+ * for the Host-PCI bridge at bus/dev/function 0/0/0:
+ *
+ * Chip	Current Value	New Value
+ * ----	----------	----------
+ * C17	0x1F0FFF01	0x1F01FF01
+ * C18D	0x9F0FFF01	0x9F01FF01
+ *
+ * We do this by always clearing the bits in 0x000e0000.
+ *
+ * See also: http://lkml.org/lkml/2004/5/3/157
+ */
+static void
+fixc1_nforce2(device_t dev)
+{
+	uint32_t val;
+
+	if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 &&
+	    pci_get_function(dev) == 0) {
+		val = pci_read_config(dev, 0x6c, 4);
+		if (val & 0x000e0000) {
+			printf("Correcting nForce2 C1 CPU disconnect hangs\n");
+			val &= ~0x000e0000;
+			pci_write_config(dev, 0x6c, val, 4);
+		}
+	}
+}