Index: amd64/amd64/local_apic.c
===================================================================
RCS file: /usr/cvs/src/sys/amd64/amd64/local_apic.c,v
retrieving revision 1.28
diff -u -r1.28 local_apic.c
--- amd64/amd64/local_apic.c	6 Sep 2006 22:05:34 -0000	1.28
+++ amd64/amd64/local_apic.c	7 Sep 2006 14:50:46 -0000
@@ -733,6 +733,7 @@
 	KASSERT(ioint_handlers[vector / 32] != NULL,
 	    ("No ISR handler for vector %u", vector));
 	setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
+	smp_rendezvous(NULL, NULL, NULL, NULL);
 }
 
 /* Release an APIC vector when it's no longer in use. */
Index: amd64/amd64/mp_machdep.c
===================================================================
RCS file: /usr/cvs/src/sys/amd64/amd64/mp_machdep.c,v
retrieving revision 1.276
diff -u -r1.276 mp_machdep.c
--- amd64/amd64/mp_machdep.c	16 May 2006 14:32:16 -0000	1.276
+++ amd64/amd64/mp_machdep.c	11 Sep 2006 19:59:28 -0000
@@ -342,7 +342,10 @@
 	setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
 	setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
 	setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
-	
+
+	/* Install an inter-CPU IPI for cache invalidation. */
+	setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
+
 	/* Install an inter-CPU IPI for all-CPU rendezvous */
 	setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
 
Index: i386/i386/local_apic.c
===================================================================
RCS file: /usr/cvs/src/sys/i386/i386/local_apic.c,v
retrieving revision 1.30
diff -u -r1.30 local_apic.c
--- i386/i386/local_apic.c	6 Sep 2006 22:05:33 -0000	1.30
+++ i386/i386/local_apic.c	11 Sep 2006 20:00:32 -0000
@@ -736,6 +736,7 @@
 	    ("No ISR handler for vector %u", vector));
 	setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
 	    GSEL(GCODE_SEL, SEL_KPL));
+	smp_rendezvous(NULL, NULL, NULL, NULL);
 }
 
 /* Release an APIC vector when it's no longer in use. */
@@ -797,6 +798,74 @@
 		}
 	}
 }
+
+static void
+dump_mask(const char *prefix, uint32_t v, int base)
+{
+	int i, first;
+
+	first = 1;
+	for (i = 0; i < 32; i++)
+		if (v & (1 << i)) {
+			if (first) {
+				db_printf("%s:", prefix);
+				first = 0;
+			}
+			db_printf(" %02x", base + i);
+		}
+	if (!first)
+		db_printf("\n");
+}
+
+/* Show info from the lapic regs for this CPU. */
+DB_SHOW_COMMAND(lapic, db_show_lapic)
+{
+	uint32_t v;
+
+	db_printf("lapic ID = %d\n", lapic_id());
+	v = lapic->version;
+	db_printf("version  = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
+	    v & 0xf);
+	db_printf("max LVT  = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
+	v = lapic->svr;
+	db_printf("SVR      = %02x (%s)\n", v & APIC_SVR_VECTOR,
+	    v & APIC_SVR_ENABLE ? "enabled" : "disabled");
+	db_printf("TPR      = %02x\n", lapic->tpr);
+
+#define dump_field(prefix, index)					\
+	dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index,	\
+	    index * 32)
+
+	db_printf("In-service Interrupts:\n");
+	dump_field(isr, 0);
+	dump_field(isr, 1);
+	dump_field(isr, 2);
+	dump_field(isr, 3);
+	dump_field(isr, 4);
+	dump_field(isr, 5);
+	dump_field(isr, 6);
+	dump_field(isr, 7);
+
+	db_printf("TMR Interrupts:\n");
+	dump_field(tmr, 0);
+	dump_field(tmr, 1);
+	dump_field(tmr, 2);
+	dump_field(tmr, 3);
+	dump_field(tmr, 4);
+	dump_field(tmr, 5);
+	dump_field(tmr, 6);
+	dump_field(tmr, 7);
+
+	db_printf("IRR Interrupts:\n");
+	dump_field(irr, 0);
+	dump_field(irr, 1);
+	dump_field(irr, 2);
+	dump_field(irr, 3);
+	dump_field(irr, 4);
+	dump_field(irr, 5);
+	dump_field(irr, 6);
+	dump_field(irr, 7);
+}
 #endif
 
 /*
Index: i386/i386/mp_machdep.c
===================================================================
RCS file: /usr/cvs/src/sys/i386/i386/mp_machdep.c,v
retrieving revision 1.269
diff -u -r1.269 mp_machdep.c
--- i386/i386/mp_machdep.c	16 May 2006 14:32:16 -0000	1.269
+++ i386/i386/mp_machdep.c	11 Sep 2006 20:00:10 -0000
@@ -385,7 +385,11 @@
 	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 	setidt(IPI_INVLRNG, IDTVEC(invlrng),
 	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-	
+
+	/* Install an inter-CPU IPI for cache invalidation. */
+	setidt(IPI_INVLCACHE, IDTVEC(invlcache),
+	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
 	/* Install an inter-CPU IPI for lazy pmap release */
 	setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
 	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));