Opcode Instruction Clocks Description 0F A4 SHLD r/m16,r16,imm8 3/7 r/m16 gets SHL of r/m16 concatenated with r16 0F A4 SHLD r/m32,r32,imm8 3/7 r/m32 gets SHL of r/m32 concatenated with r32 0F A5 SHLD r/m16,r16,CL 3/7 r/m16 gets SHL of r/m16 concatenated with r16 0F A5 SHLD r/m32,r32,CL 3/7 r/m32 gets SHL of r/m32 concatenated with r32
(* count is an unsigned integer corresponding to the last operand of the instruction, either an immediate byte or the byte in register CL *) ShiftAmt := count MOD 32; inBits := register; (* Allow overlapped operands *) IF ShiftAmt = 0 THEN no operation ELSE IF ShiftAmt >= OperandSize THEN (* Bad parameters *) r/m := UNDEFINED; CF, OF, SF, ZF, AF, PF := UNDEFINED; ELSE (* Perform the shift *) CF := BIT[Base, OperandSize - ShiftAmt]; (* Last bit shifted out on exit *) FOR i := OperandSize - 1 DOWNTO ShiftAmt DO BIT[Base, i] := BIT[Base, i - ShiftAmt]; OF; FOR i := ShiftAmt - 1 DOWNTO 0 DO BIT[Base, i] := BIT[inBits, i - ShiftAmt + OperandSize]; OD; Set SF, ZF, PF (r/m); (* SF, ZF, PF are set according to the value of the result *) AF := UNDEFINED; FI; FI;
The count operand is provided by either an immediate byte or the contents of the CL register. These operands are taken MODULO 32 to provide a number between 0 and 31 by which to shift. Because the bits to shift are provided by the specified registers, the operation is useful for multiprecision shifts (64 bits or more). The SF, ZF and PF flags are set according to the value of the result. CS is set to the value of the last bit shifted out. OF and AF are left undefined.
Chapter 17 -- 80386 Instruction Set
prev: SGDT/SIDT Store Global/Interrupt Descriptor Table Register
next: SHRD Double Precision Shift Right