Index: amd64/amd64/mp_machdep.c
===================================================================
RCS file: /home/ncvs/src/sys/amd64/amd64/mp_machdep.c,v
retrieving revision 1.248
diff -u -r1.248 mp_machdep.c
--- amd64/amd64/mp_machdep.c	5 Nov 2004 18:25:22 -0000	1.248
+++ amd64/amd64/mp_machdep.c	25 Dec 2004 00:31:30 -0000
@@ -112,6 +112,7 @@
  * Local data and functions.
  */
 
+static uint64_t cpu0_tsc;
 static u_int logical_cpus;
 
 /* used to hold the AP's until we are ready to release them */
@@ -372,6 +373,7 @@
 	struct pcpu *pc;
 	u_int64_t msr, cr0;
 	int cpu, gsel_tss;
+	uint64_t tscval;
 
 	/* Set by the startup code for us to use */
 	cpu = bootAP;
@@ -451,6 +453,17 @@
 		printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
 		panic("cpuid mismatch! boom!!");
 	}
+	/*
+	 * Synchronize the tsc.
+	 */
+	tscval = atomic_load_acq_long(&cpu0_tsc);
+	wrmsr(MSR_TSC, tscval);
+	printf("Setting tsc to: %ld\n", tscval);
+	msr = atomic_load_acq_long(&cpu0_tsc);
+	tscval = msr - rdtsc();
+	printf("Adjusting tsc by: %ld\n", tscval);
+	wrmsr(MSR_TSC, rdtsc() + tscval);
+	printf("tsc is: %ld\n", rdtsc());
 
 	mtx_lock_spin(&ap_boot_mtx);
 
@@ -1004,7 +1017,7 @@
 	mtx_lock_spin(&sched_lock);
 	atomic_store_rel_int(&aps_ready, 1);
 	while (smp_started == 0)
-		ia32_pause();
+		atomic_store_rel_long(&cpu0_tsc, rdtsc());
 	mtx_unlock_spin(&sched_lock);
 }
 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);