diff --exclude .svn -ur freebsd-svn-crashfix/sys/mips/mips/vm_machdep.c freebsd-svn-clean/sys/mips/mips/vm_machdep.c --- freebsd-svn-crashfix/sys/mips/mips/vm_machdep.c 2010-05-07 12:18:05.000299000 +0530 +++ freebsd-svn-clean/sys/mips/mips/vm_machdep.c 2010-05-04 14:25:30.000037000 +0530 @@ -148,7 +148,7 @@ pcb2->pcb_context[PCB_REG_S0] = (register_t)fork_return; pcb2->pcb_context[PCB_REG_S1] = (register_t)td2; pcb2->pcb_context[PCB_REG_S2] = (register_t)td2->td_frame; - pcb2->pcb_context[PCB_REG_SR] = SR_INT_MASK & mips_rd_status(); + pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | MIPS_SR_COP_2_BIT | SR_INT_MASK) & mips_rd_status(); /* * FREEBSD_DEVELOPERS_FIXME: * Setup any other CPU-Specific registers (Not MIPS Standard) @@ -345,6 +345,8 @@ pcb2->pcb_context[PCB_REG_S2] = (register_t)td->td_frame; /* Dont set IE bit in SR. sched lock release will take care of it */ pcb2->pcb_context[PCB_REG_SR] = SR_INT_MASK & mips_rd_status(); + if ((mips_rd_status() & 0x80) ==0 ) + printf("func %s fail\n", __func__); #ifdef TARGET_OCTEON pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | @@ -408,6 +410,8 @@ */ tf->sr = SR_KSU_USER | SR_EXL | (SR_INT_MASK & mips_rd_status()) | MIPS_SR_INT_IE; + if ((mips_rd_status() & 0x80) ==0 ) + printf("func %s fail\n", __func__); #ifdef TARGET_OCTEON tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_UX | MIPS_SR_KX; diff --exclude .svn -ur freebsd-svn-crashfix/sys/mips/mips/exception.S freebsd-svn-clean/sys/mips/mips/exception.S --- freebsd-svn-crashfix/sys/mips/mips/exception.S 2010-05-07 12:18:05.000323000 +0530 +++ freebsd-svn-clean/sys/mips/mips/exception.S 2010-05-03 20:30:36.015075000 +0530 @@ -223,7 +223,7 @@ #define SAVE_REG(reg, offs, base) \ REG_S reg, CALLFRAME_SIZ + (SZREG * offs) (base) -#ifdef TARGET_OCTEON +#if defined(TARGET_OCTEON) #define CLEAR_STATUS \ mfc0 a0, COP_0_STATUS_REG ;\ li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \ @@ -232,6 +232,15 @@ and a0, a0, a2 ; \ mtc0 a0, COP_0_STATUS_REG ; \ ITLBNOPFIX +#elif defined(TARGET_XLR_XLS) +#define CLEAR_STATUS \ + mfc0 a0, COP_0_STATUS_REG ;\ + li a2, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) ; \ + or a0, a0, a2 ; \ + li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \ + and a0, a0, a2 ; \ + mtc0 a0, COP_0_STATUS_REG ; \ + ITLBNOPFIX #else #define CLEAR_STATUS \ mfc0 a0, COP_0_STATUS_REG ;\ @@ -463,8 +472,10 @@ PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP # Turn off fpu and enter kernel mode and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB) -#ifdef TARGET_OCTEON +#if defined(TARGET_OCTEON) or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX) +#elif defined(TARGET_XLR_XLS) + or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) #endif mtc0 t0, COP_0_STATUS_REG PTR_ADDU a0, k1, U_PCB_REGS @@ -681,6 +692,8 @@ and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK) #ifdef TARGET_OCTEON or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX) +#elif defined(TARGET_XLR_XLS) + or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) #endif mtc0 t0, COP_0_STATUS_REG ITLBNOPFIX diff --exclude .svn -ur freebsd-svn-crashfix/sys/mips/mips/locore.S freebsd-svn-clean/sys/mips/mips/locore.S --- freebsd-svn-crashfix/sys/mips/mips/locore.S 2010-05-07 12:18:06.000014000 +0530 +++ freebsd-svn-clean/sys/mips/mips/locore.S 2010-05-03 20:06:27.000748000 +0530 @@ -99,7 +99,7 @@ /* Reset these bits */ li t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE) -#elif defined (CPU_XLR) +#elif defined (TARGET_XLR_XLS) /* Set these bits */ li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX) diff --exclude .svn -ur freebsd-svn-crashfix/sys/mips/mips/mpboot.S freebsd-svn-clean/sys/mips/mips/mpboot.S --- freebsd-svn-crashfix/sys/mips/mips/mpboot.S 2010-05-07 16:44:14.000304000 +0530 +++ freebsd-svn-clean/sys/mips/mips/mpboot.S 2010-05-05 15:18:57.003865000 +0530 @@ -36,14 +36,18 @@ .set noat .set noreorder -#ifdef TARGET_OCTEON +#if defined(TARGET_OCTEON) #define CLEAR_STATUS \ mfc0 a0, COP_0_STATUS_REG ;\ li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \ or a0, a0, a2 ; \ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER | MIPS_SR_BEV) ; \ and a0, a0, a2 ; \ - mtc0 a0, COP_0_STATUS_REG + mtc0 a0, COP_0_STATUS_REG +#elif defined(TARGET_XLR_XLS) +#define CLEAR_STATUS \ + li a0, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX) + mtc0 a0, COP_0_STATUS_REG #else #define CLEAR_STATUS \ mtc0 zero, COP_0_STATUS_REG