Index: i82365.h =================================================================== RCS file: /cache/ncvs/src/sys/pccard/i82365.h,v retrieving revision 1.10.2.7 diff -u -r1.10.2.7 i82365.h --- i82365.h 12 Nov 2001 05:29:21 -0000 1.10.2.7 +++ i82365.h 6 Jul 2002 17:11:05 -0000 @@ -118,7 +118,8 @@ #define PCIC_IBM3 0x8a /* IBM KING PCIC clone; Both Memory and I/O */ /* For Interface Status register (PCIC_STATUS) */ -#define PCIC_VPPV 0x80 /* Vpp_valid */ +#define PCIC_VPPV 0x80 /* Vpp_valid or reserved*/ +#define PCIC_RICOH_5VCARD 0x80 /* 5V card detected */ #define PCIC_POW 0x40 /* PC Card power active */ #define PCIC_READY 0x20 /* Ready/~Busy */ #define PCIC_MWP 0x10 /* Memory Write Protect */ Index: pccard.c =================================================================== RCS file: /cache/ncvs/src/sys/pccard/pccard.c,v retrieving revision 1.106.2.12 diff -u -r1.106.2.12 pccard.c --- pccard.c 12 Nov 2001 05:36:35 -0000 1.106.2.12 +++ pccard.c 6 Jul 2002 17:11:05 -0000 @@ -32,8 +32,6 @@ * $FreeBSD: src/sys/pccard/pccard.c,v 1.106.2.12 2001/11/12 05:36:35 imp Exp $ */ -#include "opt_pcic.h" - #include #include #include @@ -54,18 +52,6 @@ #include -#if __FreeBSD_version < 500000 -#define suser_td(a) suser(a) -#endif - -SYSCTL_NODE(_machdep, OID_AUTO, pccard, CTLFLAG_RW, 0, "pccard"); - -/* The following might now be obsolete */ -static int pcic_resume_reset = 1; - -SYSCTL_INT(_machdep_pccard, OID_AUTO, pcic_resume_reset, CTLFLAG_RW, - &pcic_resume_reset, 0, ""); - #define MIN(a,b) ((a)<(b)?(a):(b)) static int allocate_driver(struct slot *, struct dev_desc *); @@ -301,25 +287,23 @@ slt->state = filled; /* - * Enable 5V to the card so that the CIS can be read. - */ - slt->pwr.vcc = -1; - slt->pwr.vpp = 50; - - /* * Disable any pending timeouts for this slot, and explicitly * power it off right now. Then, re-enable the power using * the (possibly new) power settings. */ untimeout(power_off_slot, (caddr_t)slt, slt->poff_ch); power_off_slot(slt); + + /* + * Enable 5V to the card so that the CIS can be read. Well, + * enable the most natural voltage so that the CIS can be read. + */ + slt->pwr.vcc = -1; + slt->pwr.vpp = -1; slt->ctrl->power(slt); printf("pccard: card inserted, slot %d\n", slt->slotnum); pccard_insert_beep(); - /* - * Now start resetting the card. - */ slt->ctrl->reset(slt); } @@ -524,7 +508,7 @@ * At the very least, we only allow root to set the context. */ case PIOCSMEM: - if (suser_td(td)) + if (suser(td)) return (EPERM); if (slt->state != filled) return (ENXIO); @@ -549,7 +533,7 @@ * Set I/O port context. */ case PIOCSIO: - if (suser_td(td)) + if (suser(td)) return (EPERM); if (slt->state != filled) return (ENXIO); @@ -575,7 +559,7 @@ *(unsigned long *)data = pccard_mem; break; } - if (suser_td(td)) + if (suser(td)) return (EPERM); /* * Validate the memory by checking it against the I/O @@ -607,7 +591,7 @@ * Allocate a driver to this slot. */ case PIOCSDRV: - if (suser_td(td)) + if (suser(td)) return (EPERM); err = allocate_driver(slt, (struct dev_desc *)data); if (!err) Index: pcic.c =================================================================== RCS file: /cache/ncvs/src/sys/pccard/pcic.c,v retrieving revision 1.89.2.25 diff -u -r1.89.2.25 pcic.c --- pcic.c 18 Jan 2002 16:42:28 -0000 1.89.2.25 +++ pcic.c 6 Jul 2002 17:11:05 -0000 @@ -387,7 +387,6 @@ sp->slt->irq = sc->irq; /* Check for changes */ - pcic_setb(sp, PCIC_POWER, PCIC_PCPWRE | PCIC_DISRST); sp->slt->laststate = sp->slt->state = empty; if (pcic_boot_deactivated) { if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD) { @@ -495,10 +494,8 @@ * cardbus bridges have minor issues with power via the ExCA registers, * go ahead and do it all via cardbus registers. * - * An expamination of the code will show the relative - * ease that we do Vpp as well. - * - * Too bad it appears to not work. + * An expamination of the code will show the relative ease that we do + * Vpp in comparison to the ExCA case (which may be partially broken). */ static int pcic_cardbus_power(struct pcic_slot *sp, struct slot *slt) @@ -506,58 +503,126 @@ uint32_t power; uint32_t state; + /* + * If we're doing an auto-detect, and we're in a badvcc state, then + * we need to force the socket to rescan the card. We don't do this + * all the time because the socket can take up to 200ms to do the deed, + * and that's too long to busy wait. Since this is a relatively rare + * event (some BIOSes, and earlier versions of OLDCARD caused it), we + * test for it special. + */ + state = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE); + if (slt->pwr.vcc == -1 && (state & CB_SS_BADVCC)) { + /* + * Force the bridge to scan the card for the proper voltages + * that it supports. + */ + bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_FORCE, + CB_SF_INTCVS); + state = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE); + /* This while loop can take 100-150ms */ + while ((state & CB_SS_CARD_MASK) == 0) { + DELAY(10 * 1000); + state = bus_space_read_4(sp->bst, sp->bsh, + CB_SOCKET_STATE); + } + } + + + /* + * Preserve the clock stop bit of the socket power register. Not + * sure that we want to do that, but maybe we should set it based + * on the power state. + */ + power = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_POWER); + power = 0; + /* - * Preserve the clock stop bit of the socket power register. + * vcc == -1 means automatically detect the voltage of the card. + * Do so and apply the right amount of power. */ - power = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_POWER); - state = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE); - printf("old value 0x%x\n", power); - power &= ~CB_SP_CLKSTOP; + if (slt->pwr.vcc == -1) { + if (state & CB_SS_5VCARD) + slt->pwr.vcc = 50; + else if (state & CB_SS_3VCARD) + slt->pwr.vcc = 33; + else if (state & CB_SS_XVCARD) + slt->pwr.vcc = 22; + else if (state & CB_SS_YVCARD) + slt->pwr.vcc = 11; + if (bootverbose && slt->pwr.vcc != -1) + device_printf(sp->sc->dev, + "Autodetected %d.%dV card\n", + slt->pwr.vcc / 10, slt->pwr.vcc % 10); + } - switch(slt->pwr.vpp) { + switch(slt->pwr.vcc) { default: return (EINVAL); case 0: - power |= CB_SP_VPP_0V; + power |= CB_SP_VCC_0V; + break; + case 11: + power |= CB_SP_VCC_YV; + break; + case 22: + power |= CB_SP_VCC_XV; break; case 33: - power |= CB_SP_VPP_3V; + power |= CB_SP_VCC_3V; break; case 50: - power |= CB_SP_VPP_5V; - break; - case 120: - power |= CB_SP_VPP_12V; + power |= CB_SP_VCC_5V; break; } - switch(slt->pwr.vcc) { + /* + * vpp == -1 means use vcc voltage. + */ + if (slt->pwr.vpp == -1) + slt->pwr.vpp = slt->pwr.vcc; + switch(slt->pwr.vpp) { default: return (EINVAL); case 0: - power |= CB_SP_VCC_0V; + power |= CB_SP_VPP_0V; + break; + case 11: + power |= CB_SP_VPP_YV; + break; + case 22: + power |= CB_SP_VPP_XV; break; case 33: - power |= CB_SP_VCC_3V; + power |= CB_SP_VPP_3V; break; case 50: - power |= CB_SP_VCC_5V; + power |= CB_SP_VPP_5V; break; - case -1: - if (state & CB_SS_5VCARD) - power |= CB_SP_VCC_5V; - else if (state & CB_SS_3VCARD) - power |= CB_SP_VCC_3V; - else if (state & CB_SS_XVCARD) - power |= CB_SP_VCC_XV; - else if (state & CB_SS_YVCARD) - power |= CB_SP_VCC_YV; + case 120: + power |= CB_SP_VPP_12V; break; } - printf("Setting power reg to 0x%x", power); bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_POWER, power); - return (EIO); + /* + * OK. We need to bring the card out of reset. Let the power + * stabilize for 300ms (why 300?) and then enable the outputs + * and then wait 100ms (why 100?) for it to stabilize. These numbers + * were stolen from the dim, dark past of OLDCARD and I have no clue + * how they were derived. I also use the bit setting routines here + * as a measure of conservatism. + */ + if (power) { + pcic_setb(sp, PCIC_POWER, PCIC_DISRST); + DELAY(300*1000); + pcic_setb(sp, PCIC_POWER, PCIC_DISRST | PCIC_OUTENA); + DELAY(100*1000); + } else { + pcic_clrb(sp, PCIC_POWER, PCIC_DISRST | PCIC_OUTENA); + } + + return (0); } /* @@ -572,6 +637,7 @@ struct pcic_slot *sp = slt->cdata; struct pcic_slot *sp2; struct pcic_softc *sc = sp->sc; + int dodefault = 0; /* * Cardbus power registers are completely different. @@ -579,6 +645,9 @@ if (sc->flags & PCIC_CARDBUS_POWER) return (pcic_cardbus_power(sp, slt)); + if (bootverbose) + device_printf(sc->dev, "Power: Vcc=%d Vpp=%d\n", slt->pwr.vcc, + slt->pwr.vpp); /* * If we're automatically detecting what voltage to use, then we need * to ask the bridge what type (voltage-wise) the card is. @@ -605,7 +674,9 @@ * seem to have the signals wired right for the '29 * method to work, so we always use the '10 method for * the '22. The laptops that don't work hang solid - * when the pccard memory is accessed. + * when the pccard memory is accessed. The '32 and + * '33 cases are taken care of in cardbus code, so + * it doesn't matter that I have no clue. */ switch (sp->controller) { case PCIC_PD6710: @@ -642,11 +713,34 @@ */ reg |= PCIC_APSENA; } + if (sc->flags & PCIC_RICOH_POWER) { + switch (sp->controller) { + case PCIC_RF5C396: + case PCIC_RF5C296: + /* + * The ISA bridge have the 5V/3.3V in register + * 1, bit 7. + */ + c = sp->getb(sp, PCIC_STATUS); + if ((c & PCIC_RICOH_5VCARD) == 0) + slt->pwr.vcc = 33; + else + slt->pwr.vcc = 50; + break; + } + } /* Other bridges here */ if (bootverbose && slt->pwr.vcc != -1) device_printf(sc->dev, "Autodetected %d.%dV card\n", slt->pwr.vcc / 10, slt->pwr.vcc %10); } + if (slt->pwr.vcc == -1) { + if (bootverbose) + device_printf(sc->dev, + "Couldn't autodetect voltage, assuming 5.0V\n"); + dodefault = 1; + slt->pwr.vcc = 50; + } /* * XXX Note: The Vpp controls varies quit a bit between bridge chips @@ -655,6 +749,8 @@ * applications want vpp == vcc and the following code does appear * to do that for all bridge sets. */ + if (slt->pwr.vpp == -1) + slt->pwr.vpp = slt->pwr.vcc; switch(slt->pwr.vpp) { default: return (EINVAL); @@ -707,7 +803,6 @@ if (sc->flags & PCIC_DF_POWER) reg |= PCIC_VCC_3V; break; - case -1: /* Treat default like 5.0V */ case 50: if (sc->flags & PCIC_KING_POWER) reg |= PCIC_VCC_5V_KING; @@ -728,25 +823,36 @@ break; } sp->putb(sp, PCIC_POWER, reg); + if (bootverbose) + device_printf(sc->dev, "Power applied\n"); DELAY(300*1000); if (slt->pwr.vcc) { reg |= PCIC_OUTENA; sp->putb(sp, PCIC_POWER, reg); + if (bootverbose) + device_printf(sc->dev, "Output enabled\n"); DELAY(100*1000); + if (bootverbose) + device_printf(sc->dev, "Settling complete\n"); } /* * Some chipsets will attempt to preclude us from supplying * 5.0V to cards that only handle 3.3V. We seem to need to * try 3.3V to paper over some power handling issues in other - * parts of the system. I suspect they are in the pccard bus - * driver, but may be in pccardd as well. + * parts of the system. Maybe the proper detection of 3.3V cards + * now obviates the need for this hack, so put a printf in to + * warn the world about it. */ - if (!(sp->getb(sp, PCIC_STATUS) & PCIC_POW) && slt->pwr.vcc == -1) { + if (!(sp->getb(sp, PCIC_STATUS) & PCIC_POW) && dodefault) { slt->pwr.vcc = 33; slt->pwr.vpp = 0; + device_printf(sc->dev, + "Failed at 5.0V. Trying 3.3V. Please report message to mobile@freebsd.org\n"); return (pcic_power(slt)); } + if (bootverbose) + printf("Power complete.\n"); return (0); } @@ -764,7 +870,13 @@ } /* - * pcic_reset - Reset the card and enable initial power. + * pcic_reset - Reset the card and enable initial power. This may + * need to be interrupt driven in the future. We should likely turn + * the reset on, DELAY for a period of time < 250ms, turn it off and + * tsleep for a while and check it when we're woken up. I think that + * we're running afoul of the card status interrupt glitching, causing + * an interrupt storm because the card doesn't seem to be able to + * clear this pin while in reset. */ static void pcic_reset(void *chan) @@ -820,7 +932,8 @@ } /* - * pcic_disable - Disable the slot. + * pcic_disable - Disable the slot. I wonder if these operations can + * cause an interrupt we need to acknowledge? XXX */ static void pcic_disable(struct slot *slt) @@ -829,7 +942,8 @@ pcic_clrb(sp, PCIC_INT_GEN, PCIC_CARDTYPE | PCIC_CARDRESET); pcic_mapirq(slt, 0); - sp->putb(sp, PCIC_POWER, 0); + slt->pwr.vcc = slt->pwr.vpp = 0; + pcic_power(slt); } /* Index: pcic_pci.c =================================================================== RCS file: /cache/ncvs/src/sys/pccard/pcic_pci.c,v retrieving revision 1.54.2.19 diff -u -r1.54.2.19 pcic_pci.c --- pcic_pci.c 18 Jan 2002 16:47:56 -0000 1.54.2.19 +++ pcic_pci.c 6 Jul 2002 17:11:05 -0000 @@ -71,7 +71,7 @@ * The following should be a hint, so we can do it on a per device * instance, but this is convenient. Do not set this unless pci * routing doesn't work. It is purposely vague and undocumented - * at the moment. + * at the moment. Sadly, this seems to be needed way too often. */ static int pcic_intr_path = (int)pcic_iw_pci; TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path); @@ -87,6 +87,12 @@ setting this tunable to 1 will resolve the problem. PCI Cards will almost\n\ always require this, while builtin bridges need it less often"); +static int pcic_ignore_pci = 0; +TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci); +SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD, + &pcic_ignore_pci, 0, + "When set, driver ignores pci cardbus bridges it would otherwise claim."); + static void pcic_pci_cardbus_init(device_t); static pcic_intr_way_t pcic_pci_gen_func; static pcic_intr_way_t pcic_pci_gen_csc; @@ -202,13 +208,13 @@ PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd67xx_chip }, { PCI_DEVICE_ID_PCIC_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge", - PCIC_PD673X, PCIC_PD_POWER, &pcic_pci_pd68xx_chip }, + PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip }, { PCI_DEVICE_ID_PCIC_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge", - PCIC_PD673X, PCIC_PD_POWER, &pcic_pci_pd68xx_chip }, + PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip }, { PCI_DEVICE_ID_PCIC_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge", - PCIC_PD673X, PCIC_PD_POWER, &pcic_pci_pd68xx_chip }, + PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip }, { PCI_DEVICE_ID_PCIC_OZ6729, "O2micro OZ6729 PC-Card Bridge", PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip }, @@ -217,16 +223,16 @@ PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip }, { PCI_DEVICE_ID_PCIC_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge", - PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip }, { PCI_DEVICE_ID_PCIC_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge", - PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip }, { PCI_DEVICE_ID_PCIC_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge", - PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip }, { PCI_DEVICE_ID_PCIC_OZ6912, "O2micro 6912 PCI-Cardbus Bridge", - PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip }, { PCI_DEVICE_ID_PCIC_OZ6922, "O2micro 6922 PCI-Cardbus Bridge", PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip }, @@ -235,94 +241,94 @@ PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip }, { PCI_DEVICE_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge", - PCIC_RF5C296, PCIC_RICOH_POWER, &pcic_pci_ricoh_chip }, + PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip }, { PCI_DEVICE_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge", - PCIC_RF5C296, PCIC_RICOH_POWER, &pcic_pci_ricoh_chip }, + PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip }, { PCI_DEVICE_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge", - PCIC_RF5C296, PCIC_RICOH_POWER, &pcic_pci_ricoh_chip }, + PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip }, { PCI_DEVICE_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge", - PCIC_RF5C296, PCIC_RICOH_POWER, &pcic_pci_ricoh_chip }, + PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip }, { PCI_DEVICE_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge", - PCIC_RF5C296, PCIC_RICOH_POWER, &pcic_pci_ricoh_chip }, + PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip }, { PCI_DEVICE_ID_PCIC_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti113x_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip }, { PCI_DEVICE_ID_PCIC_TI1130, "TI PCI-1130 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti113x_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip }, { PCI_DEVICE_ID_PCIC_TI1131, "TI PCI-1131 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti113x_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip }, { PCI_DEVICE_ID_PCIC_TI1210, "TI PCI-1210 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1211, "TI PCI-1211 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1220, "TI PCI-1220 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1221, "TI PCI-1221 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1225, "TI PCI-1225 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1250, "TI PCI-1250 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1251, "TI PCI-1251 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1251B, "TI PCI-1251B PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1260, "TI PCI-1260 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1260B, "TI PCI-1260B PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1410, "TI PCI-1410 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1420, "TI PCI-1420 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1421, "TI PCI-1421 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1450, "TI PCI-1450 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI1451, "TI PCI-1451 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI4410, "TI PCI-4410 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI4450, "TI PCI-4450 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_PCIC_TI4451, "TI PCI-4451 PCI-CardBus Bridge", - PCIC_I82365SL_DF, PCIC_DF_POWER, &pcic_pci_ti12xx_chip }, + PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip }, { PCI_DEVICE_ID_TOSHIBA_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge", - PCIC_I82365, PCIC_AB_POWER, &pcic_pci_topic_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip }, { PCI_DEVICE_ID_TOSHIBA_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge", - PCIC_I82365, PCIC_AB_POWER, &pcic_pci_topic_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip }, { PCI_DEVICE_ID_TOSHIBA_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge", - PCIC_I82365, PCIC_DF_POWER, &pcic_pci_topic_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip }, { PCI_DEVICE_ID_TOSHIBA_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge", - PCIC_I82365, PCIC_DF_POWER, &pcic_pci_topic_chip }, + PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip }, { 0, NULL, 0, 0, NULL } }; @@ -429,7 +435,7 @@ { /* * The 68xx datasheets make it hard to know what the right thing - * do do here is. We do hwat we knjow, which is nothing, and + * to do here is. We do what we know, which is nothing, and * hope for the best. */ /* XXX */ @@ -818,6 +824,18 @@ u_int32_t device_id; device_id = pci_get_devid(dev); + reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4); + reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | + TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); + reg &= ~TOPIC_SLOT_CTRL_SWDETECT; + if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 || + device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) { + reg |= TOPIC97_SLOT_CTRL_PCIINT; + reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); + } + pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4); + pcic_pci_cardbus_init(dev); + if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 || device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) { /* @@ -830,15 +848,6 @@ pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR, PCIC_FCR_3V_EN | PCIC_FCR_VS_EN); } - reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4); - reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | - TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); - reg &= ~TOPIC_SLOT_CTRL_SWDETECT; - if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 || - device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) - reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); - pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4); - pcic_pci_cardbus_init(dev); } static void @@ -930,7 +939,7 @@ sc->cd_present = 1; if (bootverbose && (stat & CB_SS_BADVCC) != 0) - device_printf(sc->dev, "BAD Vcc request\n"); + device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat); if ((stat & CB_SS_16BIT) == 0) device_printf(sp->sc->dev, "Card type %s is unsupported\n", pcic_pci_cardtype(stat)); @@ -999,6 +1008,8 @@ struct resource *res; int rid; + if (pcic_ignore_pci) + return (ENXIO); device_id = pci_get_devid(dev); desc = NULL; itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]); @@ -1015,7 +1026,7 @@ if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0) desc = "Generic PCI-PCMCIA Bridge"; if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) - desc = "YENTA PCI-CARDBUS Bridge"; + desc = "YENTA PCI-CardBus Bridge"; if (bootverbose && desc) printf("Found unknown %s devid 0x%x\n", desc, device_id); } @@ -1224,9 +1235,8 @@ /* By default, assume we're a D step compatible */ sp->controller = PCIC_I82365SL_DF; sp->revision = 0; - sc->flags = PCIC_DF_POWER; + sc->flags = PCIC_CARDBUS_POWER; } - /* sc->flags = PCIC_CARDBUS_POWER; */ sp->slt = (struct slot *) 1; sc->csc_route = pcic_intr_path; sc->func_route = pcic_intr_path; @@ -1328,7 +1338,7 @@ pci_write_config(dev, sc->memrid, 0xffffffff, 4); sockbase = pci_read_config(dev, sc->memrid, 4); sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0); -#define CARDBUS_SYS_RES_MEMORY_START 0x44000000 +#define CARDBUS_SYS_RES_MEMORY_START 0x88000000 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF sc->memres = bus_generic_alloc_resource(device_get_parent(dev), dev, SYS_RES_MEMORY, &sc->memrid, Index: pcic_pci.h =================================================================== RCS file: /cache/ncvs/src/sys/pccard/pcic_pci.h,v retrieving revision 1.23.2.9 diff -u -r1.23.2.9 pcic_pci.h --- pcic_pci.h 12 Nov 2001 05:29:22 -0000 1.23.2.9 +++ pcic_pci.h 6 Jul 2002 17:11:05 -0000 @@ -201,6 +201,7 @@ #define CB_SM_CD 0x6 /* Socket MASK Card detect */ #define CB_SM_POWER 0x8 +/* Socket State Register */ #define CB_SS_CARDSTS 0x00000001 /* Card Status Change */ #define CB_SS_CD1 0x00000002 /* Card Detect 1 */ #define CB_SS_CD2 0x00000004 /* Card Detect 2 */ @@ -216,20 +217,41 @@ #define CB_SS_3VCARD 0x00000800 /* 3.3 V Card */ #define CB_SS_XVCARD 0x00001000 /* X.X V Card */ #define CB_SS_YVCARD 0x00002000 /* Y.Y V Card */ +#define CB_SS_CARD_MASK 0x00003c00 /* *VCARD signal */ #define CB_SS_5VSOCK 0x10000000 /* 5 V Socket */ #define CB_SS_3VSOCK 0x20000000 /* 3.3 V Socket */ #define CB_SS_XVSOCK 0x40000000 /* X.X V Socket */ #define CB_SS_YVSOCK 0x80000000 /* Y.Y V Socket */ +/* Socket power register */ #define CB_SP_CLKSTOP 0x80 /* Cardbus clock stop protocol */ +#define CB_SP_VCC_MASK 0x70 #define CB_SP_VCC_0V 0x00 + /* 0x10 is reserved 12V in VPP */ #define CB_SP_VCC_5V 0x20 #define CB_SP_VCC_3V 0x30 #define CB_SP_VCC_XV 0x40 #define CB_SP_VCC_YV 0x50 + /* 0x60 and 0x70 are reserved */ +#define CB_SP_VPP_MASK 0x07 #define CB_SP_VPP_0V 0x00 #define CB_SP_VPP_12V 0x01 #define CB_SP_VPP_5V 0x02 #define CB_SP_VPP_3V 0x03 #define CB_SP_VPP_XV 0x04 #define CB_SP_VPP_YV 0x05 + +/* Socket force register */ +#define CB_SF_INTCVS (1 << 14) /* Interregate CVS/CCD pins */ +#define CB_SF_5VCARD (1 << 11) +#define CB_SF_3VCARD (1 << 10) +#define CB_SF_BADVCC (1 << 9) +#define CB_SF_DATALOST (1 << 8) +#define CB_SF_NOTACARD (1 << 7) +#define CB_SF_CBCARD (1 << 5) +#define CB_SF_16CARD (1 << 4) +#define CB_SF_POWERCYCLE (1 << 3) +#define CB_SF_CCD2 (1 << 2) +#define CB_SF_CCD1 (1 << 1) +#define CB_SF_CSTCHG (1 << 0) + /* 0x6 and 0x7 are reserved */