Index: pccard/cardinfo.h
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/cardinfo.h,v
retrieving revision 1.16.2.5
diff -u -r1.16.2.5 cardinfo.h
--- pccard/cardinfo.h	28 Jul 2001 03:52:15 -0000	1.16.2.5
+++ pccard/cardinfo.h	1 Sep 2002 04:35:56 -0000
@@ -133,16 +133,23 @@
 /*
  *	Device descriptor for allocation of driver.
  */
+#define DEV_MISC_LEN	36
+#define DEV_MAX_CIS_LEN	40
 struct dev_desc {
-	char	name[16];	/* Driver name */
-	int	unit;		/* Driver unit number */
-	unsigned long mem;	/* Memory address of driver */
-	int	memsize;	/* Memory size (if used) */
-	int	iobase;		/* base of I/O ports */
-	int	iosize;		/* Length of I/O ports */
-	int	irqmask;	/* Interrupt number(s) to allocate */
-	int	flags;		/* Device flags */
-	u_char	misc[128];	/* For any random info */
+	char		name[16];	/* Driver name */
+	int		unit;		/* Driver unit number */
+	unsigned long	mem;		/* Memory address of driver */
+	int		memsize;	/* Memory size (if used) */
+	int		iobase;		/* base of I/O ports */
+	int		iosize;		/* Length of I/O ports */
+	int		irqmask;	/* Interrupt number(s) to allocate */
+	int		flags;		/* Device flags */
+	uint8_t		misc[DEV_MISC_LEN]; /* For any random info */
+	uint8_t		manufstr[DEV_MAX_CIS_LEN];
+	uint8_t		versstr[DEV_MAX_CIS_LEN];
+	uint32_t	manufacturer;	/* Manufacturer ID */
+	uint32_t	product;	/* Product ID */
+	uint32_t	prodext;	/* Product ID (extended) */
 };
 #define DEV_DESC_HAS_SIZE 1
 
@@ -155,20 +162,20 @@
  *	Slot information. Used to read current status of slot.
  */
 struct slotstate {
-	enum cardstate state;		/* Current state of slot */
-	enum cardstate laststate;	/* Previous state of slot */
-	int	maxmem;			/* Max allowed memory windows */
-	int	maxio;			/* Max allowed I/O windows */
-	int	irqs;			/* Bitmap of IRQs allowed */
-	int	flags;			/* Capability flags */
+	enum cardstate	state;		/* Current state of slot */
+	enum cardstate	laststate;	/* Previous state of slot */
+	int		maxmem;		/* Max allowed memory windows */
+	int		maxio;		/* Max allowed I/O windows */
+	int		irqs;		/* Bitmap of IRQs allowed */
+	int		flags;		/* Capability flags */
 };
 
 /*
  *	The power values are in volts * 10, e.g. 5V is 50, 3.3V is 33.
  */
 struct power {
-	int	vcc;
-	int	vpp;
+	int		vcc;
+	int		vpp;
 };
 
 /*
Index: pccard/i82365.h
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/i82365.h,v
retrieving revision 1.10.2.8
diff -u -r1.10.2.8 i82365.h
--- pccard/i82365.h	7 Jul 2002 18:52:28 -0000	1.10.2.8
+++ pccard/i82365.h	1 Sep 2002 04:35:57 -0000
@@ -104,6 +104,13 @@
 #define	PCIC_TIME_CMD1		0x3e
 #define	PCIC_TIME_RECOV1	0x3f
 
+/* Yenta only registers */
+#define PCIC_MEMORY_HIGH0	0x40	/* A31..A25 of mapping addres for */
+#define PCIC_MEMORY_HIGH1	0x41	/* the memory windows. */
+#define PCIC_MEMORY_HIGH2	0x42
+#define PCIC_MEMORY_HIGH3	0x43
+
+
 #define	PCIC_SLOT_SIZE	0x40	/* Size of register set for one slot */
 
 /* Now register bits, ordered by reg # */
@@ -261,6 +268,15 @@
 #define PCIC_VS2A	0x02
 #define PCIC_VS1B	0x04
 #define PCIC_VS2B	0x08
+
+/* Cirrus Logic: Extended register Extension Control 1 */
+#define PCIC_EXTCTRL1	0x03
+#define PCIC_EC1_VCC_LOCK 0x1		/* Vcc Power locked to s/w change */
+#define PCIC_EC1_AUTO_POWER_CLEAR 0x2	/* Vcc power cleared on eject? */
+#define PCIC_EC1_LED_ENABLE 0x4		/* LED activity enable */
+#define PCIC_EC1_CARD_IRQ_INV 0x8	/* Card IRQ level inverted for pci? */
+#define PCIC_EC1_CSC_IRQ_INV 0x10	/* CSC IRQ level inverted for pci? */
+#define PCIC_EC1_PULLUP 0x20		/* Dis pullup when 1. */
 
 /* Vadem: Card Voltage Select register (PCIC_CVSR) */
 #define PCIC_CVSR_VS	0x03		/* Voltage select */
Index: pccard/pccard.c
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/pccard.c,v
retrieving revision 1.106.2.13
diff -u -r1.106.2.13 pccard.c
--- pccard/pccard.c	7 Jul 2002 18:52:28 -0000	1.106.2.13
+++ pccard/pccard.c	1 Sep 2002 04:35:57 -0000
@@ -224,6 +224,11 @@
 	devi->running = 1;
 	devi->slt = slt;
 	bcopy(desc->misc, devi->misc, sizeof(desc->misc));
+	strcpy(devi->manufstr, desc->manufstr);
+	strcpy(devi->versstr, desc->versstr);
+	devi->manufacturer = desc->manufacturer;
+	devi->product = desc->product;
+	devi->prodext = desc->prodext;
 	resource_list_init(&devi->resources);
 	child = device_add_child(pccarddev, devi->name, desc->unit);
 	if (child == NULL) {
@@ -552,7 +557,6 @@
 		break;
 	/*
 	 * Set the memory window to be used for the read/write interface.
-	 * Not available on the alpha.
 	 */
 	case PIOCRWMEM:
 		if (*(unsigned long *)data == 0) {
Index: pccard/pccard_nbk.c
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/pccard_nbk.c,v
retrieving revision 1.15.2.10
diff -u -r1.15.2.10 pccard_nbk.c
--- pccard/pccard_nbk.c	12 Nov 2001 05:29:22 -0000	1.15.2.10
+++ pccard/pccard_nbk.c	1 Sep 2002 04:35:57 -0000
@@ -86,8 +86,13 @@
 
 SYSCTL_NODE(_machdep, OID_AUTO, pccard, CTLFLAG_RW, 0, "pccard");
 
+#ifdef UNSAFE
 static u_long mem_start = IOM_BEGIN;
 static u_long mem_end = IOM_END;
+#else
+static u_long mem_start = 0xd0000;
+static u_long mem_end = 0xeffff;
+#endif
 
 SYSCTL_ULONG(_machdep_pccard, OID_AUTO, mem_start, CTLFLAG_RW,
     &mem_start, 0, "");
@@ -114,7 +119,7 @@
 static int
 pccard_probe(device_t dev)
 {
-	device_set_desc(dev, "PC Card bus (classic)");
+	device_set_desc(dev, "PC Card 16-bit bus (classic)");
 	return (0);
 }
 
@@ -308,6 +313,15 @@
 	case PCCARD_IVAR_ETHADDR:
 		bcopy(devi->misc, result, ETHER_ADDR_LEN);
 		return (0);
+	case PCCARD_IVAR_VENDOR:
+		*(u_int32_t *) result = devi->manufacturer;
+		return (0);
+	case PCCARD_IVAR_PRODUCT:
+		*(u_int32_t *) result = devi->product;
+		return (0);
+	case PCCARD_IVAR_PRODEXT:
+		*(u_int16_t *) result = devi->prodext;
+		return (0);
 	}
 	return (ENOENT);
 }
@@ -374,9 +388,10 @@
 	return (0);
 }
 
-const struct pccard_product *
-pccard_product_lookup(device_t dev, const struct pccard_product *tab,
-    size_t ent_size, pccard_product_match_fn matchfn)
+static const struct pccard_product *
+pccard_do_product_lookup(device_t bus, device_t dev,
+		      const struct pccard_product *tab,
+		      size_t ent_size, pccard_product_match_fn matchfn)
 {
 	return (NULL);
 }
@@ -415,6 +430,7 @@
 	DEVMETHOD(card_deactivate_function, pccard_deactivate_function),
 	DEVMETHOD(card_compat_do_probe, pccard_compat_do_probe),
 	DEVMETHOD(card_compat_do_attach, pccard_compat_do_attach),
+	DEVMETHOD(card_do_product_lookup, pccard_do_product_lookup),
 #endif
 	{ 0, 0 }
 };
Index: pccard/pccard_nbk.h
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/pccard_nbk.h,v
retrieving revision 1.4.2.1
diff -u -r1.4.2.1 pccard_nbk.h
--- pccard/pccard_nbk.h	5 Jun 2001 19:16:37 -0000	1.4.2.1
+++ pccard/pccard_nbk.h	1 Sep 2002 04:35:57 -0000
@@ -28,6 +28,8 @@
 #ifndef PCCARD_PCCARD_NBK_H
 #define PCCARD_PCCARD_NBK_H
 
+SYSCTL_DECL(_machdep_pccard);
+
 struct pccard_device;
 extern devclass_t pccard_devclass;
 
Index: pccard/pcic.c
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/pcic.c,v
retrieving revision 1.89.2.26
diff -u -r1.89.2.26 pcic.c
--- pccard/pcic.c	7 Jul 2002 18:52:28 -0000	1.89.2.26
+++ pccard/pcic.c	1 Sep 2002 04:35:57 -0000
@@ -92,7 +92,27 @@
 TUNABLE_INT("hw.pcic.boot_deactivated", &pcic_boot_deactivated);
 SYSCTL_INT(_hw_pcic, OID_AUTO, boot_deactivated, CTLFLAG_RD,
     &pcic_boot_deactivated, 0,
-    "Override the automatic powering up of pccards at boot.");
+    "Override the automatic powering up of pccards at boot.  This works\n\
+around what turns out to be an old bug in the code that has since been\n\
+corrected.  It is now deprecated and will be removed completely before\n\
+FreeBSD 4.8.");
+
+/*
+ * CL-PD6722's VSENSE method
+ *     0: NO VSENSE (assume a 5.0V card)
+ *     1: 6710's method (default)
+ *     2: 6729's method
+ */
+int pcic_pd6722_vsense = 1;
+TUNABLE_INT("hw.pcic.pd6722_vsense", &pcic_pd6722_vsense);
+SYSCTL_INT(_hw_pcic, OID_AUTO, pd6722_vsense, CTLFLAG_RD,
+    &pcic_pd6722_vsense, 1,
+    "Select CL-PD6722's VSENSE method.  VSENSE is used to determine the\n\
+volatage of inserted cards.  The CL-PD6722 has two methods to determine the\n\
+voltage of the card.  0 means assume a 5.0V card and do not check.  1 means\n\
+use the same method that the CL-PD6710 uses (default).  2 means use the\n\
+same method as the CL-PD6729.  2 is documented in the datasheet as being\n\
+the correct way, but 1 seems to give better results on more laptops.");
 
 /*
  * Read a register from the PCIC.
@@ -203,14 +223,25 @@
 	}
 	if (mp->flags & MDF_ACTIVE) {
 		unsigned long sys_addr = (uintptr_t)(void *)mp->start >> 12;
+		if ((sys_addr >> 12) != 0 && 
+		    (sp->sc->flags & PCIC_YENTA_HIGH_MEMORY) == 0) {
+			printf("This pcic does not support mapping > 24M\n");
+			return (ENXIO);
+		}
 		/*
 		 * Write the addresses, card offsets and length.
 		 * The values are all stored as the upper 12 bits of the
 		 * 24 bit address i.e everything is allocated as 4 Kb chunks.
+		 * Memory mapped cardbus bridges extend this slightly to allow
+		 * one to set the upper 8 bits of the 32bit address as well.
+		 * If the chip supports it, then go ahead and write those
+		 * upper 8 bits.
 		 */
 		pcic_putw(sp, reg, sys_addr & 0xFFF);
 		pcic_putw(sp, reg+2, (sys_addr + (mp->size >> 12) - 1) & 0xFFF);
 		pcic_putw(sp, reg+4, ((mp->card >> 12) - sys_addr) & 0x3FFF);
+		if (sp->sc->flags & PCIC_YENTA_HIGH_MEMORY)
+		    sp->putb(sp, PCIC_MEMORY_HIGH0 + win, sys_addr >> 12);
 		/*
 		 *	Each 16 bit register has some flags in the upper bits.
 		 */
@@ -389,6 +420,7 @@
 		/* Check for changes */
 		sp->slt->laststate = sp->slt->state = empty;
 		if (pcic_boot_deactivated) {
+			sp->putb(sp, PCIC_POWER, 0);
 			if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD) {
 				sp->slt->state = inactive;
 				pccard_event(sp->slt, card_deactivated);
@@ -638,7 +670,8 @@
 	struct pcic_slot *sp2;
 	struct pcic_softc *sc = sp->sc;
 	int dodefault = 0;
-
+	char controller;
+	
 	/*
 	 * Cardbus power registers are completely different.
 	 */
@@ -667,26 +700,39 @@
 		if (sc->flags & PCIC_PD_POWER) {
 			/*
 			 * The 6710 does it one way, and the '22 and '29 do it
-			 * another.  And it appears that the '32 and '33 yet
-			 * another way (which I don't know).  The '22 can also
-			 * do it the same way as a '10 does it, despite what
-			 * the datasheets say.  Some laptops with '22 don't
-			 * seem to have the signals wired right for the '29
-			 * method to work, so we always use the '10 method for
-			 * the '22.  The laptops that don't work hang solid
-			 * when the pccard memory is accessed.  The '32 and
-			 * '33 cases are taken care of in cardbus code, so
-			 * it doesn't matter that I have no clue.
+			 * another.  The '22 can also do it the same way as a
+			 * '10 does it, despite what the datasheets say.  Some
+			 * laptops with '22 don't seem to have the signals
+			 * wired right for the '29 method to work.  The
+			 * laptops that don't work hang solid when the pccard
+			 * memory is accessed.
+			 *
+			 * To allow for both types of laptops,
+			 * hw.pcic.pd6722_vsense will select which one to use.
+			 * 0 - none, 1 - the '10 way and 2 - the '29 way.
 			 */
-			switch (sp->controller) {
+			controller = sp->controller;
+			if (controller == PCIC_PD6722) {
+				switch (pcic_pd6722_vsense) {
+				case 1:
+					controller = PCIC_PD6710;
+					break;
+				case 2:
+					controller = PCIC_PD6729;
+					break;
+				}
+			}
+
+			switch (controller) {
 			case PCIC_PD6710:
-			case PCIC_PD6722:
 				c = sp->getb(sp, PCIC_MISC1);
 				if ((c & PCIC_MISC1_5V_DETECT) == 0)
 					slt->pwr.vcc = 33;
 				else
 					slt->pwr.vcc = 50;
 				break;
+			case PCIC_PD6722:	/* see above for why we do */
+ 				break;		/* none here */
 			case PCIC_PD6729:
 				/*
 				 * VS[12] signals are in slot1's
@@ -703,7 +749,7 @@
 					slt->pwr.vcc = 50;
 				break;
 			default:
-				/* I have no idea how do do this for others */
+				/* I have no idea how to do this for others */
 				break;
 			}
 
@@ -1282,7 +1328,6 @@
 pcic_isa_mapirq(struct pcic_slot *sp, int irq)
 {
 	irq = host_irq_to_pcic(irq);
-	sp->sc->chip->func_intr_way(sp, pcic_iw_isa);
 	if (irq == 0)
 		pcic_clrb(sp, PCIC_INT_GEN, 0xF);
 	else
Index: pccard/pcic_pci.c
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/pcic_pci.c,v
retrieving revision 1.54.2.20
diff -u -r1.54.2.20 pcic_pci.c
--- pccard/pcic_pci.c	7 Jul 2002 18:52:29 -0000	1.54.2.20
+++ pccard/pcic_pci.c	1 Sep 2002 04:35:57 -0000
@@ -65,7 +65,8 @@
 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RD,
     &pcic_ignore_function_1, 0,
-    "When set, driver ignores pci function 1 of the bridge");
+    "When set, driver ignores pci function 1 of the bridge.  This option\n\
+is obsolete and will be deleted before FreeBSD 4.8.");
 
 /*
  * The following should be a hint, so we can do it on a per device
@@ -76,22 +77,39 @@
 static int pcic_intr_path = (int)pcic_iw_pci;
 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RD, &pcic_intr_path, 0,
-    "Which path to send the interrupts over.");
+    "Which path to send the interrupts over.  Normally interrupts for\n\
+cardbus bridges are routed over the PCI bus (2).  However, some laptops\n\
+will hang when using PCI interrupts due to bugs in this code.  Those\n\
+bugs can be worked around by forcings ISA interrupts (1).");
 
 static int pcic_init_routing = 0;
 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RD,
     &pcic_init_routing, 0,
     "Force the interrupt routing to be initialized on those bridges where\n\
-doing so will cause probelms.  Often when no interrupts appear to be routed\n\
-setting this tunable to 1 will resolve the problem.  PCI Cards will almost\n\
-always require this, while builtin bridges need it less often");
+doing so will cause probelms.  This is very rare and generally is not\n\
+needed.  The default of 0 is almost always appropriate.  Only set to 1 if\n\
+instructed to do so for debugging.  Only TI bridges are affected by this\n\
+option, and what the code does is of dubious value.  This option is obsolete\n\
+and will be deleted before FreeBSD 4.8.");
 
 static int pcic_ignore_pci = 0;
 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD,
     &pcic_ignore_pci, 0,
-    "When set, driver ignores pci cardbus bridges it would otherwise claim.");
+    "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
+Generally speaking, this option is not needed for anything other than as an\n\
+aid in debugging.");
+
+static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
+TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
+SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RD,
+    &pcic_pd6729_intr_path, 0,
+  "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
+similar I/O space based pcmcia bridge.  Chips on a PCI expansion card need\n\
+a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
+also the default).  This is similar to hw.pcic.intr_path, but separate so\n\
+that it can default to ISA when intr_path defaults to PCI.");
 
 static void pcic_pci_cardbus_init(device_t);
 static pcic_intr_way_t pcic_pci_gen_func;
@@ -192,6 +210,9 @@
 	pcic_pci_cardbus_init
 };
 
+/* Chipset specific flags */
+#define TI_NO_MFUNC	0x10000
+
 struct pcic_pci_table
 {
 	u_int32_t	devid;
@@ -200,134 +221,101 @@
 	u_int32_t	flags;
 	struct pcic_chip *chip;
 } pcic_pci_devs[] = {
-	{ PCI_DEVICE_ID_OMEGA_82C094,
-	  "Omega 82C094G",
+	{ PCIC_ID_OMEGA_82C094, "Omega 82C094G",
 	  PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd67xx_chip },
-	{ PCI_DEVICE_ID_PCIC_CLPD6729,
-	  "Cirrus Logic PD6729/6730 PC-Card Controller",
+	{ PCIC_ID_CLPD6729, "Cirrus Logic PD6729/6730 PCI-PCMCIA Bridge",
 	  PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd67xx_chip },
-	{ PCI_DEVICE_ID_PCIC_CLPD6832,
-	  "Cirrus Logic PD6832 PCI-CardBus Bridge",
+	{ PCIC_ID_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge",
 	  PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_CLPD6833,
-	  "Cirrus Logic PD6833 PCI-CardBus Bridge",
+	{ PCIC_ID_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge",
 	  PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_CLPD6834,
-	  "Cirrus Logic PD6834 PCI-CardBus Bridge",
+	{ PCIC_ID_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge",
 	  PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6729,
-	  "O2micro OZ6729 PC-Card Bridge",
+	{ PCIC_ID_OZ6729, "O2micro OZ6729 PC-Card Bridge",
 	  PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6730,
-	  "O2micro OZ6730 PC-Card Bridge",
+	{ PCIC_ID_OZ6730, "O2micro OZ6730 PC-Card Bridge",
 	  PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6832,
-	  "O2micro 6832/6833 PCI-Cardbus Bridge",
+	{ PCIC_ID_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6860,
-	  "O2micro 6836/6860 PCI-Cardbus Bridge",
+	{ PCIC_ID_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6872,
-	  "O2micro 6812/6872 PCI-Cardbus Bridge",
+	{ PCIC_ID_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6912,
-	  "O2micro 6912 PCI-Cardbus Bridge",
+	{ PCIC_ID_OZ6912, "O2micro 6912 PCI-Cardbus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6922,
-	  "O2micro 6922 PCI-Cardbus Bridge",
+	{ PCIC_ID_OZ6922, "O2micro 6922 PCI-Cardbus Bridge",
 	  PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
-	{ PCI_DEVICE_ID_PCIC_OZ6933,
-	  "O2micro 6933 PCI-Cardbus Bridge",
+	{ PCIC_ID_OZ6933, "O2micro 6933 PCI-Cardbus Bridge",
 	  PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
-	{ PCI_DEVICE_ID_RICOH_RL5C465,
-	  "Ricoh RL5C465 PCI-CardBus Bridge",
+	{ PCIC_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge",
 	  PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
-	{ PCI_DEVICE_ID_RICOH_RL5C475,
-	  "Ricoh RL5C475 PCI-CardBus Bridge",
+	{ PCIC_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge",
 	  PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
-	{ PCI_DEVICE_ID_RICOH_RL5C476,
-	  "Ricoh RL5C476 PCI-CardBus Bridge",
+	{ PCIC_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge",
 	  PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
-	{ PCI_DEVICE_ID_RICOH_RL5C477,
-	  "Ricoh RL5C477 PCI-CardBus Bridge",
+	{ PCIC_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge",
 	  PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
-	{ PCI_DEVICE_ID_RICOH_RL5C478,
-	  "Ricoh RL5C478 PCI-CardBus Bridge",
+	{ PCIC_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge",
 	  PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1031,
-	  "TI PCI-1031 PCI-PCMCIA Bridge",
+	{ PCIC_ID_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1130,
-	  "TI PCI-1130 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1130, "TI PCI-1130 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1131,
-	  "TI PCI-1131 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1131, "TI PCI-1131 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1210,
-	  "TI PCI-1210 PCI-CardBus Bridge",
-	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1211,
-	  "TI PCI-1211 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1210, "TI PCI-1210 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1220,
-	  "TI PCI-1220 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1211, "TI PCI-1211 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1221,
-	  "TI PCI-1221 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1220, "TI PCI-1220 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1225,
-	  "TI PCI-1225 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1221, "TI PCI-1221 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1250,
-	  "TI PCI-1250 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1225, "TI PCI-1225 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1251,
-	  "TI PCI-1251 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1250, "TI PCI-1250 PCI-CardBus Bridge",
+	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
+	  &pcic_pci_ti12xx_chip },
+	{ PCIC_ID_TI1251, "TI PCI-1251 PCI-CardBus Bridge",
+	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
+	  &pcic_pci_ti12xx_chip },
+	{ PCIC_ID_TI1251B, "TI PCI-1251B PCI-CardBus Bridge",
+	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
+	  &pcic_pci_ti12xx_chip },
+	{ PCIC_ID_TI1260, "TI PCI-1260 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1251B,
-	  "TI PCI-1251B PCI-CardBus Bridge",
+	{ PCIC_ID_TI1260B, "TI PCI-1260B PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1260,
-	  "TI PCI-1260 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1410, "TI PCI-1410 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1260B,
-	  "TI PCI-1260B PCI-CardBus Bridge",
+	{ PCIC_ID_TI1420, "TI PCI-1420 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1410,
-	  "TI PCI-1410 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1421, "TI PCI-1421 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1420,
-	  "TI PCI-1420 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1450, "TI PCI-1450 PCI-CardBus Bridge",
+	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
+	  &pcic_pci_ti12xx_chip },
+	{ PCIC_ID_TI1451, "TI PCI-1451 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1421,
-	  "TI PCI-1421 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1510, "TI PCI-1510 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1450,
-	  "TI PCI-1450 PCI-CardBus Bridge",
+	{ PCIC_ID_TI1520, "TI PCI-1520 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI1451,
-	  "TI PCI-1451 PCI-CardBus Bridge",
+	{ PCIC_ID_TI4410, "TI PCI-4410 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI4410,
-	  "TI PCI-4410 PCI-CardBus Bridge",
+	{ PCIC_ID_TI4450, "TI PCI-4450 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI4450,
-	  "TI PCI-4450 PCI-CardBus Bridge",
+	{ PCIC_ID_TI4451, "TI PCI-4451 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_PCIC_TI4451,
-	  "TI PCI-4451 PCI-CardBus Bridge",
+	{ PCIC_ID_TI4510, "TI PCI-4510 PCI-CardBus Bridge",
 	  PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
-	{ PCI_DEVICE_ID_TOSHIBA_TOPIC95,
-	  "Toshiba ToPIC95 PCI-CardBus Bridge",
+	{ PCIC_ID_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
-	{ PCI_DEVICE_ID_TOSHIBA_TOPIC95B,
-	  "Toshiba ToPIC95B PCI-CardBus Bridge",
+	{ PCIC_ID_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
-	{ PCI_DEVICE_ID_TOSHIBA_TOPIC97,
-	  "Toshiba ToPIC97 PCI-CardBus Bridge",
+	{ PCIC_ID_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
-	{ PCI_DEVICE_ID_TOSHIBA_TOPIC100,
-	  "Toshiba ToPIC100 PCI-CardBus Bridge",
+	{ PCIC_ID_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge",
 	  PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
 	{ 0, NULL, 0, 0, NULL }
 };
@@ -454,15 +442,25 @@
 
 /*
  * The Cirrus Logic PD6729/30.  These are weird beasts, so be careful.
+ * They are ISA parts glued to the PCI bus and do not follow the yenta
+ * specification for cardbus bridges.  They seem to be similar to the
+ * intel parts that were also cloned by o2micro and maybe others, but
+ * they are so much more common that the author doesn't have experience
+ * with them to know for sure.
  */
 static int
 pcic_pci_pd67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
 {
 	/*
-	 * We're only supporting ISA interrupts, so do nothing for the
-	 * moment.
+	 * For pci interrupts, we need to set bit 3 of extension register
+	 * 3 to 1.  For ISA interrupts, we need to clear it.
 	 */
-	/* XXX */
+	sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
+	if (way == pcic_iw_pci)
+		pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
+	else
+		pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
+
 	return (0);
 }
 
@@ -470,10 +468,15 @@
 pcic_pci_pd67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
 {
 	/*
-	 * We're only supporting ISA interrupts, so do nothing for the
-	 * moment.
+	 * For pci interrupts, we need to set bit 4 of extension register
+	 * 3 to 1.  For ISA interrupts, we need to clear it.
 	 */
-	/* XXX */
+	sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
+	if (way == pcic_iw_pci)
+		pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
+	else
+		pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
+
 	return (0);
 }
 
@@ -484,7 +487,7 @@
 	struct pcic_softc *sc = device_get_softc(dev);
 
 	if (sc->csc_route == pcic_iw_pci || sc->func_route == pcic_iw_pci)
-		device_printf(dev, "CL-PD67xx broken for PCI routing.\n");
+		device_printf(dev, "PD67xx maybe broken for PCI routing.\n");
 }
 
 /*
@@ -518,7 +521,7 @@
 	 *
 	 * I'm assuming that the CLPD6834 does things like the '33
 	 */
-	if (device_id == PCI_DEVICE_ID_PCIC_CLPD6832) {
+	if (device_id == PCIC_ID_CLPD6832) {
 		bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
 		if (way == pcic_iw_pci)
 			bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
@@ -526,7 +529,7 @@
 			bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
 		pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
 	}
-	if (device_id != PCI_DEVICE_ID_PCIC_CLPD6832) {
+	if (device_id != PCIC_ID_CLPD6832) {
 		cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
 		if (way == pcic_iw_pci)
 			cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
@@ -579,8 +582,8 @@
 	u_int32_t	device_id = pci_get_devid(dev);
 
 	switch (device_id) {
-	case PCI_DEVICE_ID_RICOH_RL5C465:
-	case PCI_DEVICE_ID_RICOH_RL5C466:
+	case PCIC_ID_RICOH_RL5C465:
+	case PCIC_ID_RICOH_RL5C466:
 		/*
 		 * Ricoh chips have a legacy bridge enable different than most
 		 * Code cribbed from NEWBUS's bridge code since I can't find a
@@ -666,6 +669,67 @@
 static int
 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
 {
+	u_int32_t	syscntl, devcntl, cardcntl, mfunc;
+	device_t	dev = sp->sc->dev;
+
+	syscntl  = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
+	devcntl  = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
+	cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL,   1);
+
+	/*
+	 * Special code for the Orinoco cards (and a few others).  They
+	 * seem to need this special code to make them work only over pci
+	 * interrupts.  Sadly, doing this code also causes problems for
+	 * many laptops, so we have to make it controlled by a tunable.
+	 * Actually, experience has shown that this rarely, if ever,
+	 * helps.
+	 */
+	if (way == pcic_iw_pci) {
+		/*
+		 * pcic_init_routing seems to do nothing useful towards
+		 * fixing the hang problems.  I plan on removing it in
+		 * 4.8 or so.
+		 */
+		if (pcic_init_routing) {
+			devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
+			pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
+			    devcntl, 1);
+			syscntl |= TI113X_SYSCNTL_INTRTIE;
+		}
+		/* 
+		 * I'm not sure that this helps/hurts things at all and
+		 * plan on removing it in the 4.8 time frame unless someone
+		 * can show that it really helps.
+		 */
+		syscntl &= ~TI113X_SYSCNTL_SMIENB;
+		pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL, syscntl, 1);
+
+		/*
+		 * Some PCI add-in cards don't have good EEPROMs on them,
+		 * so they get this MUX register wrong.  The MUX register
+		 * defaults to 0, which is usually wrong for this register,
+		 * so we initialize it to make sense.
+		 *
+		 * We don't bother to turn it off in the ISA case since it
+		 * is an initialization issue.
+		 *
+		 * A few weird TI bridges don't have MFUNC, so filter
+		 * those out too.
+		 */
+		if ((sp->sc->flags & TI_NO_MFUNC) == 0) {
+			mfunc  = pci_read_config(dev, TI12XX_PCI_MFUNC, 4);
+			if (mfunc == 0) {
+				mfunc = (mfunc & ~TI12XX_MFUNC_PIN0) |
+				    TI12XX_MFUNC_PIN0_INTA;
+				if ((syscntl & TI113X_SYSCNTL_INTRTIE) == 0)
+					mfunc = (mfunc & ~TI12XX_MFUNC_PIN1) |
+					    TI12XX_MFUNC_PIN1_INTB;
+				pci_write_config(dev, TI12XX_PCI_MFUNC, mfunc,
+				    4);
+			}
+		}
+		
+	}
 	return (pcic_pci_gen_func(sp, way));
 }
 
@@ -694,10 +758,9 @@
 {
 	u_int32_t	syscntl, diagctl, devcntl, cardcntl;
 	u_int32_t	device_id = pci_get_devid(dev);
-	struct pcic_softc *sc = device_get_softc(dev);
-	int	 	ti113x = (device_id == PCI_DEVICE_ID_PCIC_TI1031) ||
-	    (device_id == PCI_DEVICE_ID_PCIC_TI1130) ||
-	    (device_id == PCI_DEVICE_ID_PCIC_TI1131);
+	int	 	ti113x = (device_id == PCIC_ID_TI1031) ||
+	    (device_id == PCIC_ID_TI1130) ||
+	    (device_id == PCIC_ID_TI1131);
 
 	syscntl  = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
 	devcntl  = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
@@ -729,28 +792,10 @@
 		 * register doesn't exist on the 1130 (and likely the 1131,
 		 * but without a datasheet it is impossible to know).
 		 * Some 12xx chips may not have it, but setting it is
-		 * believed to be harmless.
+		 * believed to be harmless on those models.
 		 */
 		pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
 	}
-	/*
-	 * Special code for the Orinoco cards (and a few others).  They
-	 * seem to need this special code to make them work only over pci
-	 * interrupts.  Sadly, doing this code also causes problems for
-	 * many laptops, so we have to make it controlled by a tunable.
-	 */
-	if (sc->func_route == pcic_iw_pci) {
-		if (pcic_init_routing) {
-			devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
-			pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
-			    devcntl, 1);
-			devcntl = pci_read_config(dev,
-			    TI113X_PCI_DEVICE_CONTROL, 1);
-			syscntl |= TI113X_SYSCNTL_INTRTIE;
-		}
-		syscntl &= ~TI113X_SYSCNTL_SMIENB;
-		pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL, syscntl, 1);
-	}
 	if (cardcntl & TI113X_CARDCNTL_RING_ENA)
 		printf("[ring enable]");
 	if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
@@ -803,8 +848,7 @@
 	u_int32_t device_id;
 
 	device_id = pci_get_devid(dev);
-	if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 ||
-	    device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) {
+	if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
 		scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
 		if (way == pcic_iw_pci)
 			scr |= TOPIC97_SLOT_CTRL_PCIINT;
@@ -828,16 +872,14 @@
 	reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 
 	    TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
 	reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
-	if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 ||
-	    device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) {
+	if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
 		reg |= TOPIC97_SLOT_CTRL_PCIINT;
 		reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
 	}
 	pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
 	pcic_pci_cardbus_init(dev);
 
-	if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 ||
-	    device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) {
+	if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
 		/*
 		 * We need to enable voltage sense and 3V cards explicitly
 		 * in the bridge.  The datasheets I have for both the
@@ -882,10 +924,9 @@
 	pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
 
 	/*
-	 * Force the function interrupts to be pulse rather than
-	 * edge triggered.
+	 * Tell the chip to do its routing thing.
 	 */
-	sc->chip->func_intr_way(&sc->slots[0], pcic_iw_isa);
+	sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
 	sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
 
 	return;
@@ -1053,18 +1094,24 @@
 	 * We only need to route interrupts when we're doing pci
 	 * parallel interrupt routing.
 	 *
-	 * Note: The CLPD6729 is a special case.  See its init function
-	 * for an explaination of ISA vs PCI interrupts. XXX Might be other
-	 * special cases as well.
+	 * We use two different variables for the memory based and I/O
+	 * based cards, so the check here is a little more complex than
+	 * one would otherwise hope.
+	 *
+	 * XXX The bus code for PCI really should do this for us.
 	 */
-	if (pcic_intr_path == pcic_iw_pci && 
-	    device_id != PCI_DEVICE_ID_PCIC_CLPD6729) {
+	if ((pcic_intr_path == pcic_iw_pci && 
+	    device_id != PCIC_ID_CLPD6729) ||
+	  (pcic_pd6729_intr_path == pcic_iw_pci &&
+	    device_id == PCIC_ID_CLPD6729)) {
 		rid = 0;
 #ifdef __i386__
 		/*
 		 * IRQ 0 is invalid on x86, but not other platforms.
 		 * If we have irq 0, then write 255 to force a new, non-
-		 * bogus one to be assigned.
+		 * bogus one to be assigned.  I think that in -current
+		 * the code in this ifdef may be obsolete with the new
+		 * invalid mapping that we're doing in the pci layer -- imp
 		 */
 		if (pci_get_irq(dev) == 0) {
 			pci_set_irq(dev, 255);
@@ -1094,12 +1141,6 @@
 	sp = &sc->slots[0];
 
 	/*
-	 * Make the chips use ISA again.
-	 */
-	sc->chip->func_intr_way(&sc->slots[0], pcic_iw_isa);
-	sc->chip->csc_intr_way(&sc->slots[0], pcic_iw_isa);
-
-	/*
 	 * Turn off the power to the slot in an attempt to
 	 * keep the system from hanging on reboot.  We also turn off
 	 * card interrupts in an attempt to control interrupt storms.
@@ -1150,9 +1191,8 @@
 }
 
 /*
- * General PCI based card dispatch routine.  Right now
- * it only understands the Ricoh, CL-PD6832 and TI parts.  It does
- * try to do generic things with other parts.
+ * Generic pci interrupt attach routine.  It tries to understand all parts,
+ * and do sane things for those parts it does not understand.
  */
 static int
 pcic_pci_attach(device_t dev)
@@ -1190,6 +1230,7 @@
 		    &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
 		if (sc->iores == NULL)
 			return (ENOMEM);
+
 		sc->flags = PCIC_PD_POWER;
 		itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
 		for (i = 0; i < 2; i++) {
@@ -1204,17 +1245,17 @@
 			if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
 				sp[i].slt = (struct slot *) 1;
 		}
-		/*
-		 * We only support isa at this time.  These cards can be
-		 * wired up as either ISA cards *OR* PCI cards (well, weird
-		 * hybrids are possible, but not seen in the wild).  Since it
-		 * is an either or thing, we assume ISA since all laptops that
-		 * we supported in 4.3 and earlier work.
-		 */ 
-		sc->csc_route = pcic_iw_isa;
-		sc->func_route = pcic_iw_isa;
+		sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
 		if (itm)
 			sc->flags = itm->flags;
+		/*
+		 * We have to use the ISA interrupt routine for status
+		 * changes since we don't have any "yenta" pci registers.
+		 * We have to do this even when we're using pci type
+		 * interrupts because on these cards the interrupts are
+		 * cleared in the same way that the ISA cards clear them.
+		 */
+		intr = pcic_isa_intr;
 	} else {
 		sc->memrid = CB_PCI_SOCKET_BASE;
 		sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
@@ -1237,6 +1278,8 @@
 			sp->revision = 0;
 			sc->flags = PCIC_CARDBUS_POWER;
 		}
+		/* All memory mapped cardbus bridges have these registers */
+		sc->flags |= PCIC_YENTA_HIGH_MEMORY;
 		sp->slt = (struct slot *) 1;
 		sc->csc_route = pcic_intr_path;
 		sc->func_route = pcic_intr_path;
@@ -1259,7 +1302,8 @@
 			device_printf(dev,
 			    "No PCI interrupt routed, trying ISA.\n");
 		} else {
-			intr = pcic_pci_intr;
+			if (intr == NULL)
+				intr = pcic_pci_intr;
 			irq = rman_get_start(r);
 		}
 	}
@@ -1277,7 +1321,8 @@
 			}
 			device_printf(dev,
 			    "Management interrupt on ISA IRQ %ld\n", irq);
-			intr = pcic_isa_intr;
+			if (intr == NULL)
+				intr = pcic_isa_intr;
 		} else {
 			sc->slot_poll = pcic_timeout;
 			sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
@@ -1360,13 +1405,30 @@
 	/*
 	 * If we're doing ISA interrupt routing, then just go to the
 	 * generic ISA routine.  Also, irq 0 means turn off the interrupts
-	 * at the bridge.  We do this by making the interrupts edge
-	 * triggered rather then level.
+	 * at the bridge.
 	 */
 	if (sp->sc->func_route == pcic_iw_isa || irq == 0)
 		return (pcic_isa_mapirq(sp, irq));
 
-	return (sp->sc->chip->func_intr_way(sp, pcic_iw_pci));
+	/*
+	 * Ohterwise we're doing PCI interrupts.  For those cardbus bridges
+	 * that follow yenta (and the one pcmcia bridge that does), we don't
+	 * do a thing to get the IRQ mapped into the system.  However,
+	 * for other controllers that are PCI, but not yetna compliant, we
+	 * need to do some special mapping.
+	 */
+	if (sp->controller == PCIC_PD6729) {
+		/*
+		 * INTA - 3
+		 * INTB - 4
+		 * INTC - 5
+		 * INTD - 7
+		 */
+		sp->putb(sp, PCIC_INT_GEN,	/* Assume INTA# */
+		    (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
+		return (0);
+	}
+	return (0);
 }
 
 static void
@@ -1375,9 +1437,24 @@
 	struct pcic_softc *sc = (struct pcic_softc *) arg;
 	struct pcic_slot *sp = &sc->slots[0];
 	u_int32_t stat;
+	int doit = 0;
 
-	stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
-	if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
+	/*
+	 * The 6729 controller is a weird one, and we have to use
+	 * the ISA registers to check to see if the card is there.
+	 * Otherwise we look at the PCI state register to find out
+	 * if the card is there.
+	 */ 
+	if (sp->controller == PCIC_PD6729) {
+		if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
+			doit = 1;
+	}
+	else {
+		stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
+		if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
+			doit = 1;
+	}
+	if (doit && sc->func_intr != NULL)
 		sc->func_intr(sc->func_arg);
 }
 	
Index: pccard/pcic_pci.h
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/pcic_pci.h,v
retrieving revision 1.23.2.10
diff -u -r1.23.2.10 pcic_pci.h
--- pccard/pcic_pci.h	7 Jul 2002 18:52:29 -0000	1.23.2.10
+++ pccard/pcic_pci.h	1 Sep 2002 04:35:57 -0000
@@ -43,6 +43,7 @@
 /* Texas Instruments PCI-1130/1131 CardBus Controller */
 #define TI113X_PCI_SYSTEM_CONTROL	0x80	/* System Control */
 #define TI12XX_PCI_MULTIMEDIA_CONTROL	0x84	/* Zoom Video */
+#define TI12XX_PCI_MFUNC		0x8c	/* multifunction pins */
 #define TI113X_PCI_RETRY_STATUS		0x90	/* Retry Status */
 #define TI113X_PCI_CARD_CONTROL		0x91	/* Card Control */
 #define TI113X_PCI_DEVICE_CONTROL	0x92	/* Device Control */
@@ -59,6 +60,17 @@
 #define	TI113X_SYSCNTL_PWRSAVINGS	0x00000040u
 #define TI113X_SYSCNTL_KEEP_CLK		0x00000002u
 #define TI113X_SYSCNTL_CLKRUN_ENA	0x00000001u
+
+/* MFUNC register (TI12XX_MFUNC == 0x8c) */
+#define TI12XX_MFUNC_PIN0		0x0000000fu
+#define   TI12XX_MFUNC_PIN0_INTA	0x2
+#define TI12XX_MFUNC_PIN1		0x000000f0u
+#define   TI12XX_MFUNC_PIN1_INTB	0x20
+#define TI12XX_MFUNC_PIN2		0x00000f00u
+#define TI12XX_MFUNC_PIN3		0x0000f000u
+#define TI12XX_MFUNC_PIN4		0x000f0000u
+#define TI12XX_MFUNC_PIN5		0x00f00000u
+#define TI12XX_MFUNC_PIN6		0x0f000000u
 
 /* Card control register (TI113X_CARD_CONTROL == 0x91) */
 #define TI113X_CARDCNTL_RING_ENA	0x80u
Index: pccard/pcicvar.h
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/pcicvar.h,v
retrieving revision 1.15.2.10
diff -u -r1.15.2.10 pcicvar.h
--- pccard/pcicvar.h	13 Sep 2001 17:54:50 -0000	1.15.2.10
+++ pccard/pcicvar.h	1 Sep 2002 04:35:57 -0000
@@ -52,6 +52,7 @@
 #define PCIC_KING_POWER    0x00000010	/* Uses IBM KING regs  */
 #define PCIC_RICOH_POWER   0x00000020	/* Uses the ricoh power regs */
 #define PCIC_CARDBUS_POWER 0x00000040	/* Cardbus power regs */
+#define PCIC_YENTA_HIGH_MEMORY 0x0080	/* Can do high memory mapping */
 
 	enum pcic_intr_way	csc_route; /* How to route csc interrupts */
 	enum pcic_intr_way	func_route; /* How to route function ints */
Index: pccard/slot.h
===================================================================
RCS file: /cache/ncvs/src/sys/pccard/slot.h,v
retrieving revision 1.25.2.4
diff -u -r1.25.2.4 slot.h
--- pccard/slot.h	30 Jul 2001 00:11:29 -0000	1.25.2.4
+++ pccard/slot.h	1 Sep 2002 04:35:57 -0000
@@ -86,11 +86,15 @@
  *	devices together.
  */
 struct pccard_devinfo {
-	u_char	name[128];
-	int running;			/* Current state of driver */
-	u_char	misc[128];		/* For any random info */
-	struct slot *slt;		/* Back pointer to slot */
-
+	uint8_t		name[128];
+	int		running;	/* Current state of driver */
+	uint8_t		misc[DEV_MISC_LEN]; /* For any random info */
+	uint8_t		manufstr[DEV_MAX_CIS_LEN];
+	uint8_t		versstr[DEV_MAX_CIS_LEN];
+	uint32_t	manufacturer;	/* Manufacturer ID */
+	uint32_t	product;	/* Product ID */
+	uint32_t	prodext;	/* Product ID (extended) */
+	struct slot	*slt;		/* Back pointer to slot */
 	struct resource_list resources;
 };