Index: at91_pmcreg.h
===================================================================
--- at91_pmcreg.h	(revision 238879)
+++ at91_pmcreg.h	(working copy)
@@ -57,6 +57,11 @@
 #define PMC_IDR		0x64		/* Interrupt Disable Register */
 #define PMC_SR		0x68		/* Status Register */
 #define PMC_IMR		0x6c		/* Interrupt Mask Register */
+		/*	0x70		   reserved */
+		/*	0x74		   reserved */
+		/*	0x78		   reserved */
+		/*	0x7c		   reserved */
+#define	PMC_PLLICPR	0x80		/* PLL Charge Pump Current Register */
 
 /* PMC System Clock Enable Register */
 /* PMC System Clock Disable Register */
Index: at91sam9x5.c
===================================================================
--- at91sam9x5.c	(revision 238922)
+++ at91sam9x5.c	(working copy)
@@ -125,21 +125,29 @@
 	{ 0, 0, 0, 0, 0 }
 };
 
+/*
+ * The following is unused currently since we don't ever set the PLLA
+ * frequency of the device.  If we did, we'd have to also pay attention
+ * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower
+ * than ~600MHz, which the PMC code doesn't do right now.
+ * XXX this likely should be in at91_pmc as at91_pmc_800mhz_plla_outa.
+ */
 static uint32_t
 at91_pll_outa(int freq)
 {
+	uint32_t outa;
 
-	switch (freq / 10000000) {
-		case 747 ... 801: return ((1 << 29) | (0 << 14));
-		case 697 ... 746: return ((1 << 29) | (1 << 14));
-		case 647 ... 696: return ((1 << 29) | (2 << 14));
-		case 597 ... 646: return ((1 << 29) | (3 << 14));
-		case 547 ... 596: return ((1 << 29) | (1 << 14));
-		case 497 ... 546: return ((1 << 29) | (2 << 14));
-		case 447 ... 496: return ((1 << 29) | (3 << 14));
-		case 397 ... 446: return ((1 << 29) | (4 << 14));
-		default: return (1 << 29);
-	}
+	/*
+	 * Set OUTA, per the data sheet.  See Table 46-16 titled
+	 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9X25 doc.
+	 * Note: the frequencies overlap by 5MHz, so we add 3 here to
+	 * center shoot the transition.
+	 */
+
+	freq /= 1000000;		/* MHz */
+	freq -= 3;			/* Allow for overlap. */
+	outa = 3 - ((freq / 50) & 3);	/* 750 / 50 = 7, see table */
+	return (1 << 29)| (outa << 14);
 }
 
 static uint32_t
Index: at91sam9260.c
===================================================================
--- at91sam9260.c	(revision 238879)
+++ at91sam9260.c	(working copy)
@@ -116,27 +116,35 @@
 	DEVICE("spi",  SPI0,   0),
 	DEVICE("spi",  SPI1,   1),
 	DEVICE("ate",  EMAC,   0),
-	DEVICE("macb", EMAC,   0),
 	DEVICE("nand", NAND,   0),
 	DEVICE("ohci", OHCI,   0),
 	{ 0, 0, 0, 0, 0 }
 };
 
+/*
+ * The following is unused currently since we don't ever set the PLLA
+ * frequency of the device.
+ */
 static uint32_t
 at91_pll_outa(int freq)
 {
+	uint32_t outa = 0;
 
-	if (freq > 195000000)
-		return (0x20000000);
-	else
-		return (0x20008000);
+	/*
+	 * Set OUTA, per the data sheet.  See Table 40-15 titled
+	 * PLLA Characteristics in the SAM9260 doc.
+	 */
+
+	if (freq > 155000000)
+		outa = 2 << 14;
+	return ((1 << 29) | outa);
 }
 
 static uint32_t
 at91_pll_outb(int freq)
 {
 
-	return (0x4000);
+	return (1 << 14);
 }
 
 static void
@@ -173,7 +181,7 @@
 	 * to be near the optimal 2 MHz per datasheet.  We know
 	 * we are going to be using this for the USB clock at 96 MHz.
 	 * Causes no extra frequency deviation for all recomended crystal
-	 * values.
+	 * values.  See Note 1, table 40-16 SAM9260 doc.
 	 */
 	clk = at91_pmc_clock_ref("pllb");
 	clk->pll_min_in    = SAM9260_PLL_B_MIN_IN_FREQ;		/*   1 MHz */
Index: at91sam9g20.c
===================================================================
--- at91sam9g20.c	(revision 238879)
+++ at91sam9g20.c	(working copy)
@@ -122,21 +122,29 @@
 	{ 0, 0, 0, 0, 0 }
 };
 
+/*
+ * The following is unused currently since we don't ever set the PLLA
+ * frequency of the device.  If we did, we'd have to also pay attention
+ * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower
+ * than ~600MHz, which the PMC code doesn't do right now.
+ * XXX this likely should be in at91_pmc as at91_pmc_800mhz_plla_outa.
+ */
 static uint32_t
 at91_pll_outa(int freq)
 {
+	uint32_t outa;
 
-	switch (freq / 10000000) {
-		case 747 ... 801: return ((1 << 29) | (0 << 14));
-		case 697 ... 746: return ((1 << 29) | (1 << 14));
-		case 647 ... 696: return ((1 << 29) | (2 << 14));
-		case 597 ... 646: return ((1 << 29) | (3 << 14));
-		case 547 ... 596: return ((1 << 29) | (1 << 14));
-		case 497 ... 546: return ((1 << 29) | (2 << 14));
-		case 447 ... 496: return ((1 << 29) | (3 << 14));
-		case 397 ... 446: return ((1 << 29) | (4 << 14));
-		default: return (1 << 29);
-	}
+	/*
+	 * Set OUTA, per the data sheet.  See Table 41-17 titled
+	 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9G20 doc.
+	 * Note: the frequencies overlap by 5MHz, so we add 3 here to
+	 * center shoot the transition.
+	 */
+
+	freq /= 1000000;		/* MHz */
+	freq -= 3;			/* Allow for overlap. */
+	outa = 3 - ((freq / 50) & 3);	/* 750 / 50 = 7, see table */
+	return (1 << 29)| (outa << 14);
 }
 
 static uint32_t
Index: at91sam9g45.c
===================================================================
--- at91sam9g45.c	(revision 238879)
+++ at91sam9g45.c	(working copy)
@@ -125,21 +125,29 @@
 	{ 0, 0, 0, 0, 0 }
 };
 
+/*
+ * The following is unused currently since we don't ever set the PLLA
+ * frequency of the device.  If we did, we'd have to also pay attention
+ * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower
+ * than ~600MHz, which the PMC code doesn't do right now.
+ * XXX this likely should be in at91_pmc as at91_pmc_800mhz_plla_outa.
+ */
 static uint32_t
 at91_pll_outa(int freq)
 {
+	uint32_t outa;
 
-	switch (freq / 10000000) {
-		case 747 ... 801: return ((1 << 29) | (0 << 14));
-		case 697 ... 746: return ((1 << 29) | (1 << 14));
-		case 647 ... 696: return ((1 << 29) | (2 << 14));
-		case 597 ... 646: return ((1 << 29) | (3 << 14));
-		case 547 ... 596: return ((1 << 29) | (4 << 14));
-		case 497 ... 546: return ((1 << 29) | (5 << 14));
-		case 447 ... 496: return ((1 << 29) | (6 << 14));
-		case 397 ... 446: return ((1 << 29) | (7 << 14));
-		default: return (1 << 29);
-	}
+	/*
+	 * Set OUTA, per the data sheet.  See Table 46-15 titled
+	 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9G45 doc.
+	 * Note: the frequencies overlap by 5MHz, so we add 3 here to
+	 * center shoot the transition.
+	 */
+
+	freq /= 1000000;		/* MHz */
+	freq -= 3;			/* Allow for overlap. */
+	outa = 3 - ((freq / 50) & 3);	/* 750 / 50 = 7, see table */
+	return (1 << 29)| (outa << 14);
 }
 
 static void
Index: at91_pmc.c
===================================================================
--- at91_pmc.c	(revision 238879)
+++ at91_pmc.c	(working copy)
@@ -500,6 +500,7 @@
 		uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
 		udpck.pmc_mask = PMC_SCER_UDP_SAM9;
 	}
+
 	/* There is no pllb on AT91SAM9G45 */
 	if (at91_cpu_is(AT91_T_SAM9G45)) {
 		uhpck.parent = &upll;
@@ -509,6 +510,9 @@
 	mckr = RD4(sc, PMC_MCKR);
 	main_ck.hz = main_clock;
 
+	// Note: this means outa calc code for plla never used since
+	// we never change it.  If we did, we'd also have to mind
+	// ICPLLA to get the charge pump current right.
 	at91_pmc_pll_rate(&plla, RD4(sc, CKGR_PLLAR));
 
 	if (at91_cpu_is(AT91_T_SAM9G45) && (mckr & PMC_MCKR_PLLADIV2))
@@ -516,16 +520,17 @@
 
 	/*
 	 * Initialize the usb clock.  This sets up pllb, but disables the
-	 * actual clock.
+	 * actual clock. XXX except for the if 0 :(
 	 */
-	pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000;
-	at91_pmc_pll_rate(&pllb, pllb_init);
-
+	if (!at91_cpu_is(AT91_T_SAM9G45)) {
+		pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000;
+		at91_pmc_pll_rate(&pllb, pllb_init);
 #if 0
-	/* Turn off USB clocks */
-	at91_pmc_set_periph_mode(&ohci_clk, 0);
-	at91_pmc_set_periph_mode(&udc_clk, 0);
+		/* Turn off USB clocks */
+		at91_pmc_set_periph_mode(&ohci_clk, 0);
+		at91_pmc_set_periph_mode(&udc_clk, 0);
 #endif
+	}
 
 	if (at91_is_rm92()) {
 		WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);