Index: sys/arm/arm/pmap-v6.c
===================================================================
--- sys/arm/arm/pmap-v6.c	(revision 234076)
+++ sys/arm/arm/pmap-v6.c	(working copy)
@@ -810,6 +810,8 @@
 	pte = *ptep;
 
 	if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
+		cpu_dcache_wbinv_range(va, PAGE_SIZE);
+
 		/*
 		 * Page tables must have the cache-mode set to
 		 * Write-Thru.
@@ -1497,6 +1499,7 @@
 
 	if (l1pte_section_p(pde)) {
 		if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
+			cpu_dcache_wbinv_range(va, PAGE_SIZE);
 			*pdep = (pde & ~L1_S_CACHE_MASK) |
 			    pte_l1_s_cache_mode_pt;
 			PTE_SYNC(pdep);
@@ -1511,6 +1514,7 @@
 		ptep = &ptep[l2pte_index(va)];
 		pte = *ptep;
 		if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
+			cpu_dcache_wbinv_range(va, PAGE_SIZE);
 			*ptep = (pte & ~L2_S_CACHE_MASK) |
 			    pte_l2_s_cache_mode_pt;
 			PTE_SYNC(ptep);
@@ -2094,6 +2098,10 @@
 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
 {
 
+	/*
+	 * Actually we should flush caches only for pa
+	 */
+	cpu_dcache_wbinv_all();
 	pmap_kenter_internal(va, pa, 0);
 }
 
@@ -2756,6 +2764,9 @@
 		else if (PV_BEEN_REFD(oflags))
 			cpu_tlb_flushD_SE(va);
 	}
+
+	if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap))
+		cpu_icache_sync_range(va, PAGE_SIZE);
 }
 
 /*
@@ -3194,6 +3205,7 @@
 	PTE_SYNC(cdst_pte);
 	cpu_tlb_flushD_SE(cdstp);
 	cpu_cpwait();
+
 	if (off || size != PAGE_SIZE)
 		bzero((void *)(cdstp + off), size);
 	else
Index: sys/arm/include/pmap.h
===================================================================
--- sys/arm/include/pmap.h	(revision 234076)
+++ sys/arm/include/pmap.h	(working copy)
@@ -61,7 +61,7 @@
 #else
 #define PTE_NOCACHE	1
 #endif
-#define PTE_CACHE	4
+#define PTE_CACHE	6
 #define PTE_DEVICE	2
 #define PTE_PAGETABLE	4
 #else