Index: sys/boot/fdt/dts/bcm2835-rpi-b.dts =================================================================== --- sys/boot/fdt/dts/bcm2835-rpi-b.dts (revision 0) +++ sys/boot/fdt/dts/bcm2835-rpi-b.dts (working copy) @@ -0,0 +1,561 @@ +/dts-v1/; +/memreserve/ 0x08000000 0x08000000; /* Set by VideoCore */ + +/ { + model = "Raspberry Pi Model B (BCM2835)"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "raspberrypi,model-b", "broadcom,bcm2835-vc", "broadcom,bcm2708-vc"; + + system { + revision = <0>; /* Set by VideoCore */ + serial = <0 0>; /* Set by VideoCore */ + }; + + cpus { + cpu@0 { + compatible = "arm,1176jzf-s"; + }; + }; + + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x20000000 0x01000000>; + ranges = <0 0x20000000 0x01000000>; + + intc: interrupt-controller { + compatible = "broadcom,bcm2835-armctrl-ic", "broadcom,bcm2708-armctrl-ic"; + reg = <0xB200 0x200>; + + interrupt-controller; + #interrupt-cells = <1>; + + /* Bank 0 + * 0: ARM_TIMER + * 1: ARM_MAILBOX + * 2: ARM_DOORBELL_0 + * 3: ARM_DOORBELL_1 + * 4: VPU0_HALTED + * 5: VPU1_HALTED + * 6: ILLEGAL_TYPE0 + * 7: ILLEGAL_TYPE1 + */ + + /* Bank 1 + * 0: TIMER0 16: DMA0 + * 1: TIMER1 17: DMA1 + * 2: TIMER2 18: VC_DMA2 + * 3: TIMER3 19: VC_DMA3 + * 4: CODEC0 20: DMA4 + * 5: CODEC1 21: DMA5 + * 6: CODEC2 22: DMA6 + * 7: VC_JPEG 23: DMA7 + * 8: ISP 24: DMA8 + * 9: VC_USB 25: DMA9 + * 10: VC_3D 26: DMA10 + * 11: TRANSPOSER 27: DMA11 + * 12: MULTICORESYNC0 28: DMA12 + * 13: MULTICORESYNC1 29: AUX + * 14: MULTICORESYNC2 30: ARM + * 15: MULTICORESYNC3 31: VPUDMA + */ + + /* Bank 2 + * 0: HOSTPORT 16: SMI + * 1: VIDEOSCALER 17: GPIO0 + * 2: CCP2TX 18: GPIO1 + * 3: SDC 19: GPIO2 + * 4: DSI0 20: GPIO3 + * 5: AVE 21: VC_I2C + * 6: CAM0 22: VC_SPI + * 7: CAM1 23: VC_I2SPCM + * 8: HDMI0 24: VC_SDIO + * 9: HDMI1 25: VC_UART + * 10: PIXELVALVE1 26: SLIMBUS + * 11: I2CSPISLV 27: VEC + * 12: DSI1 28: CPG + * 13: PWA0 29: RNG + * 14: PWA1 30: VC_ARASANSDIO + * 15: CPR 31: AVSPMON + */ + }; + + timer { + compatible = "broadcom,bcm2835-system-timer", "broadcom,bcm2708-system-timer"; + reg = <0x3000 0x1000>; + interrupts = <8 9 10 11>; + interrupt-parent = <&intc>; + + clock-frequency = <1000000>; + }; + + dma: dma { + compatible = "broadcom,bcm2835-dma", "broadcom,bcm2708-dma"; + reg = <0x7000 0x1000>, <0xE05000 0x1000>; + interrupts = < + 26 /* 2 */ + 27 /* 3 */ + >; + interrupt-parent = <&intc>; + + broadcom,channels = <0>; /* Set by VideoCore */ + }; + + sdhci { + compatible = "broadcom,bcm2835-sdhci", "broadcom,bcm2708-sdhci"; + reg = <0x300000 0x100>; + interrupts = <70>; + interrupt-parent = <&intc>; + + clock-frequency = <50000000>; /* Set by VideoCore */ + }; + + armtimer { + /* Not AMBA compatible */ + compatible = "broadcom,bcm2835-sp804", "arm,sp804"; + reg = <0xB400 0x24>; + interrupts = <0>; + interrupt-parent = <&intc>; + }; + + vc_mbox: mbox { + compatible = "broadcom,bcm2835-mbox", "broadcom,bcm2708-mbox"; + reg = <0xB880 0x40>; + interrupts = <1>; + interrupt-parent = <&intc>; + + /* Channels + * 0: Power + * 1: Frame buffer + * 2: Virtual UART + * 3: VCHIQ + * 4: LEDs + * 5: Buttons + * 6: Touch screen + */ + }; + + watchdog0 { + compatible = "broadcom,bcm2835-wdt", "broadcom,bcm2708-wdt"; + reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */ + }; + + gpio: gpio { + compatible = "broadcom,bcm2835-gpio", "broadcom,bcm2708-gpio"; + reg = <0x200000 0xb0>; + + /* Unusual arrangement of interrupts (determined by testing) + * 17: Bank 0 (GPIOs 0-31) + * 19: Bank 1 (GPIOs 32-53) + * 18: Bank 2 + * 20: All banks (GPIOs 0-53) + */ + interrupts = <57 59 58 60>; + interrupt-parent = <&intc>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_reserved>; + + /* pins that can short 3.3V to GND in output mode: 46-47 + * pins used by VideoCore: 48-53 + */ + broadcom,read-only = <46>, <47>, <48>, <49>, <50>, <51>, <52>, <53>; + + /* BSC0 */ + pins_bsc0_a: bsc0_a { + broadcom,pins = <0>, <1>; + broadcom,function = "ALT0"; + }; + + pins_bsc0_b: bsc0_b { + broadcom,pins = <28>, <29>; + broadcom,function = "ALT0"; + }; + + pins_bsc0_c: bsc0_c { + broadcom,pins = <44>, <45>; + broadcom,function = "ALT1"; + }; + + /* BSC1 */ + pins_bsc1_a: bsc1_a { + broadcom,pins = <2>, <3>; + broadcom,function = "ALT0"; + }; + + pins_bsc1_b: bsc1_b { + broadcom,pins = <44>, <45>; + broadcom,function = "ALT2"; + }; + + /* GPCLK0 */ + pins_gpclk0_a: gpclk0_a { + broadcom,pins = <4>; + broadcom,function = "ALT0"; + }; + + pins_gpclk0_b: gpclk0_b { + broadcom,pins = <20>; + broadcom,function = "ALT5"; + }; + + pins_gpclk0_c: gpclk0_c { + broadcom,pins = <32>; + broadcom,function = "ALT0"; + }; + + pins_gpclk0_d: gpclk0_d { + broadcom,pins = <34>; + broadcom,function = "ALT0"; + }; + + /* GPCLK1 */ + pins_gpclk1_a: gpclk1_a { + broadcom,pins = <5>; + broadcom,function = "ALT0"; + }; + + pins_gpclk1_b: gpclk1_b { + broadcom,pins = <21>; + broadcom,function = "ALT5"; + }; + + pins_gpclk1_c: gpclk1_c { + broadcom,pins = <42>; + broadcom,function = "ALT0"; + }; + + pins_gpclk1_d: gpclk1_d { + broadcom,pins = <44>; + broadcom,function = "ALT0"; + }; + + /* GPCLK2 */ + pins_gpclk2_a: gpclk2_a { + broadcom,pins = <6>; + broadcom,function = "ALT0"; + }; + + pins_gpclk2_b: gpclk2_b { + broadcom,pins = <43>; + broadcom,function = "ALT0"; + }; + + /* SPI0 */ + pins_spi0_a: spi0_a { + broadcom,pins = <7>, <8>, <9>, <10>, <11>; + broadcom,function = "ALT0"; + }; + + pins_spi0_b: spi0_b { + broadcom,pins = <35>, <36>, <37>, <38>, <39>; + broadcom,function = "ALT0"; + }; + + /* PWM */ + pins_pwm0_a: pwm0_a { + broadcom,pins = <12>; + broadcom,function = "ALT0"; + }; + + pins_pwm0_b: pwm0_b { + broadcom,pins = <18>; + broadcom,function = "ALT5"; + }; + + pins_pwm0_c: pwm0_c { + broadcom,pins = <40>; + broadcom,function = "ALT0"; + }; + + pins_pwm1_a: pwm1_a { + broadcom,pins = <13>; + broadcom,function = "ALT0"; + }; + + pins_pwm1_b: pwm1_b { + broadcom,pins = <19>; + broadcom,function = "ALT5"; + }; + + pins_pwm1_c: pwm1_c { + broadcom,pins = <41>; + broadcom,function = "ALT0"; + }; + + pins_pwm1_d: pwm1_d { + broadcom,pins = <45>; + broadcom,function = "ALT0"; + }; + + /* UART0 */ + pins_uart0_a: uart0_a { + broadcom,pins = <14>, <15>; + broadcom,function = "ALT0"; + }; + + pins_uart0_b: uart0_b { + broadcom,pins = <32>, <33>; + broadcom,function = "ALT3"; + }; + + pins_uart0_c: uart0_c { + broadcom,pins = <36>, <37>; + broadcom,function = "ALT2"; + }; + + pins_uart0_fc_a: uart0_fc_a { + broadcom,pins = <16>, <17>; + broadcom,function = "ALT3"; + }; + + pins_uart0_fc_b: uart0_fc_b { + broadcom,pins = <30>, <31>; + broadcom,function = "ALT3"; + }; + + pins_uart0_fc_c: uart0_fc_c { + broadcom,pins = <39>, <38>; + broadcom,function = "ALT2"; + }; + + /* PCM */ + pins_pcm_a: pcm_a { + broadcom,pins = <18>, <19>, <20>, <21>; + broadcom,function = "ALT0"; + }; + + pins_pcm_b: pcm_b { + broadcom,pins = <28>, <29>, <30>, <31>; + broadcom,function = "ALT2"; + }; + + /* Secondary Address Bus */ + pins_sm_addr_a: sm_addr_a { + broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>; + broadcom,function = "ALT1"; + }; + + pins_sm_addr_b: sm_addr_b { + broadcom,pins = <33>, <32>, <31>, <30>, <29>, <28>; + broadcom,function = "ALT1"; + }; + + pins_sm_ctl_a: sm_ctl_a { + broadcom,pins = <6>, <7>; + broadcom,function = "ALT1"; + }; + + pins_sm_ctl_b: sm_ctl_b { + broadcom,pins = <34>, <35>; + broadcom,function = "ALT1"; + }; + + pins_sm_data_8bit_a: sm_data_8bit_a { + broadcom,pins = <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>; + broadcom,function = "ALT1"; + }; + + pins_sm_data_8bit_b: sm_data_8bit_b { + broadcom,pins = <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>; + broadcom,function = "ALT1"; + }; + + pins_sm_data_16bit: sm_data_16bit { + broadcom,pins = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>; + broadcom,function = "ALT1"; + }; + + pins_sm_data_18bit: sm_data_18bit { + broadcom,pins = <24>, <25>; + broadcom,function = "ALT1"; + }; + + /* BSCSL */ + pins_bscsl: bscsl { + broadcom,pins = <18>, <19>; + broadcom,function = "ALT3"; + }; + + /* SPISL */ + pins_spisl: spisl { + broadcom,pins = <18>, <19>, <20>, <21>; + broadcom,function = "ALT3"; + }; + + /* SPI1 */ + pins_spi1: spi1 { + broadcom,pins = <16>, <17>, <18>, <19>, <20>, <21>; + broadcom,function = "ALT4"; + }; + + /* UART1 */ + pins_uart1_a: uart1_a { + broadcom,pins = <14>, <15>; + broadcom,function = "ALT5"; + }; + + pins_uart1_b: uart1_b { + broadcom,pins = <32>, <33>; + broadcom,function = "ALT5"; + }; + + pins_uart1_c: uart1_c { + broadcom,pins = <40>, <41>; + broadcom,function = "ALT5"; + }; + + pins_uart1_fc_a: uart1_fc_a { + broadcom,pins = <16>, <17>; + broadcom,function = "ALT5"; + }; + + pins_uart1_fc_b: uart1_fc_b { + broadcom,pins = <30>, <31>; + broadcom,function = "ALT5"; + }; + + pins_uart1_fc_c: uart1_fc_c { + broadcom,pins = <43>, <42>; + broadcom,function = "ALT5"; + }; + + /* SPI2 */ + pins_spi2: spi2 { + broadcom,pins = <40>, <41>, <42>, <43>, <44>, <45>; + broadcom,function = "ALT4"; + }; + + /* ARM JTAG */ + pins_arm_jtag_trst: arm_jtag_trst { + broadcom,pins = <22>; + broadcom,function = "ALT4"; + }; + + pins_arm_jtag_a: arm_jtag_a { + broadcom,pins = <4>, <5>, <6>, <12>, <13>; + broadcom,function = "ALT5"; + }; + + pins_arm_jtag_b: arm_jtag_b { + broadcom,pins = <23>, <24>, <25>, <26>, <27>; + broadcom,function = "ALT4"; + }; + + /* Reserved */ + pins_reserved: reserved { + broadcom,pins = <48>, <49>, <50>, <51>, <52>, <53>; + broadcom,function = "ALT3"; + }; + }; + + uart0: uart0 { + compatible = "broadcom,bcm2835-uart", "broadcom,bcm2708-uart", "arm,pl011", "arm,primecell"; + reg = <0x201000 0x1000>; + interrupts = <65>; + interrupt-parent = <&intc>; + + clock-frequency = <3000000>; /* Set by VideoCore */ + reg-shift = <2>; + }; + + usb { + compatible = "broadcom,bcm2835-usb", "broadcom,bcm2708-usb", "synopsys,designware-hs-otg2"; + reg = <0x980000 0x20000>; + interrupts = <17>; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <0>; + }; + + display { + compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; + + broadcom,vc-mailbox = <&vc_mbox>; + broadcom,vc-channel = <1>; + + broadcom,width = <0>; /* Set by VideoCore */ + broadcom,height = <0>; /* Set by VideoCore */ + broadcom,depth = <0>; /* Set by VideoCore */ + }; + }; + + + memory { + device_type = "memory"; + reg = <0 0x08000000>; /* 128MB */ + }; + + leds { + compatible = "gpio-leds"; + + ok { + label = "ok"; + gpios = <&gpio 16 1>; + + /* Don't change this - it configures + * how the led driver determines if + * the led is on or off when it loads. + */ + default-state = "keep"; + + /* This is the real default state. */ + linux,default-trigger = "default-on"; + }; + }; + + power: regulator { + compatible = "broadcom,bcm2835-power-mgr", "broadcom,bcm2708-power-mgr", "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + broadcom,vc-mailbox = <&vc_mbox>; + broadcom,vc-channel = <0>; + + regulator-name = "VideoCore"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on = <1>; + + sd_card_power: regulator@0 { + compatible = "broadcom,bcm2835-power-dev", "broadcom,bcm2708-power-dev"; + reg = <0>; + + vin-supply = <&power>; + regulator-name = "SD Card"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* This is for the controller itself, not the root port */ + usb_hcd_power: regulator@3 { + compatible = "broadcom,bcm2835-power-dev", "broadcom,bcm2708-power-dev"; + reg = <3>; + + vin-supply = <&power>; + regulator-name = "USB HCD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + aliases { + uart0 = &uart0; + }; + + chosen { + bootargs = ""; /* Set by VideoCore */ + stdin = "uart0"; + stdout = "uart0"; + }; + +}; Index: sys/arm/arm/disassem.c =================================================================== --- sys/arm/arm/disassem.c (revision 239664) +++ sys/arm/arm/disassem.c (working copy) @@ -130,6 +130,15 @@ { 0x0c500000, 0x04100000, "ldr", "daW" }, { 0x0c500000, 0x04400000, "strb", "daW" }, { 0x0c500000, 0x04500000, "ldrb", "daW" }, + { 0xffffffff, 0xf57ff01f, "clrex", "c" }, + { 0x0ff00ff0, 0x01800f90, "strex", "dmo" }, + { 0x0ff00fff, 0x01900f9f, "ldrex", "do" }, + { 0x0ff00ff0, 0x01a00f90, "strexd", "dmo" }, + { 0x0ff00fff, 0x01b00f9f, "ldrexd", "do" }, + { 0x0ff00ff0, 0x01c00f90, "strexb", "dmo" }, + { 0x0ff00fff, 0x01d00f9f, "ldrexb", "do" }, + { 0x0ff00ff0, 0x01e00f90, "strexh", "dmo" }, + { 0x0ff00fff, 0x01f00f9f, "ldrexh", "do" }, { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ { 0x0e100000, 0x08000000, "stm", "XnWl" }, Index: sys/arm/arm/sc_machdep.c =================================================================== --- sys/arm/arm/sc_machdep.c (revision 0) +++ sys/arm/arm/sc_machdep.c (working copy) @@ -0,0 +1,90 @@ +/*- + * Copyright (c) 2003 Jake Burkholder. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static sc_softc_t sc_softcs[8]; + +int +sc_get_cons_priority(int *unit, int *flags) +{ + + *unit = 0; + *flags = 0; + return (CN_INTERNAL); +} + +int +sc_max_unit(void) +{ + return (1); +} + +sc_softc_t * +sc_get_softc(int unit, int flags) +{ + sc_softc_t *sc; + + if (unit < 0) + return (NULL); + sc = &sc_softcs[unit]; + sc->unit = unit; + if ((sc->flags & SC_INIT_DONE) == 0) { + sc->keyboard = -1; + sc->adapter = -1; + sc->cursor_char = SC_CURSOR_CHAR; + sc->mouse_char = SC_MOUSE_CHAR; + } + return (sc); +} + +void +sc_get_bios_values(bios_values_t *values) +{ + values->cursor_start = 0; + values->cursor_end = 32; + values->shift_state = 0; +} + +int +sc_tone(int hz) +{ + return (0); +} Property changes on: sys/arm/arm/sc_machdep.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/arm/machdep.c =================================================================== --- sys/arm/arm/machdep.c (revision 239664) +++ sys/arm/arm/machdep.c (working copy) @@ -791,7 +791,7 @@ void pcpu0_init(void) { -#if ARM_ARCH_7A || defined(CPU_MV_PJ4B) +#if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B) set_pcpu(pcpup); #endif pcpu_init(pcpup, 0, sizeof(struct pcpu)); Index: sys/arm/arm/cpufunc.c =================================================================== --- sys/arm/arm/cpufunc.c (revision 239664) +++ sys/arm/arm/cpufunc.c (working copy) @@ -968,6 +968,68 @@ }; #endif /* CPU_FA526 || CPU_FA626TE */ +#if defined(CPU_ARM11) +struct cpu_functions arm11_cpufuncs = { + /* CPU functions */ + + cpufunc_id, /* id */ + arm11_drain_writebuf, /* cpwait */ + + /* MMU functions */ + + cpufunc_control, /* control */ + cpufunc_domains, /* Domain */ + arm11_setttb, /* Setttb */ + cpufunc_faultstatus, /* Faultstatus */ + cpufunc_faultaddress, /* Faultaddress */ + + /* TLB functions */ + + arm11_tlb_flushID, /* tlb_flushID */ + arm11_tlb_flushID_SE, /* tlb_flushID_SE */ + arm11_tlb_flushI, /* tlb_flushI */ + arm11_tlb_flushI_SE, /* tlb_flushI_SE */ + arm11_tlb_flushD, /* tlb_flushD */ + arm11_tlb_flushD_SE, /* tlb_flushD_SE */ + + /* Cache operations */ + + armv6_icache_sync_all, /* icache_sync_all */ + armv6_icache_sync_range, /* icache_sync_range */ + + armv6_dcache_wbinv_all, /* dcache_wbinv_all */ + armv6_dcache_wbinv_range, /* dcache_wbinv_range */ + armv6_dcache_inv_range, /* dcache_inv_range */ + armv6_dcache_wb_range, /* dcache_wb_range */ + + armv6_idcache_wbinv_all, /* idcache_wbinv_all */ + armv6_idcache_wbinv_range, /* idcache_wbinv_range */ + + (void*)cpufunc_nullop, /* l2cache_wbinv_all */ + (void *)cpufunc_nullop, /* l2cache_wbinv_range */ + (void *)cpufunc_nullop, /* l2cache_inv_range */ + (void *)cpufunc_nullop, /* l2cache_wb_range */ + + /* Other functions */ + + cpufunc_nullop, /* flush_prefetchbuf */ + arm11_drain_writebuf, /* drain_writebuf */ + cpufunc_nullop, /* flush_brnchtgt_C */ + (void *)cpufunc_nullop, /* flush_brnchtgt_E */ + + arm11_sleep, /* sleep */ + + /* Soft functions */ + + cpufunc_null_fixup, /* dataabt_fixup */ + cpufunc_null_fixup, /* prefetchabt_fixup */ + + arm11_context_switch, /* context_switch */ + + arm11_setup /* cpu setup */ +}; +#endif /* CPU_ARM11 */ + #if defined(CPU_CORTEXA) struct cpu_functions cortexa_cpufuncs = { /* CPU functions */ @@ -1324,6 +1386,18 @@ goto out; } #endif /* CPU_ARM10 */ +#ifdef CPU_ARM11 + if (1) { + cpufuncs = arm11_cpufuncs; + cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ + get_cachetype_cp15(); + + pmap_pte_init_mmu_v6(); + /* Use powersave on this CPU. */ + + goto out; + } +#endif /* CPU_ARM11 */ #ifdef CPU_CORTEXA if (cputype == CPU_ID_CORTEXA8R1 || cputype == CPU_ID_CORTEXA8R2 || @@ -2197,38 +2271,36 @@ arm11_setup(args) char *args; { - int cpuctrl, cpuctrlmask; + int cpuctrl; - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - /* | CPU_CONTROL_BPRD_ENABLE */; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; - + cpuctrl = CPU_CONTROL_MMU_ENABLE; #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS cpuctrl |= CPU_CONTROL_AFLT_ENABLE; #endif - + cpuctrl |= CPU_CONTROL_DC_ENABLE; + cpuctrl |= (0xf << 3); cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl); - #ifdef __ARMEB__ cpuctrl |= CPU_CONTROL_BEND_ENABLE; #endif + cpuctrl |= CPU_CONTROL_SYST_ENABLE; + cpuctrl |= CPU_CONTROL_BPRD_ENABLE; + cpuctrl |= CPU_CONTROL_IC_ENABLE; + if (vector_page == ARM_VECTORS_HIGH) + cpuctrl |= CPU_CONTROL_VECRELOC; + cpuctrl |= (0x5 << 16); + cpuctrl |= CPU_CONTROL_V6_EXTPAGE; - /* Clear out the cache */ + /* Make sure caches are clean. */ cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); - /* Now really make sure they are clean. */ - __asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); - /* Set the control register */ + ctrl = cpuctrl; cpu_control(0xffffffff, cpuctrl); - /* And again. */ cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); } #endif /* CPU_ARM11 */ Index: sys/arm/arm/cpufunc_asm_arm11.S =================================================================== --- sys/arm/arm/cpufunc_asm_arm11.S (revision 239664) +++ sys/arm/arm/cpufunc_asm_arm11.S (working copy) @@ -44,9 +44,11 @@ * addresses that are about to change. */ ENTRY(arm11_setttb) +#ifdef PMAP_CACHE_VIVT stmfd sp!, {r0, lr} bl _C_LABEL(armv5_idcache_wbinv_all) ldmfd sp!, {r0, lr} +#endif mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ Index: sys/arm/arm/elf_trampoline.c =================================================================== --- sys/arm/arm/elf_trampoline.c (revision 239664) +++ sys/arm/arm/elf_trampoline.c (working copy) @@ -63,6 +63,8 @@ #define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all #elif defined(CPU_ARM10) #define cpu_idcache_wbinv_all arm10_idcache_wbinv_all +#elif defined(CPU_ARM11) +#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all #elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \ defined(CPU_IXP12X0) #define cpu_idcache_wbinv_all sa1_cache_purgeID Index: sys/arm/arm/cpufunc_asm_armv6.S =================================================================== --- sys/arm/arm/cpufunc_asm_armv6.S (revision 0) +++ sys/arm/arm/cpufunc_asm_armv6.S (working copy) @@ -0,0 +1,136 @@ +/* $NetBSD: cpufunc_asm_armv6.S,v 1.4 2010/12/10 02:06:22 bsh Exp $ */ + +/* + * Copyright (c) 2002, 2005 ARM Limited + * Portions Copyright (c) 2007 Microsoft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * ARMv6 assembly functions for manipulating caches. + * These routines can be used by any core that supports the mcrr address + * range operations. + */ + +#include + + .arch armv6 + +/* + * Functions to set the MMU Translation Table Base register + * + * We need to clean and flush the cache as it uses virtual + * addresses that are about to change. + */ +ENTRY(armv6_setttb) +#ifdef PMAP_CACHE_VIVT + mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ + mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */ +#endif + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + + mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ + + mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ + RET + +/* + * Cache operations. + */ + +/* LINTSTUB: void armv6_icache_sync_range(vaddr_t, vsize_t); */ +ENTRY_NP(armv6_icache_sync_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */ + mcrr p15, 0, r1, r0, c12 /* clean D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_icache_sync_all(void); */ +ENTRY_NP(armv6_icache_sync_all) + /* + * We assume that the code here can never be out of sync with the + * dcache, so that we can safely flush the Icache and fall through + * into the Dcache cleaning code. + */ + mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ + mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_dcache_wb_range(vaddr_t, vsize_t); */ +ENTRY(armv6_dcache_wb_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c12 /* clean D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */ +ENTRY(armv6_dcache_wbinv_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* + * Note, we must not invalidate everything. If the range is too big we + * must use wb-inv of the entire cache. + * + * LINTSTUB: void armv6_dcache_inv_range(vaddr_t, vsize_t); + */ +ENTRY(armv6_dcache_inv_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_idcache_wbinv_range(vaddr_t, vsize_t); */ +ENTRY(armv6_idcache_wbinv_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c5 /* invaliate I cache range */ + mcrr p15, 0, r1, r0, c14 /* clean & invaliate D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_idcache_wbinv_all(void); */ +ENTRY_NP(armv6_idcache_wbinv_all) + /* + * We assume that the code here can never be out of sync with the + * dcache, so that we can safely flush the Icache and fall through + * into the Dcache purging code. + */ + mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ + /* Fall through to purge Dcache. */ + +/* LINTSTUB: void armv6_dcache_wbinv_all(void); */ +ENTRY(armv6_dcache_wbinv_all) + mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET Property changes on: sys/arm/arm/cpufunc_asm_armv6.S ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/include/sc_machdep.h =================================================================== --- sys/arm/include/sc_machdep.h (revision 0) +++ sys/arm/include/sc_machdep.h (working copy) @@ -0,0 +1,71 @@ +/*- + * Copyright (c) 2003 Jake Burkholder. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_SC_MACHDEP_H_ +#define _MACHINE_SC_MACHDEP_H_ + +/* Color attributes for foreground text */ + +#define FG_BLACK 0x0 +#define FG_BLUE 0x1 +#define FG_GREEN 0x2 +#define FG_CYAN 0x3 +#define FG_RED 0x4 +#define FG_MAGENTA 0x5 +#define FG_BROWN 0x6 +#define FG_LIGHTGREY 0x7 /* aka white */ +#define FG_DARKGREY 0x8 +#define FG_LIGHTBLUE 0x9 +#define FG_LIGHTGREEN 0xa +#define FG_LIGHTCYAN 0xb +#define FG_LIGHTRED 0xc +#define FG_LIGHTMAGENTA 0xd +#define FG_YELLOW 0xe +#define FG_WHITE 0xf /* aka bright white */ +#define FG_BLINK 0x80 + +/* Color attributes for text background */ + +#define BG_BLACK 0x00 +#define BG_BLUE 0x10 +#define BG_GREEN 0x20 +#define BG_CYAN 0x30 +#define BG_RED 0x40 +#define BG_MAGENTA 0x50 +#define BG_BROWN 0x60 +#define BG_LIGHTGREY 0x70 +#define BG_DARKGREY 0x80 +#define BG_LIGHTBLUE 0x90 +#define BG_LIGHTGREEN 0xa0 +#define BG_LIGHTCYAN 0xb0 +#define BG_LIGHTRED 0xc0 +#define BG_LIGHTMAGENTA 0xd0 +#define BG_YELLOW 0xe0 +#define BG_WHITE 0xf0 + +#endif /* !_MACHINE_SC_MACHDEP_H_ */ Property changes on: sys/arm/include/sc_machdep.h ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/include/cpufunc.h =================================================================== --- sys/arm/include/cpufunc.h (revision 239664) +++ sys/arm/include/cpufunc.h (working copy) @@ -494,10 +494,17 @@ void pj4b_flush_brnchtgt_va (u_int); void pj4b_sleep (int); -void armv6_icache_sync_all (void); -void armv6_dcache_wbinv_all (void); -void armv6_idcache_wbinv_all (void); +void armv6_icache_sync_all (void); +void armv6_icache_sync_range (vm_offset_t, vm_size_t); +void armv6_dcache_wbinv_all (void); +void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); +void armv6_dcache_inv_range (vm_offset_t, vm_size_t); +void armv6_dcache_wb_range (vm_offset_t, vm_size_t); + +void armv6_idcache_wbinv_all (void); +void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); + void armv7_setttb (u_int); void armv7_tlb_flushID (void); void armv7_tlb_flushID_SE (u_int); Index: sys/arm/include/intr.h =================================================================== --- sys/arm/include/intr.h (revision 239664) +++ sys/arm/include/intr.h (working copy) @@ -52,6 +52,8 @@ #define NIRQ 64 #elif defined(CPU_CORTEXA) #define NIRQ 128 +#elif defined(CPU_ARM11) +#define NIRQ 128 #else #define NIRQ 32 #endif Index: sys/arm/broadcom/bcm2835/files.bcm2835 =================================================================== --- sys/arm/broadcom/bcm2835/files.bcm2835 (revision 0) +++ sys/arm/broadcom/bcm2835/files.bcm2835 (working copy) @@ -0,0 +1,22 @@ +arm/broadcom/bcm2835/bcm2835_machdep.c standard +arm/broadcom/bcm2835/dma.c standard +arm/broadcom/bcm2835/sdhci_brcm.c optional sdhci +arm/broadcom/bcm2835/wdog_brcm.c standard +arm/broadcom/bcm2835/bus_space.c optional fdt +arm/broadcom/bcm2835/common.c optional fdt +# arm/broadcom/bcm2835/dotg_brcm.c optional dotg +# dev/usb/controller/dotg.c optional dotg +arm/broadcom/bcm2835/interrupt.c standard +arm/broadcom/bcm2835/systimer.c standard +arm/broadcom/bcm2835/mbox.c standard +# arm/broadcom/bcm2835/dma.c standard +arm/broadcom/bcm2835/framebuffer.c optional sc + +kern/kern_clocksource.c standard + +arm/arm/bus_space_generic.c standard +arm/arm/bus_space_asm_generic.S standard +arm/arm/cpufunc_asm_arm11.S standard +arm/arm/cpufunc_asm_armv5.S standard +arm/arm/cpufunc_asm_armv6.S standard +arm/arm/irq_dispatch.S standard Index: sys/arm/broadcom/bcm2835/wdog_brcm.c =================================================================== --- sys/arm/broadcom/bcm2835/wdog_brcm.c (revision 0) +++ sys/arm/broadcom/bcm2835/wdog_brcm.c (working copy) @@ -0,0 +1,167 @@ +/*- + * Copyright (c) 2012 Alexander Rybalko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define BCM2835_PASWORD 0x5a + +#define BCM2835_WDOG_RESET 0 +#define BCM2835_PASSWORD_MASK 0xff000000 +#define BCM2835_PASSWORD_SHIFT 24 +#define BCM2835_WDOG_TIME_MASK 0x000fffff +#define BCM2835_WDOG_TIME_SHIFT 0 + +#define READ(_sc, _r) bus_space_read_4((_sc)->bst, (_sc)->bsh, (_r)) +#define WRITE(_sc, _r, _v) bus_space_write_4((_sc)->bst, (_sc)->bsh, (_r), (_v)) + +#define BCM2835_RSTC_WRCFG_CLR 0xffffffcf +#define BCM2835_RSTC_WRCFG_SET 0x00000030 +#define BCM2835_RSTC_WRCFG_FULL_RESET 0x00000020 +#define BCM2835_RSTC_RESET 0x00000102 + +#define BCM2835_RSTC_REG 0x00 +#define BCM2835_RSTS_REG 0x04 +#define BCM2835_WDOG_REG 0x08 + +static struct bcmwd_softc *bcmwd_lsc = NULL; + +struct bcmwd_softc { + device_t dev; + struct resource * res; + bus_space_tag_t bst; + bus_space_handle_t bsh; + int wdog_armed; + int wdog_period; + char wdog_passwd; +}; + +#ifdef notyet +static void bcmwd_watchdog_fn(void *private, u_int cmd, int *error); +#endif + +static int +bcmwd_probe(device_t dev) +{ + + if (ofw_bus_is_compatible(dev, "broadcom,bcm2835-wdt")) { + device_set_desc(dev, "BCM2708/2835 Watchdog"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +bcmwd_attach(device_t dev) +{ + struct bcmwd_softc *sc; + int rid; + + if (bcmwd_lsc != NULL) + return (ENXIO); + + sc = device_get_softc(dev); + sc->wdog_period = 7; + sc->wdog_passwd = BCM2835_PASWORD; + sc->wdog_armed = 0; + sc->dev = dev; + + rid = 0; + sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (sc->res == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return (ENXIO); + } + + sc->bst = rman_get_bustag(sc->res); + sc->bsh = rman_get_bushandle(sc->res); + + bcmwd_lsc = sc; +#ifdef notyet + EVENTHANDLER_REGISTER(watchdog_list, bcmwd_watchdog_fn, sc, 0); +#endif + return (0); +} + +#ifdef notyet +static void +bcmwd_watchdog_fn(void *private, u_int cmd, int *error) +{ + /* XXX: not yet */ +} +#endif + +void +bcmwd_watchdog_reset() +{ + + if (bcmwd_lsc == NULL) + return; + + WRITE(bcmwd_lsc, BCM2835_WDOG_REG, + (BCM2835_PASWORD << BCM2835_PASSWORD_SHIFT) | 10); + + WRITE(bcmwd_lsc, BCM2835_RSTC_REG, + (READ(bcmwd_lsc, BCM2835_RSTC_REG) & BCM2835_RSTC_WRCFG_CLR) | + (BCM2835_PASWORD << BCM2835_PASSWORD_SHIFT) | + BCM2835_RSTC_WRCFG_FULL_RESET); +} + +static device_method_t bcmwd_methods[] = { + DEVMETHOD(device_probe, bcmwd_probe), + DEVMETHOD(device_attach, bcmwd_attach), + + DEVMETHOD_END +}; + +static driver_t bcmwd_driver = { + "bcmwd", + bcmwd_methods, + sizeof(struct bcmwd_softc), +}; +static devclass_t bcmwd_devclass; + +DRIVER_MODULE(bcmwd, simplebus, bcmwd_driver, bcmwd_devclass, 0, 0); Property changes on: sys/arm/broadcom/bcm2835/wdog_brcm.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/mbox.c =================================================================== --- sys/arm/broadcom/bcm2835/mbox.c (revision 0) +++ sys/arm/broadcom/bcm2835/mbox.c (working copy) @@ -0,0 +1,251 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#define REG_READ 0x00 +#define REG_POL 0x10 +#define REG_SENDER 0x14 +#define REG_STATUS 0x18 +#define STATUS_FULL 0x80000000 +#define STATUS_EMPTY 0x40000000 +#define REG_CONFIG 0x1C +#define CONFIG_DATA_IRQ 0x00000001 +#define REG_WRITE 0x20 /* This is Mailbox 1 address */ + +#define MBOX_MSG(chan, data) (((data) & ~0xf) | ((chan) & 0xf)) +#define MBOX_CHAN(msg) ((msg) & 0xf) +#define MBOX_DATA(msg) ((msg) & ~0xf) + +#define MBOX_LOCK do { \ + mtx_lock(&brcm_mbox_sc->lock); \ +} while(0) + +#define MBOX_UNLOCK do { \ + mtx_unlock(&brcm_mbox_sc->lock); \ +} while(0) + +#define DEBUG +#ifdef DEBUG +#define dprintf(fmt, args...) printf(fmt, ##args) +#else +#define dprintf(fmt, args...) +#endif + +struct brcm_mbox_softc { + struct mtx lock; + struct resource * mem_res; + struct resource * irq_res; + void* intr_hl; + bus_space_tag_t bst; + bus_space_handle_t bsh; + int valid[BCM2835_MBOX_CHANS]; + int msg[BCM2835_MBOX_CHANS]; +}; + +static struct brcm_mbox_softc *brcm_mbox_sc = NULL; + +#define mbox_read_4(reg) \ + bus_space_read_4(brcm_mbox_sc->bst, brcm_mbox_sc->bsh, reg) +#define mbox_write_4(reg, val) \ + bus_space_write_4(brcm_mbox_sc->bst, brcm_mbox_sc->bsh, reg, val) + +static void +brcm_mbox_intr(void *arg) +{ + struct brcm_mbox_softc *sc = arg; + int chan; + uint32_t data; + uint32_t msg; + + MBOX_LOCK; + while (!(mbox_read_4(REG_STATUS) & STATUS_EMPTY)) { + msg = mbox_read_4(REG_READ); + dprintf("brcm_mbox_intr: raw data %08x\n", msg); + chan = MBOX_CHAN(msg); + data = MBOX_DATA(msg); + if (sc->valid[chan]) { + printf("brcm_mbox_intr: channel %d oveflow\n", chan); + continue; + } + dprintf("brcm_mbox_intr: chan %d, data %08x\n", chan, data); + sc->msg[chan] = data; + sc->valid[chan] = 1; + wakeup(&sc->msg[chan]); + + } + MBOX_UNLOCK; +} + +static int +brcm_mbox_probe(device_t dev) +{ + + if (ofw_bus_is_compatible(dev, "broadcom,bcm2835-mbox")) { + device_set_desc(dev, "BCM2835 VideoCore Mailbox"); + return(BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +brcm_mbox_attach(device_t dev) +{ + struct brcm_mbox_softc *sc = device_get_softc(dev); + int i; + int rid = 0; + + if (brcm_mbox_sc != NULL) + return (EINVAL); + + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return (ENXIO); + } + + sc->bst = rman_get_bustag(sc->mem_res); + sc->bsh = rman_get_bushandle(sc->mem_res); + + rid = 0; + sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); + if (sc->irq_res == NULL) { + device_printf(dev, "could not allocate interrupt resource\n"); + return (ENXIO); + } + + /* Setup and enable the timer */ + if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, + NULL, brcm_mbox_intr, sc, + &sc->intr_hl) != 0) { + bus_release_resource(dev, SYS_RES_IRQ, rid, + sc->irq_res); + device_printf(dev, "Unable to setup the clock irq handler.\n"); + return (ENXIO); + } + + mtx_init(&sc->lock, "vcio mbox", MTX_DEF, 0); + for (i = 0; i < BCM2835_MBOX_CHANS; i++) { + sc->valid[0] = 0; + sc->msg[0] = 0; + } + + brcm_mbox_sc = sc; + /* Read all pending messages */ + brcm_mbox_intr(sc); + + /* Should be called after brcm_mbox_sc initialization */ + mbox_write_4(REG_CONFIG, CONFIG_DATA_IRQ); + + return (0); +} + +static device_method_t brcm_mbox_methods[] = { + DEVMETHOD(device_probe, brcm_mbox_probe), + DEVMETHOD(device_attach, brcm_mbox_attach), + { 0, 0 } +}; + +static driver_t brcm_mbox_driver = { + "mbox", + brcm_mbox_methods, + sizeof(struct brcm_mbox_softc), +}; + +static devclass_t brcm_mbox_devclass; + +DRIVER_MODULE(mbox, simplebus, brcm_mbox_driver, brcm_mbox_devclass, 0, 0); + +/* + * Mailbox API + */ + +int +brcm_mbox_write(int chan, uint32_t data) +{ + int limit = 20000; + + dprintf("brcm_mbox_write: chan %d, data %08x\n", chan, data); + MBOX_LOCK; + + while ((mbox_read_4(REG_STATUS) & STATUS_FULL) && limit--) { + DELAY(2); + } + + if (limit == 0) { + printf("brcm_mbox_write: STATUS_FULL stuck"); + MBOX_UNLOCK; + return (EAGAIN); + } + + mbox_write_4(REG_WRITE, MBOX_MSG(chan, data)); + + MBOX_UNLOCK; + return (0); +} + +int +brcm_mbox_read(int chan, uint32_t *data) +{ + struct brcm_mbox_softc *sc = brcm_mbox_sc; + + dprintf("brcm_mbox_read: chan %d\n", chan); + MBOX_LOCK; + while (!sc->valid[chan]) + msleep(&sc->msg[chan], &sc->lock, PZERO, "vcio mbox read", 0); + *data = brcm_mbox_sc->msg[chan]; + brcm_mbox_sc->valid[chan] = 0; + MBOX_UNLOCK; + dprintf("brcm_mbox_read: chan %d, data %08x\n", chan, *data); + + return (0); +} Property changes on: sys/arm/broadcom/bcm2835/mbox.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/wdog_brcm.h =================================================================== --- sys/arm/broadcom/bcm2835/wdog_brcm.h (revision 0) +++ sys/arm/broadcom/bcm2835/wdog_brcm.h (working copy) @@ -0,0 +1,30 @@ +/*- + * Copyright (c) 2012 Alexander Rybalko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _WDOG_BRCM_H_ +#define _WDOG_BRCM_H_ + +void bcmwd_watchdog_reset(void); +#endif Property changes on: sys/arm/broadcom/bcm2835/wdog_brcm.h ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/mbox.h =================================================================== --- sys/arm/broadcom/bcm2835/mbox.h (revision 0) +++ sys/arm/broadcom/bcm2835/mbox.h (working copy) @@ -0,0 +1,42 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _BCM2835_MBOX_H_ +#define _BCM2835_MBOX_H_ + +#define BCM2835_MBOX_CHAN_POWER 0 +#define BCM2835_MBOX_CHAN_FB 1 +#define BCM2835_MBOX_CHAN_VUART 2 +#define BCM2835_MBOX_CHAN_VCHIQ 3 +#define BCM2835_MBOX_CHAN_LEDS 4 +#define BCM2835_MBOX_CHAN_BUTTONS 5 +#define BCM2835_MBOX_CHAN_TS 6 +#define BCM2835_MBOX_CHANS 7 + +int brcm_mbox_write(int chan, uint32_t data); +int brcm_mbox_read(int chan, uint32_t *data); + +#endif /* _BCM2835_MBOX_H_ */ Property changes on: sys/arm/broadcom/bcm2835/mbox.h ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/systimer.c =================================================================== --- sys/arm/broadcom/bcm2835/systimer.c (revision 0) +++ sys/arm/broadcom/bcm2835/systimer.c (working copy) @@ -0,0 +1,300 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * Copyright (c) 2012 Damjan Marion + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#define BCM2835_NUM_TIMERS 4 + +#define DEFAULT_TIMER 3 +#define DEFAULT_FREQUENCY 1000000 + +#define SYSTIMER_CS 0x00 +#define SYSTIMER_CLO 0x04 +#define SYSTIMER_CHI 0x08 +#define SYSTIMER_C0 0x0C +#define SYSTIMER_C1 0x10 +#define SYSTIMER_C2 0x14 +#define SYSTIMER_C3 0x18 + +struct systimer { + int index; + bool enabled; + struct eventtimer et; +}; + +struct brcm_systimer_softc { + struct resource* mem_res; + struct resource* irq_res[BCM2835_NUM_TIMERS]; + void* intr_hl[BCM2835_NUM_TIMERS]; + uint32_t sysclk_freq; + bus_space_tag_t bst; + bus_space_handle_t bsh; + struct systimer st[BCM2835_NUM_TIMERS]; +}; + +static struct resource_spec brcm_systimer_irq_spec[] = { + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 1, RF_ACTIVE }, + { SYS_RES_IRQ, 2, RF_ACTIVE }, + { SYS_RES_IRQ, 3, RF_ACTIVE }, + { -1, 0, 0 } +}; + +static struct brcm_systimer_softc *brcm_systimer_sc = NULL; + +/* Read/Write macros for Timer used as timecounter */ +#define brcm_systimer_tc_read_4(reg) \ + bus_space_read_4(brcm_systimer_sc->bst, \ + brcm_systimer_sc->bsh, reg) + +#define brcm_systimer_tc_write_4(reg, val) \ + bus_space_write_4(brcm_systimer_sc->bst, \ + brcm_systimer_sc->bsh, reg, val) + +static unsigned brcm_systimer_tc_get_timecount(struct timecounter *); + +static struct timecounter brcm_systimer_tc = { + .tc_name = "BCM2835 Timecouter", + .tc_get_timecount = brcm_systimer_tc_get_timecount, + .tc_poll_pps = NULL, + .tc_counter_mask = ~0u, + .tc_frequency = 0, + .tc_quality = 1000, +}; + +static unsigned +brcm_systimer_tc_get_timecount(struct timecounter *tc) +{ + return brcm_systimer_tc_read_4(SYSTIMER_CLO); +} + +static int +brcm_systimer_start(struct eventtimer *et, struct bintime *first, + struct bintime *period) +{ + struct systimer *st = et->et_priv; + uint32_t clo; + uint32_t count; + + if (first != NULL) { + st->enabled = 1; + + count = (st->et.et_frequency * (first->frac >> 32)) >> 32; + if (first->sec != 0) + count += st->et.et_frequency * first->sec; + + clo = brcm_systimer_tc_read_4(SYSTIMER_CLO); + clo += count; + brcm_systimer_tc_write_4(SYSTIMER_C0 + st->index*4, clo); + + return (0); + } + + return (EINVAL); +} + +static int +brcm_systimer_stop(struct eventtimer *et) +{ + struct systimer *st = et->et_priv; + st->enabled = 0; + + return (0); +} + +static int +brcm_systimer_intr(void *arg) +{ + struct systimer *st = (struct systimer *)arg; + + brcm_systimer_tc_write_4(SYSTIMER_CS, (1 << st->index)); + if (st->enabled) { + if (st->et.et_active) { + st->et.et_event_cb(&st->et, st->et.et_arg); + } + } + + return (FILTER_HANDLED); +} + +static int +brcm_systimer_probe(device_t dev) +{ + + if (ofw_bus_is_compatible(dev, "broadcom,bcm2835-system-timer")) { + device_set_desc(dev, "BCM2835 System Timer"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +brcm_systimer_attach(device_t dev) +{ + struct brcm_systimer_softc *sc = device_get_softc(dev); + int err; + int rid = 0; + + if (brcm_systimer_sc != NULL) + return (EINVAL); + + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return (ENXIO); + } + + sc->bst = rman_get_bustag(sc->mem_res); + sc->bsh = rman_get_bushandle(sc->mem_res); + + /* Request the IRQ resources */ + err = bus_alloc_resources(dev, brcm_systimer_irq_spec, + sc->irq_res); + if (err) { + device_printf(dev, "Error: could not allocate irq resources\n"); + return (ENXIO); + } + + /* TODO: get frequency from FDT */ + sc->sysclk_freq = DEFAULT_FREQUENCY; + + /* Setup and enable the timer */ + if (bus_setup_intr(dev, sc->irq_res[DEFAULT_TIMER], INTR_TYPE_CLK, + brcm_systimer_intr, NULL, &sc->st[DEFAULT_TIMER], + &sc->intr_hl[DEFAULT_TIMER]) != 0) { + bus_release_resources(dev, brcm_systimer_irq_spec, + sc->irq_res); + device_printf(dev, "Unable to setup the clock irq handler.\n"); + return (ENXIO); + } + + sc->st[DEFAULT_TIMER].index = DEFAULT_TIMER; + sc->st[DEFAULT_TIMER].enabled = 0; + sc->st[DEFAULT_TIMER].et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO); + sprintf(sc->st[DEFAULT_TIMER].et.et_name, "BCM2835 Event Timer %d", DEFAULT_TIMER); + sc->st[DEFAULT_TIMER].et.et_flags = ET_FLAGS_ONESHOT; + sc->st[DEFAULT_TIMER].et.et_quality = 1000; + sc->st[DEFAULT_TIMER].et.et_frequency = sc->sysclk_freq; + sc->st[DEFAULT_TIMER].et.et_min_period.sec = 0; + sc->st[DEFAULT_TIMER].et.et_min_period.frac = + ((0x00000002LLU << 32) / sc->st[DEFAULT_TIMER].et.et_frequency) << 32; + sc->st[DEFAULT_TIMER].et.et_max_period.sec = 0xfffffff0U / sc->st[DEFAULT_TIMER].et.et_frequency; + sc->st[DEFAULT_TIMER].et.et_max_period.frac = + ((0xfffffffeLLU << 32) / sc->st[DEFAULT_TIMER].et.et_frequency) << 32; + sc->st[DEFAULT_TIMER].et.et_start = brcm_systimer_start; + sc->st[DEFAULT_TIMER].et.et_stop = brcm_systimer_stop; + sc->st[DEFAULT_TIMER].et.et_priv = &sc->st[DEFAULT_TIMER]; + et_register(&sc->st[DEFAULT_TIMER].et); + + brcm_systimer_sc = sc; + + brcm_systimer_tc.tc_frequency = DEFAULT_FREQUENCY; + tc_init(&brcm_systimer_tc); + + return (0); +} + +static device_method_t brcm_systimer_methods[] = { + DEVMETHOD(device_probe, brcm_systimer_probe), + DEVMETHOD(device_attach, brcm_systimer_attach), + { 0, 0 } +}; + +static driver_t brcm_systimer_driver = { + "systimer", + brcm_systimer_methods, + sizeof(struct brcm_systimer_softc), +}; + +static devclass_t brcm_systimer_devclass; + +DRIVER_MODULE(brcm_systimer, simplebus, brcm_systimer_driver, brcm_systimer_devclass, 0, 0); + +void +cpu_initclocks(void) +{ + cpu_initclocks_bsp(); +} + +int foo_bar = 0; +void +DELAY(int usec) +{ + int32_t counts; + uint32_t first, last; + + if (brcm_systimer_sc == NULL) { + for (; usec > 0; usec--) + for (counts = 200; counts > 0; counts--) + /* Prevent gcc from optimizing out the loop */ + cpufunc_nullop(); + return; + } + + /* Get the number of times to count */ + counts = usec * ((brcm_systimer_tc.tc_frequency / 1000000) + 1);; + + first = brcm_systimer_tc_read_4(SYSTIMER_CLO); + + while (counts > 0) { + last = brcm_systimer_tc_read_4(SYSTIMER_CLO); + if (last == first) + continue; + if (last>first) { + counts -= (int32_t)(last - first); + } else { + counts -= (int32_t)((0xFFFFFFFF - first) + last); + } + first = last; + } +} + Property changes on: sys/arm/broadcom/bcm2835/systimer.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/framebuffer.c =================================================================== --- sys/arm/broadcom/bcm2835/framebuffer.c (revision 0) +++ sys/arm/broadcom/bcm2835/framebuffer.c (working copy) @@ -0,0 +1,744 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#define BCMFB_FONT_HEIGHT 16 + +#define FB_WIDTH 640 +#define FB_HEIGHT 480 + +struct bcm_fb_config { + uint32_t xres; + uint32_t yres; + uint32_t vxres; + uint32_t vyres; + uint32_t pitch; + uint32_t bpp; + uint32_t xoffset; + uint32_t yoffset; + /* Filled by videocore */ + uint32_t base; + uint32_t screen_size; +}; + +struct bcmsc_softc { + device_t dev; + struct cdev * cdev; + struct mtx mtx; + bus_dma_tag_t dma_tag; + bus_dmamap_t dma_map; + struct bcm_fb_config* fb_config; + bus_addr_t fb_config_phys; + struct intr_config_hook init_hook; + +}; + +struct video_adapter_softc { + /* Videoadpater part */ + video_adapter_t va; + int console; + + intptr_t fb_addr; + unsigned int fb_size; + + unsigned int height; + unsigned int width; + unsigned int stride; + + unsigned int xmargin; + unsigned int ymargin; + + unsigned char *font; + int initialized; +}; + +static struct bcmsc_softc *bcmsc_softc; +static struct video_adapter_softc va_softc; + +#define bcm_fb_lock(_sc) mtx_lock(&(_sc)->mtx) +#define bcm_fb_unlock(_sc) mtx_unlock(&(_sc)->mtx) +#define bcm_fb_lock_assert(sc) mtx_assert(&(_sc)->mtx, MA_OWNED) + +static int bcm_fb_probe(device_t); +static int bcm_fb_attach(device_t); +static void bcm_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err); + +static void +bcm_fb_init(void *arg) +{ + struct bcmsc_softc *sc = arg; + struct video_adapter_softc *va_sc = &va_softc; + int err; + volatile struct bcm_fb_config* fb_config = sc->fb_config; + + /* TODO: replace it with FDT stuff */ + fb_config->xres = FB_WIDTH; + fb_config->yres = FB_HEIGHT; + fb_config->vxres = 0; + fb_config->vyres = 0; + fb_config->xoffset = 0; + fb_config->yoffset = 0; + fb_config->bpp = 24; + fb_config->base = 0; + fb_config->pitch = 0; + fb_config->screen_size = 0; + + bus_dmamap_sync(sc->dma_tag, sc->dma_map, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + brcm_mbox_write(BCM2835_MBOX_CHAN_FB, sc->fb_config_phys); + brcm_mbox_read(BCM2835_MBOX_CHAN_FB, &err); + bus_dmamap_sync(sc->dma_tag, sc->dma_map, + BUS_DMASYNC_POSTREAD); + + if (err == 0) { + device_printf(sc->dev, "%dx%d(%dx%d@%d,%d) %dbpp\n", + fb_config->xres, fb_config->yres, + fb_config->vxres, fb_config->vyres, + fb_config->xoffset, fb_config->yoffset, + fb_config->bpp); + + + device_printf(sc->dev, "pitch %d, base 0x%08x, screen_size %d\n", + fb_config->pitch, fb_config->base, + fb_config->screen_size); + + if (fb_config->base) { + va_sc->fb_addr = (intptr_t)pmap_mapdev(fb_config->base, fb_config->screen_size); + va_sc->fb_size = fb_config->screen_size; + va_sc->stride = fb_config->pitch; + } + } + else + device_printf(sc->dev, "Failed to set framebuffer info\n"); + + config_intrhook_disestablish(&sc->init_hook); +} + +static int +bcm_fb_probe(device_t dev) +{ + int error; + + if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-fb")) + return (ENXIO); + + device_set_desc(dev, "BCM2835 framebuffer device"); + + error = sc_probe_unit(device_get_unit(dev), + device_get_flags(dev) | SC_AUTODETECT_KBD); + + if (error != 0) + return (error); + + return (BUS_PROBE_DEFAULT); +} + +static int +bcm_fb_attach(device_t dev) +{ + struct bcmsc_softc *sc = device_get_softc(dev); + int dma_size = sizeof(struct bcm_fb_config); + int err; + + if (bcmsc_softc) + return (ENXIO); + + bcmsc_softc = sc; + + sc->dev = dev; + mtx_init(&sc->mtx, "bcm2835fb", "fb", MTX_DEF); + + err = bus_dma_tag_create( + bus_get_dma_tag(sc->dev), + PAGE_SIZE, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + dma_size, 1, /* maxsize, nsegments */ + dma_size, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->dma_tag); + + err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->fb_config, + 0, &sc->dma_map); + if (err) { + device_printf(dev, "cannot allocate framebuffer\n"); + goto fail; + } + + err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->fb_config, + dma_size, bcm_fb_dmamap_cb, &sc->fb_config_phys, BUS_DMA_NOWAIT); + + if (err) { + device_printf(dev, "cannot load DMA map\n"); + goto fail; + } + + err = (sc_attach_unit(device_get_unit(dev), + device_get_flags(dev) | SC_AUTODETECT_KBD)); + + if (err) { + device_printf(dev, "failed to attach syscons\n"); + goto fail; + } + + /* + * We have to wait until interrupts are enabled. + * Mailbox relies on it to get data from VideoCore + */ + sc->init_hook.ich_func = bcm_fb_init; + sc->init_hook.ich_arg = sc; + + if (config_intrhook_establish(&sc->init_hook) != 0) { + device_printf(dev, "failed to establish intrhook\n"); + return (ENOMEM); + } + + return (0); + +fail: + return (ENXIO); +} + + +static void +bcm_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) +{ + bus_addr_t *addr; + + if (err) + return; + + addr = (bus_addr_t*)arg; + *addr = PHYS_TO_VCBUS(segs[0].ds_addr); +} + +static device_method_t bcm_fb_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bcm_fb_probe), + DEVMETHOD(device_attach, bcm_fb_attach), + + { 0, 0 } +}; + +static devclass_t bcm_fb_devclass; + +static driver_t bcm_fb_driver = { + "fb", + bcm_fb_methods, + sizeof(struct bcmsc_softc), +}; + +DRIVER_MODULE(bcm2835fb, simplebus, bcm_fb_driver, bcm_fb_devclass, 0, 0); + +/* + * Video driver routines and glue. + */ +static int bcmfb_configure(int); +static vi_probe_t bcmfb_probe; +static vi_init_t bcmfb_init; +static vi_get_info_t bcmfb_get_info; +static vi_query_mode_t bcmfb_query_mode; +static vi_set_mode_t bcmfb_set_mode; +static vi_save_font_t bcmfb_save_font; +static vi_load_font_t bcmfb_load_font; +static vi_show_font_t bcmfb_show_font; +static vi_save_palette_t bcmfb_save_palette; +static vi_load_palette_t bcmfb_load_palette; +static vi_set_border_t bcmfb_set_border; +static vi_save_state_t bcmfb_save_state; +static vi_load_state_t bcmfb_load_state; +static vi_set_win_org_t bcmfb_set_win_org; +static vi_read_hw_cursor_t bcmfb_read_hw_cursor; +static vi_set_hw_cursor_t bcmfb_set_hw_cursor; +static vi_set_hw_cursor_shape_t bcmfb_set_hw_cursor_shape; +static vi_blank_display_t bcmfb_blank_display; +static vi_mmap_t bcmfb_mmap; +static vi_ioctl_t bcmfb_ioctl; +static vi_clear_t bcmfb_clear; +static vi_fill_rect_t bcmfb_fill_rect; +static vi_bitblt_t bcmfb_bitblt; +static vi_diag_t bcmfb_diag; +static vi_save_cursor_palette_t bcmfb_save_cursor_palette; +static vi_load_cursor_palette_t bcmfb_load_cursor_palette; +static vi_copy_t bcmfb_copy; +static vi_putp_t bcmfb_putp; +static vi_putc_t bcmfb_putc; +static vi_puts_t bcmfb_puts; +static vi_putm_t bcmfb_putm; + +static video_switch_t bcmfbvidsw = { + .probe = bcmfb_probe, + .init = bcmfb_init, + .get_info = bcmfb_get_info, + .query_mode = bcmfb_query_mode, + .set_mode = bcmfb_set_mode, + .save_font = bcmfb_save_font, + .load_font = bcmfb_load_font, + .show_font = bcmfb_show_font, + .save_palette = bcmfb_save_palette, + .load_palette = bcmfb_load_palette, + .set_border = bcmfb_set_border, + .save_state = bcmfb_save_state, + .load_state = bcmfb_load_state, + .set_win_org = bcmfb_set_win_org, + .read_hw_cursor = bcmfb_read_hw_cursor, + .set_hw_cursor = bcmfb_set_hw_cursor, + .set_hw_cursor_shape = bcmfb_set_hw_cursor_shape, + .blank_display = bcmfb_blank_display, + .mmap = bcmfb_mmap, + .ioctl = bcmfb_ioctl, + .clear = bcmfb_clear, + .fill_rect = bcmfb_fill_rect, + .bitblt = bcmfb_bitblt, + .diag = bcmfb_diag, + .save_cursor_palette = bcmfb_save_cursor_palette, + .load_cursor_palette = bcmfb_load_cursor_palette, + .copy = bcmfb_copy, + .putp = bcmfb_putp, + .putc = bcmfb_putc, + .puts = bcmfb_puts, + .putm = bcmfb_putm, +}; + +VIDEO_DRIVER(bcmfb, bcmfbvidsw, bcmfb_configure); + +extern sc_rndr_sw_t txtrndrsw; +RENDERER(bcmfb, 0, txtrndrsw, gfb_set); +RENDERER_MODULE(bcmfb, gfb_set); + +static uint16_t bcmfb_static_window[ROW*COL]; +extern u_char dflt_font_16[]; + +static int +bcmfb_configure(int flags) +{ + struct video_adapter_softc *sc; + + sc = &va_softc; + + if (sc->initialized) + return 0; + + sc->height = FB_HEIGHT; + sc->width = FB_WIDTH; + + bcmfb_init(0, &sc->va, 0); + + sc->initialized = 1; + + return (0); +} + + + +static int +bcmfb_probe(int unit, video_adapter_t **adp, void *arg, int flags) +{ + + return (0); +} + +static int +bcmfb_init(int unit, video_adapter_t *adp, int flags) +{ + struct video_adapter_softc *sc; + video_info_t *vi; + + sc = (struct video_adapter_softc *)adp; + vi = &adp->va_info; + + vid_init_struct(adp, "bcmfb", -1, unit); + + sc->font = dflt_font_16; + vi->vi_cheight = BCMFB_FONT_HEIGHT; + vi->vi_cwidth = 8; + vi->vi_width = sc->width/8; + vi->vi_height = sc->height/vi->vi_cheight; + + /* + * Clamp width/height to syscons maximums + */ + if (vi->vi_width > COL) + vi->vi_width = COL; + if (vi->vi_height > ROW) + vi->vi_height = ROW; + + sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2; + sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight))/2; + + adp->va_window = (vm_offset_t) bcmfb_static_window; + adp->va_flags |= V_ADP_FONT /* | V_ADP_COLOR | V_ADP_MODECHANGE */; + + vid_register(&sc->va); + + return (0); +} + +static int +bcmfb_get_info(video_adapter_t *adp, int mode, video_info_t *info) +{ + bcopy(&adp->va_info, info, sizeof(*info)); + return (0); +} + +static int +bcmfb_query_mode(video_adapter_t *adp, video_info_t *info) +{ + return (0); +} + +static int +bcmfb_set_mode(video_adapter_t *adp, int mode) +{ + return (0); +} + +static int +bcmfb_save_font(video_adapter_t *adp, int page, int size, int width, + u_char *data, int c, int count) +{ + return (0); +} + +static int +bcmfb_load_font(video_adapter_t *adp, int page, int size, int width, + u_char *data, int c, int count) +{ + struct video_adapter_softc *sc = (struct video_adapter_softc *)adp; + + sc->font = data; + + return (0); +} + +static int +bcmfb_show_font(video_adapter_t *adp, int page) +{ + return (0); +} + +static int +bcmfb_save_palette(video_adapter_t *adp, u_char *palette) +{ + return (0); +} + +static int +bcmfb_load_palette(video_adapter_t *adp, u_char *palette) +{ + return (0); +} + +static int +bcmfb_set_border(video_adapter_t *adp, int border) +{ + return (bcmfb_blank_display(adp, border)); +} + +static int +bcmfb_save_state(video_adapter_t *adp, void *p, size_t size) +{ + return (0); +} + +static int +bcmfb_load_state(video_adapter_t *adp, void *p) +{ + return (0); +} + +static int +bcmfb_set_win_org(video_adapter_t *adp, off_t offset) +{ + return (0); +} + +static int +bcmfb_read_hw_cursor(video_adapter_t *adp, int *col, int *row) +{ + *col = *row = 0; + + return (0); +} + +static int +bcmfb_set_hw_cursor(video_adapter_t *adp, int col, int row) +{ + return (0); +} + +static int +bcmfb_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, + int celsize, int blink) +{ + return (0); +} + +static int +bcmfb_blank_display(video_adapter_t *adp, int mode) +{ +#if 0 + struct bcmsc_softc *sc = (struct bcmsc_softc *)adp; + uint32_t *p; + + for (p = (uint32_t *)sc->fb_addr; + p < (uint32_t *)(sc->fb_addr + sc->fb_size); + p++) + *p = bcmfb_cmap[bcmfb_background(SC_NORM_ATTR)]; +#endif + + return (0); +} + +static int +bcmfb_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr, + int prot, vm_memattr_t *memattr) +{ + struct video_adapter_softc *sc; + + sc = (struct video_adapter_softc *)adp; + + /* + * This might be a legacy VGA mem request: if so, just point it at the + * framebuffer, since it shouldn't be touched + */ + if (offset < sc->stride*sc->height) { + *paddr = sc->fb_addr + offset; + return (0); + } + + return (EINVAL); +} + +static int +bcmfb_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data) +{ + return (0); +} + +static int +bcmfb_clear(video_adapter_t *adp) +{ + return (bcmfb_blank_display(adp, 0)); +} + +static int +bcmfb_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) +{ + return (0); +} + +static int +bcmfb_bitblt(video_adapter_t *adp, ...) +{ + return (0); +} + +static int +bcmfb_diag(video_adapter_t *adp, int level) +{ + return (0); +} + +static int +bcmfb_save_cursor_palette(video_adapter_t *adp, u_char *palette) +{ + return (0); +} + +static int +bcmfb_load_cursor_palette(video_adapter_t *adp, u_char *palette) +{ + return (0); +} + +static int +bcmfb_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n) +{ + return (0); +} + +static int +bcmfb_putp(video_adapter_t *adp, vm_offset_t off, uint32_t p, uint32_t a, + int size, int bpp, int bit_ltor, int byte_ltor) +{ + return (0); +} + +static int +bcmfb_putc(video_adapter_t *adp, vm_offset_t off, uint8_t c, uint8_t a) +{ + struct video_adapter_softc *sc; + int row; + int col; + int i, j, k; + uint8_t *addr; + u_char *p; + uint8_t fg, bg, color; + + sc = (struct video_adapter_softc *)adp; + + if (sc->fb_addr == 0) + return (0); + + row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; + col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; + p = sc->font + c*BCMFB_FONT_HEIGHT; + addr = (uint8_t *)sc->fb_addr + + (row + sc->ymargin)*(sc->stride) + + 3 * (col + sc->xmargin); + + // bg = bcmfb_cmap[bcmfb_background(a)]; + // fg = bcmfb_cmap[bcmfb_foreground(a)]; + + bg = 0x00; + fg = 0x80; + + for (i = 0; i < BCMFB_FONT_HEIGHT; i++) { + for (j = 0, k = 7; j < 8; j++, k--) { + if ((p[i] & (1 << k)) == 0) + color = bg; + else + color = fg; + + addr[3*j] = color; + addr[3*j+1] = color; + addr[3*j+2] = color; + } + + addr += (sc->stride); + } + + return (0); +} + +static int +bcmfb_puts(video_adapter_t *adp, vm_offset_t off, u_int16_t *s, int len) +{ + int i; + + for (i = 0; i < len; i++) + bcmfb_putc(adp, off + i, s[i] & 0xff, (s[i] & 0xff00) >> 8); + + return (0); +} + +/* + * XXX TODO: revisit this, as the pixel size is 16 bits not 32 bits! + */ +static int +bcmfb_putm(video_adapter_t *adp, int x, int y, uint8_t *pixel_image, + uint32_t pixel_mask, int size, int width) +{ +#if 0 + struct bcmsc_softc *sc = (struct bcmsc_softc *)adp; + int i, j, k; + uint32_t fg, bg; + uint32_t *addr; + + *(volatile uint32_t *)(0x0d0000c0) |= 0x20; + addr = (uint32_t *)sc->fb_addr + + (y + sc->ymargin)*(sc->stride/4) + + x + sc->xmargin; + + fg = bcmfb_cmap[bcmfb_foreground(SC_NORM_ATTR)]; + bg = bcmfb_cmap[bcmfb_background(SC_NORM_ATTR)]; + + for (i = 0; i < size && i+y < sc->height - 2*sc->ymargin; i++) { + for (j = 0, k = width; j < 8; j++, k--) { + if (x + j >= sc->width - 2*sc->xmargin) + continue; + + if (pixel_image[i] & (1 << k)) + *(addr + j) = (*(addr + j) == fg) ? bg : fg; + } + addr += (sc->stride/4); + } +#endif + return (0); + +} + +/* + * Define a stub keyboard driver in case one hasn't been + * compiled into the kernel + */ +#include +#include + +static int dummy_kbd_configure(int flags); + +keyboard_switch_t bcmdummysw; + +static int +dummy_kbd_configure(int flags) +{ + + return (0); +} +KEYBOARD_DRIVER(bcmdummy, bcmdummysw, dummy_kbd_configure); Property changes on: sys/arm/broadcom/bcm2835/framebuffer.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/interrupt.c =================================================================== --- sys/arm/broadcom/bcm2835/interrupt.c (revision 0) +++ sys/arm/broadcom/bcm2835/interrupt.c (working copy) @@ -0,0 +1,209 @@ +/*- + * Copyright (c) 2012 Damjan Marion + * All rights reserved. + * + * Based on OMAP3 INTC code by Ben Gray + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define INTC_PENDING_BASIC 0x00 +#define INTC_PENDING_BANK1 0x04 +#define INTC_PENDING_BANK2 0x08 +#define INTC_FIQ_CONTROL 0x0C +#define INTC_ENABLE_BANK1 0x10 +#define INTC_ENABLE_BANK2 0x14 +#define INTC_ENABLE_BASIC 0x18 +#define INTC_DISABLE_BANK1 0x1C +#define INTC_DISABLE_BANK2 0x20 +#define INTC_DISABLE_BASIC 0x24 + +#define BANK1_START 8 +#define BANK1_END (BANK1_START + 32 - 1) +#define BANK2_START (BANK1_START + 32) +#define BANK2_END (BANK2_START + 32 - 1) + +#define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START)) +#define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END)) +#define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END)) +#define IRQ_BANK1(n) ((n) - BANK1_START) +#define IRQ_BANK2(n) ((n) - BANK2_START) + +#ifdef DEBUG +#define dprintf(fmt, args...) printf(fmt, ##args) +#else +#define dprintf(fmt, args...) +#endif + +struct brcm_intc_softc { + device_t sc_dev; + struct resource * intc_res; + bus_space_tag_t intc_bst; + bus_space_handle_t intc_bsh; +}; + +static struct brcm_intc_softc *brcm_intc_sc = NULL; + +#define intc_read_4(reg) \ + bus_space_read_4(brcm_intc_sc->intc_bst, brcm_intc_sc->intc_bsh, reg) +#define intc_write_4(reg, val) \ + bus_space_write_4(brcm_intc_sc->intc_bst, brcm_intc_sc->intc_bsh, reg, val) + +static int +brcm_intc_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic")) + return (ENXIO); + device_set_desc(dev, "BCM2835 Interrupt Controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +brcm_intc_attach(device_t dev) +{ + struct brcm_intc_softc *sc = device_get_softc(dev); + int rid = 0; + + sc->sc_dev = dev; + + if (brcm_intc_sc) + return (ENXIO); + + sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (sc->intc_res == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return (ENXIO); + } + + sc->intc_bst = rman_get_bustag(sc->intc_res); + sc->intc_bsh = rman_get_bushandle(sc->intc_res); + + brcm_intc_sc = sc; + + return (0); +} + +static device_method_t brcm_intc_methods[] = { + DEVMETHOD(device_probe, brcm_intc_probe), + DEVMETHOD(device_attach, brcm_intc_attach), + { 0, 0 } +}; + +static driver_t brcm_intc_driver = { + "intc", + brcm_intc_methods, + sizeof(struct brcm_intc_softc), +}; + +static devclass_t brcm_intc_devclass; + +DRIVER_MODULE(intc, simplebus, brcm_intc_driver, brcm_intc_devclass, 0, 0); + +int +arm_get_next_irq(int last_irq) +{ + uint32_t pending; + int32_t irq = last_irq + 1; + + /* Sanity check */ + if (irq < 0) + irq = 0; + + /* TODO: should we mask last_irq? */ + pending = intc_read_4(INTC_PENDING_BASIC); + while (irq < BANK1_START) { + if (pending & (1 << irq)) { + dprintf("%s: %d -> %d\n", __func__, last_irq, irq); + return irq; + } + irq++; + } + + pending = intc_read_4(INTC_PENDING_BANK1); + while (irq < BANK2_START) { + if (pending & (1 << IRQ_BANK1(irq))) { + dprintf("%s: %d -> %d\n", __func__, last_irq, irq); + return irq; + } + irq++; + } + + pending = intc_read_4(INTC_PENDING_BANK2); + while (irq <= BANK2_END) { + if (pending & (1 << IRQ_BANK2(irq))) { + dprintf("%s: %d -> %d\n", __func__, last_irq, irq); + return irq; + } + irq++; + } + + return (-1); +} + +void +arm_mask_irq(uintptr_t nb) +{ + dprintf("%s: %d\n", __func__, nb); + + if (IS_IRQ_BASIC(nb)) + intc_write_4(INTC_DISABLE_BASIC, (1 << nb)); + else if (IS_IRQ_BANK1(nb)) + intc_write_4(INTC_DISABLE_BANK1, (1 << IRQ_BANK1(nb))); + else if (IS_IRQ_BANK2(nb)) + intc_write_4(INTC_DISABLE_BANK2, (1 << IRQ_BANK2(nb))); + else + printf("arm_mask_irq: Invalid IRQ number: %d\n", nb); +} + +void +arm_unmask_irq(uintptr_t nb) +{ + dprintf("%s: %d\n", __func__, nb); + + if (IS_IRQ_BASIC(nb)) + intc_write_4(INTC_ENABLE_BASIC, (1 << nb)); + else if (IS_IRQ_BANK1(nb)) + intc_write_4(INTC_ENABLE_BANK1, (1 << IRQ_BANK1(nb))); + else if (IS_IRQ_BANK2(nb)) + intc_write_4(INTC_ENABLE_BANK2, (1 << IRQ_BANK2(nb))); + else + printf("arm_mask_irq: Invalid IRQ number: %d\n", nb); +} Property changes on: sys/arm/broadcom/bcm2835/interrupt.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/dma.c =================================================================== --- sys/arm/broadcom/bcm2835/dma.c (revision 0) +++ sys/arm/broadcom/bcm2835/dma.c (working copy) @@ -0,0 +1,237 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#define DMA_LOCK do { \ + mtx_lock(&brcm_dma_sc->lock); \ +} while(0) + +#define DMA_UNLOCK do { \ + mtx_unlock(&brcm_dma_sc->lock); \ +} while(0) + +#define DEBUG +#ifdef DEBUG +#define dprintf(fmt, args...) printf(fmt, ##args) +#else +#define dprintf(fmt, args...) +#endif + +#define DMA_REG_CS(chan) (0x100*(chan) + 0x00) +#define REG_CS_RESET (1 << 31) +#define REG_CS_ABORT (1 << 30) +#define REG_CS_DISDEBUG (1 << 29) +#define REG_CS_WAIT_WRITES (1 << 28) +#define REG_CS_PANIC_PRI_SHIFT 20 +#define REG_CS_PANIC_PRI_MASK 0xf +#define REG_CS_PRI_SHIFT 16 +#define REG_CS_PRI_MASK 0xf +#define REG_CS_ERROR (1 << 8) +#define REG_CS_WAITING_WRITES (1 << 6) +#define REG_CS_DREQ_STOPS_DMA (1 << 5) +#define REG_CS_PAUSED (1 << 4) +#define REG_CS_DREQ (1 << 3) +#define REG_CS_INT (1 << 2) +#define REG_CS_END (1 << 1) +#define REG_CS_ACTIVE (1 << 0) +#define DMA_REG_CB_ADDR(chan) (0x100*(chan) + 0x04) +#define DMA_REG_TI(chan) (0x100*(chan) + 0x08) +#define REG_TI_NO_WIDE_BURSTS (1 << 26) +#define REG_TI_WAITS_SHIFT 21 +#define REG_TI_WAITS_MASK 0x1f +#define REG_TI_PERMAP_SHIFT 16 +#define REG_TI_PERMAP_MASK 0x1f +#define REG_TI_BURST_LEN_SHIFT 12 +#define REG_TI_BURST_LEN_MASK 7 +#define REG_TI_SRC_IGNORE (1 << 11) +#define REG_TI_SRC_DREQ (1 << 10) +#define REG_TI_SRC_WIDTH (1 << 9) +#define REG_TI_SRC_INC (1 << 8) +#define REG_TI_DST_IGNORE (1 << 7) +#define REG_TI_DST_DREQ (1 << 6) +#define REG_TI_DST_WIDTH (1 << 5) +#define REG_TI_DST_INC (1 << 4) +#define REG_TI_WAIT_RESP (1 << 3) +#define REG_TI_TD_MODE (1 << 1) +#define REG_TI_INTEN (1 << 0) +#define DMA_REG_SRC_ADDR(chan) (0x100*(chan) + 0x10) +#define DMA_REG_DST_ADDR(chan) (0x100*(chan) + 0x14) +#define DMA_REG_STRIDE(chan) (0x100*(chan) + 0x18) +#define DMA_REG_NEXT_CB(chan) (0x100*(chan) + 0x1C) +#define DMA_REG_DEBUG(chan) (0x100*(chan) + 0x20) +#define DMA_REG_INT_STATUS 0xfe0 +#define DMA_REG_ENABLE 0xff0 + +#define DMA_MAX_CHANNEL 14 +#define DMA_IRQS 12 + +struct dma_cb +{ + uint32_t cb_ti; /* transfer information */ + uint32_t cb_src_pa; /* source address */ + uint32_t cb_dst_pa; /* destination address */ + uint32_t cb_length; /* transfer length */ + uint32_t cb_stride; /* sride for 2D mode */ + uint32_t cb_next; /* next CB address */ + uint32_t cb_reserved[2]; /* set to zero */ +}; + +struct brcm_dma_softc { + struct mtx lock; + struct resource * mem_res; + struct resource * irq_res[DMA_IRQS]; + void* intr_hl[DMA_IRQS]; + bus_space_tag_t bst; + bus_space_handle_t bsh; +}; + +static struct brcm_dma_softc *brcm_dma_sc = NULL; + +#define dma_read_4(reg) \ + bus_space_read_4(brcm_dma_sc->bst, brcm_dma_sc->bsh, reg) +#define dma_write_4(reg, val) \ + bus_space_write_4(brcm_dma_sc->bst, brcm_dma_sc->bsh, reg, val) + +/* + * We're interested only in channels 2 and 3 + */ +static struct resource_spec bcm_dma_irq_spec[] = { + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 1, RF_ACTIVE }, + { -1, 0, 0 } +}; + +static void +brcm_dma_intr(void *arg) +{ + + DMA_LOCK; + // TODO: implement + DMA_UNLOCK; +} + +static int +brcm_dma_probe(device_t dev) +{ + + if (ofw_bus_is_compatible(dev, "broadcom,bcm2835-dma")) { + device_set_desc(dev, "BCM2835 DMA Controller"); + return(BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +brcm_dma_attach(device_t dev) +{ + struct brcm_dma_softc *sc = device_get_softc(dev); + int i; + int rid = 0; + int err; + + if (brcm_dma_sc != NULL) + return (EINVAL); + + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return (ENXIO); + } + + sc->bst = rman_get_bustag(sc->mem_res); + sc->bsh = rman_get_bushandle(sc->mem_res); + + rid = 0; + err = bus_alloc_resources(dev, bcm_dma_irq_spec, sc->irq_res); + if (err) { + device_printf(dev, "could not allocate interrupt resource\n"); + return (ENXIO); + } + + /* Setup and enable the timer */ + for (i = 0; bcm_dma_irq_spec[i].type != -1; i++) { + if (bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC | INTR_MPSAFE, + NULL, brcm_dma_intr, sc, + &sc->intr_hl[i]) != 0) { + device_printf(dev, "Unable to setup the clock irq handler.\n"); + goto fail; + } + } + + mtx_init(&sc->lock, "vcio dma", MTX_DEF, 0); + + brcm_dma_sc = sc; + + return (0); +fail: + /* TODO: teardown */ + bus_release_resources(dev, bcm_dma_irq_spec, sc->irq_res); + + return (ENXIO); +} + +static device_method_t brcm_dma_methods[] = { + DEVMETHOD(device_probe, brcm_dma_probe), + DEVMETHOD(device_attach, brcm_dma_attach), + { 0, 0 } +}; + +static driver_t brcm_dma_driver = { + "dma", + brcm_dma_methods, + sizeof(struct brcm_dma_softc), +}; + +static devclass_t brcm_dma_devclass; + +DRIVER_MODULE(dma, simplebus, brcm_dma_driver, brcm_dma_devclass, 0, 0); Property changes on: sys/arm/broadcom/bcm2835/dma.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/bcm2835_machdep.c =================================================================== --- sys/arm/broadcom/bcm2835/bcm2835_machdep.c (revision 0) +++ sys/arm/broadcom/bcm2835/bcm2835_machdep.c (working copy) @@ -0,0 +1,603 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko. + * Copyright (c) 1994-1998 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 + */ + +#include "opt_ddb.h" +#include "opt_platform.h" +#include "opt_global.h" + +#include +__FBSDID("$FreeBSD$"); + +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DEBUG +#ifdef DEBUG +#define debugf(fmt, args...) printf(fmt, ##args) +#else +#define debugf(fmt, args...) +#endif + +/* Start of address space used for bootstrap map */ +#define DEVMAP_BOOTSTRAP_MAP_START 0xE0000000 + +/* + * This is the number of L2 page tables required for covering max + * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf, + * stacks etc.), uprounded to be divisible by 4. + */ +#define KERNEL_PT_MAX 78 + +/* Define various stack sizes in pages */ +#define IRQ_STACK_SIZE 1 +#define ABT_STACK_SIZE 1 +#define UND_STACK_SIZE 1 + +extern unsigned char kernbase[]; +extern unsigned char _etext[]; +extern unsigned char _edata[]; +extern unsigned char __bss_start[]; +extern unsigned char _end[]; + +#ifdef DDB +extern vm_offset_t ksym_start, ksym_end; +#endif + +extern u_int data_abort_handler_address; +extern u_int prefetch_abort_handler_address; +extern u_int undefined_handler_address; + +extern vm_offset_t pmap_bootstrap_lastaddr; +extern int *end; + +struct pv_addr kernel_pt_table[KERNEL_PT_MAX]; + +/* Physical and virtual addresses for some global pages */ +vm_paddr_t phys_avail[10]; +vm_paddr_t dump_avail[4]; +vm_offset_t physical_pages; +vm_offset_t pmap_bootstrap_lastaddr; +vm_paddr_t pmap_pa; + +const struct pmap_devmap *pmap_devmap_bootstrap_table; +struct pv_addr systempage; +struct pv_addr msgbufpv; +struct pv_addr irqstack; +struct pv_addr undstack; +struct pv_addr abtstack; +struct pv_addr kernelstack; + +void set_stackptrs(int cpu); + +static struct mem_region availmem_regions[FDT_MEM_REGIONS]; +static int availmem_regions_sz; + +static void print_kenv(void); +static void print_kernel_section_addr(void); + +static void physmap_init(void); +static int platform_devmap_init(void); + +static char * +kenv_next(char *cp) +{ + + if (cp != NULL) { + while (*cp != 0) + cp++; + cp++; + if (*cp == 0) + cp = NULL; + } + return (cp); +} + +static void +print_kenv(void) +{ + int len; + char *cp; + + debugf("loader passed (static) kenv:\n"); + if (kern_envp == NULL) { + debugf(" no env, null ptr\n"); + return; + } + debugf(" kern_envp = 0x%08x\n", (uint32_t)kern_envp); + + len = 0; + for (cp = kern_envp; cp != NULL; cp = kenv_next(cp)) + debugf(" %x %s\n", (uint32_t)cp, cp); +} + +static void +print_kernel_section_addr(void) +{ + + debugf("kernel image addresses:\n"); + debugf(" kernbase = 0x%08x\n", (uint32_t)kernbase); + debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext); + debugf(" _edata = 0x%08x\n", (uint32_t)_edata); + debugf(" __bss_start = 0x%08x\n", (uint32_t)__bss_start); + debugf(" _end = 0x%08x\n", (uint32_t)_end); +} + +static void +physmap_init(void) +{ + int i, j, cnt; + vm_offset_t phys_kernelend, kernload; + uint32_t s, e, sz; + struct mem_region *mp, *mp1; + + phys_kernelend = KERNPHYSADDR + (virtual_avail - KERNVIRTADDR); + kernload = KERNPHYSADDR; + + /* + * Remove kernel physical address range from avail + * regions list. Page align all regions. + * Non-page aligned memory isn't very interesting to us. + * Also, sort the entries for ascending addresses. + */ + sz = 0; + cnt = availmem_regions_sz; + debugf("processing avail regions:\n"); + for (mp = availmem_regions; mp->mr_size; mp++) { + s = mp->mr_start; + e = mp->mr_start + mp->mr_size; + debugf(" %08x-%08x -> ", s, e); + /* Check whether this region holds all of the kernel. */ + if (s < kernload && e > phys_kernelend) { + availmem_regions[cnt].mr_start = phys_kernelend; + availmem_regions[cnt++].mr_size = e - phys_kernelend; + e = kernload; + } + /* Look whether this regions starts within the kernel. */ + if (s >= kernload && s < phys_kernelend) { + if (e <= phys_kernelend) + goto empty; + s = phys_kernelend; + } + /* Now look whether this region ends within the kernel. */ + if (e > kernload && e <= phys_kernelend) { + if (s >= kernload) { + goto empty; + } + e = kernload; + } + /* Now page align the start and size of the region. */ + s = round_page(s); + e = trunc_page(e); + if (e < s) + e = s; + sz = e - s; + debugf("%08x-%08x = %x\n", s, e, sz); + + /* Check whether some memory is left here. */ + if (sz == 0) { + empty: + printf("skipping\n"); + bcopy(mp + 1, mp, + (cnt - (mp - availmem_regions)) * sizeof(*mp)); + cnt--; + mp--; + continue; + } + + /* Do an insertion sort. */ + for (mp1 = availmem_regions; mp1 < mp; mp1++) + if (s < mp1->mr_start) + break; + if (mp1 < mp) { + bcopy(mp1, mp1 + 1, (char *)mp - (char *)mp1); + mp1->mr_start = s; + mp1->mr_size = sz; + } else { + mp->mr_start = s; + mp->mr_size = sz; + } + } + availmem_regions_sz = cnt; + + /* Fill in phys_avail table, based on availmem_regions */ + debugf("fill in phys_avail:\n"); + for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { + + debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", + availmem_regions[i].mr_start, + availmem_regions[i].mr_start + availmem_regions[i].mr_size, + availmem_regions[i].mr_size); + + phys_avail[j] = availmem_regions[i].mr_start; + phys_avail[j + 1] = availmem_regions[i].mr_start + + availmem_regions[i].mr_size; + } + phys_avail[j] = 0; + phys_avail[j + 1] = 0; +} + +void * +initarm(struct arm_boot_params *abp) +{ + struct pv_addr kernel_l1pt; + struct pv_addr dpcpu; + vm_offset_t dtbp, freemempos, l2_start, lastaddr; + uint32_t memsize, l2size; + void *kmdp; + u_int l1pagetable; + int i = 0, j = 0; + + lastaddr = fake_preload_metadata(abp); + memsize = 0; + set_cpufuncs(); + + kmdp = preload_search_by_type("elf kernel"); + if (kmdp != NULL) + dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); + else + dtbp = (vm_offset_t)NULL; + +#if defined(FDT_DTB_STATIC) + /* + * In case the device tree blob was not retrieved (from metadata) try + * to use the statically embedded one. + */ + if (dtbp == (vm_offset_t)NULL) + dtbp = (vm_offset_t)&fdt_static_dtb; +#endif + + if (OF_install(OFW_FDT, 0) == FALSE) + while (1); + + if (OF_init((void *)dtbp) != 0) + while (1); + + /* Grab physical memory regions information from device tree. */ + if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz, + &memsize) != 0) + while(1); + + /* Platform-specific initialisation */ + pmap_bootstrap_lastaddr = DEVMAP_BOOTSTRAP_MAP_START - ARM_NOCACHE_KVA_SIZE; + + pcpu0_init(); + + /* Calculate number of L2 tables needed for mapping vm_page_array */ + l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page); + l2size = (l2size >> L1_S_SHIFT) + 1; + + /* + * Add one table for end of kernel map, one for stacks, msgbuf and + * L1 and L2 tables map and one for vectors map. + */ + l2size += 3; + + /* Make it divisible by 4 */ + l2size = (l2size + 3) & ~3; + +#define KERNEL_TEXT_BASE (KERNBASE) + freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; + + /* Define a macro to simplify memory allocation */ +#define valloc_pages(var, np) \ + alloc_pages((var).pv_va, (np)); \ + (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR); + +#define alloc_pages(var, np) \ + (var) = freemempos; \ + freemempos += (np * PAGE_SIZE); \ + memset((char *)(var), 0, ((np) * PAGE_SIZE)); + + while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) + freemempos += PAGE_SIZE; + valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); + + for (i = 0; i < l2size; ++i) { + if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { + valloc_pages(kernel_pt_table[i], + L2_TABLE_SIZE / PAGE_SIZE); + j = i; + } else { + kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va + + L2_TABLE_SIZE_REAL * (i - j); + kernel_pt_table[i].pv_pa = + kernel_pt_table[i].pv_va - KERNVIRTADDR + + KERNPHYSADDR; + + } + } + /* + * Allocate a page for the system page mapped to 0x00000000 + * or 0xffff0000. This page will just contain the system vectors + * and can be shared by all processes. + */ + valloc_pages(systempage, 1); + + /* Allocate dynamic per-cpu area. */ + valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); + dpcpu_init((void *)dpcpu.pv_va, 0); + + /* Allocate stacks for all modes */ + valloc_pages(irqstack, (IRQ_STACK_SIZE * MAXCPU)); + valloc_pages(abtstack, (ABT_STACK_SIZE * MAXCPU)); + valloc_pages(undstack, (UND_STACK_SIZE * MAXCPU)); + valloc_pages(kernelstack, (KSTACK_PAGES * MAXCPU)); + + init_param1(); + + valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); + + /* + * Now we start construction of the L1 page table + * We start by mapping the L2 page tables into the L1. + * This means that we can replace L1 mappings later on if necessary + */ + l1pagetable = kernel_l1pt.pv_va; + + /* + * Try to map as much as possible of kernel text and data using + * 1MB section mapping and for the rest of initial kernel address + * space use L2 coarse tables. + * + * Link L2 tables for mapping remainder of kernel (modulo 1MB) + * and kernel structures + */ + l2_start = lastaddr & ~(L1_S_OFFSET); + for (i = 0 ; i < l2size - 1; i++) + pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE, + &kernel_pt_table[i]); + + pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE; + + /* Map kernel code and data */ + pmap_map_chunk(l1pagetable, KERNVIRTADDR, KERNPHYSADDR, + (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + /* Map L1 directory and allocated L2 page tables */ + pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, + L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); + + pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va, + kernel_pt_table[0].pv_pa, + L2_TABLE_SIZE_REAL * l2size, + VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); + + /* Map allocated DPCPU, stacks and msgbuf */ + pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, + freemempos - dpcpu.pv_va, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + + /* Map allocated DPCPU, stacks and msgbuf */ + pmap_map_chunk(l1pagetable, 0xf2200000, 0x20200000, + 0x00100000, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + /* Link and map the vector page */ + pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, + &kernel_pt_table[l2size - 1]); + pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, + VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE); + + /* Map pmap_devmap[] entries */ + if (platform_devmap_init() != 0) + while (1); + pmap_devmap_bootstrap(l1pagetable, pmap_devmap_bootstrap_table); + + cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | + DOMAIN_CLIENT); + + pmap_pa = kernel_l1pt.pv_pa; + + setttb(kernel_l1pt.pv_pa); + cpu_tlb_flushID(); + cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); + + /* + * Only after the SOC registers block is mapped we can perform device + * tree fixups, as they may attempt to read parameters from hardware. + */ + OF_interpret("perform-fixup", 0); + + cninit(); + + physmem = memsize / PAGE_SIZE; + + debugf("initarm: console initialized\n"); + debugf(" arg1 mmdp = 0x%08x\n", (uint32_t)kmdp); + debugf(" boothowto = 0x%08x\n", boothowto); + debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); + print_kernel_section_addr(); + print_kenv(); + + /* + * Pages were allocated during the secondary bootstrap for the + * stacks for different CPU modes. + * We must now set the r13 registers in the different CPU modes to + * point to these stacks. + * Since the ARM stacks use STMFD etc. we must set r13 to the top end + * of the stack memory. + */ + cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); + + set_stackptrs(0); + + /* + * We must now clean the cache again.... + * Cleaning may be done by reading new data to displace any + * dirty data in the cache. This will have happened in setttb() + * but since we are boot strapping the addresses used for the read + * may have just been remapped and thus the cache could be out + * of sync. A re-clean after the switch will cure this. + * After booting there are no gross relocations of the kernel thus + * this problem will not occur after initarm(). + */ + cpu_idcache_wbinv_all(); + + /* Set stack for exception handlers */ + data_abort_handler_address = (u_int)data_abort_handler; + prefetch_abort_handler_address = (u_int)prefetch_abort_handler; + undefined_handler_address = (u_int)undefinedinstruction_bounce; + undefined_init(); + + init_proc0(kernelstack.pv_va); + + arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); + + arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0])); + pmap_bootstrap(freemempos, pmap_bootstrap_lastaddr, &kernel_l1pt); + msgbufp = (void *)msgbufpv.pv_va; + msgbufinit(msgbufp, msgbufsize); + mutex_init(); + + /* + * Prepare map of physical memory regions available to vm subsystem. + */ + physmap_init(); + + /* Do basic tuning, hz etc */ + init_param2(physmem); + kdb_init(); + + return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - + sizeof(struct pcb))); +} + +void +set_stackptrs(int cpu) +{ + + set_stackptr(PSR_IRQ32_MODE, + irqstack.pv_va + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); + set_stackptr(PSR_ABT32_MODE, + abtstack.pv_va + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); + set_stackptr(PSR_UND32_MODE, + undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); +} + +#define FDT_DEVMAP_MAX (2) // FIXME +static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { + { 0, 0, 0, 0, 0, } +}; + + +/* + * Construct pmap_devmap[] with DT-derived config data. + */ +static int +platform_devmap_init(void) +{ + int i = 0; + + fdt_devmap[i].pd_va = 0xf2000000; + fdt_devmap[i].pd_pa = 0x20000000; + fdt_devmap[i].pd_size = 0x01000000; /* 1 MB */ + fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; + fdt_devmap[i].pd_cache = PTE_DEVICE; + i++; + + pmap_devmap_bootstrap_table = &fdt_devmap[0]; + return (0); +} + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + + return (0); +} + +void +cpu_reset() +{ + bcmwd_watchdog_reset(); + while (1); +} Property changes on: sys/arm/broadcom/bcm2835/bcm2835_machdep.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/bus_space.c =================================================================== --- sys/arm/broadcom/bcm2835/bus_space.c (revision 0) +++ sys/arm/broadcom/bcm2835/bus_space.c (working copy) @@ -0,0 +1,113 @@ +/*- + * Copyright (C) 2012 FreeBSD Foundation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of MARVELL nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include + +/* Prototypes for all the bus_space structure functions */ +bs_protos(generic); +bs_protos(generic_armv4); + +struct bus_space _base_tag = { + /* cookie */ + .bs_cookie = (void *) 0, + + /* mapping/unmapping */ + .bs_map = generic_bs_map, + .bs_unmap = generic_bs_unmap, + .bs_subregion = generic_bs_subregion, + + /* allocation/deallocation */ + .bs_alloc = generic_bs_alloc, + .bs_free = generic_bs_free, + + /* barrier */ + .bs_barrier = generic_bs_barrier, + + /* read (single) */ + .bs_r_1 = generic_bs_r_1, + .bs_r_2 = generic_armv4_bs_r_2, + .bs_r_4 = generic_bs_r_4, + .bs_r_8 = NULL, + + /* read multiple */ + .bs_rm_1 = generic_bs_rm_1, + .bs_rm_2 = generic_armv4_bs_rm_2, + .bs_rm_4 = generic_bs_rm_4, + .bs_rm_8 = NULL, + + /* read region */ + .bs_rr_1 = generic_bs_rr_1, + .bs_rr_2 = generic_armv4_bs_rr_2, + .bs_rr_4 = generic_bs_rr_4, + .bs_rr_8 = NULL, + + /* write (single) */ + .bs_w_1 = generic_bs_w_1, + .bs_w_2 = generic_armv4_bs_w_2, + .bs_w_4 = generic_bs_w_4, + .bs_w_8 = NULL, + + /* write multiple */ + .bs_wm_1 = generic_bs_wm_1, + .bs_wm_2 = generic_armv4_bs_wm_2, + .bs_wm_4 = generic_bs_wm_4, + .bs_wm_8 = NULL, + + /* write region */ + .bs_wr_1 = generic_bs_wr_1, + .bs_wr_2 = generic_armv4_bs_wr_2, + .bs_wr_4 = generic_bs_wr_4, + .bs_wr_8 = NULL, + + /* set multiple */ + /* XXX not implemented */ + + /* set region */ + .bs_sr_1 = NULL, + .bs_sr_2 = generic_armv4_bs_sr_2, + .bs_sr_4 = generic_bs_sr_4, + .bs_sr_8 = NULL, + + /* copy */ + .bs_c_1 = NULL, + .bs_c_2 = generic_armv4_bs_c_2, + .bs_c_4 = NULL, + .bs_c_8 = NULL, +}; + +bus_space_tag_t fdtbus_bs_tag = &_base_tag; Property changes on: sys/arm/broadcom/bcm2835/bus_space.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/dma.h =================================================================== --- sys/arm/broadcom/bcm2835/dma.h (revision 0) +++ sys/arm/broadcom/bcm2835/dma.h (working copy) @@ -0,0 +1,38 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _BCM2835_DMA_H_ +#define _BCM2835_DMA_H_ + +typedef int dma_channel_t; + +dma_channel_t bcm_dma_allocate_chan(void); +void bcm_dma_release_chan(dma_channel_t); +int bcm_dma_setup(vm_paddr_t src, vm_paddr_t dst, vm_offset_t len); +int bcm_dma_start(dma_channel_t); +int bcm_dma_abort(dma_channel_t); + +#endif /* _BCM2835_DMA_H_ */ Property changes on: sys/arm/broadcom/bcm2835/dma.h ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/vcbus.h =================================================================== --- sys/arm/broadcom/bcm2835/vcbus.h (revision 0) +++ sys/arm/broadcom/bcm2835/vcbus.h (working copy) @@ -0,0 +1,50 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Defines for converting physical address to VideoCore bus address and back + */ + +#ifndef _BCM2835_VCBUS_H_ +#define _BCM2835_VCBUS_H_ + +#define BCM2835_VCBUS_SDRAM_CACHED 0x40000000 +#define BCM2835_VCBUS_SDRAM_UNCACHED 0xC0000000 + +/* + * Convert physical address to VC bus address. Should be used + * when submitting address over mailbox interface + */ +#define PHYS_TO_VCBUS(pa) ((pa) + BCM2835_VCBUS_SDRAM_CACHED) + +/* + * Convert address from VC bus space to physical. Should be used + * when address is returned by VC over mailbox interface. e.g. + * framebuffer base + */ +#define VCBUS_TO_PHYS(vca) ((vca) - BCM2835_VCBUS_SDRAM_CACHED) + +#endif /* _BCM2835_VCBUS_H_ */ Property changes on: sys/arm/broadcom/bcm2835/vcbus.h ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/common.c =================================================================== --- sys/arm/broadcom/bcm2835/common.c (revision 0) +++ sys/arm/broadcom/bcm2835/common.c (working copy) @@ -0,0 +1,75 @@ +/*- + * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. + * All rights reserved. + * + * Developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of MARVELL nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "opt_global.h" + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +struct fdt_fixup_entry fdt_fixup_table[] = { + { NULL, NULL } +}; + +static int +fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, + int *pol) +{ + + if (!fdt_is_compatible(node, "broadcom,bcm2835-armctrl-ic")) + return (ENXIO); + + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + + return (0); +} + + +fdt_pic_decode_t fdt_pic_table[] = { + &fdt_intc_decode_ic, + NULL +}; Property changes on: sys/arm/broadcom/bcm2835/common.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/dwc_otg_brcm.c =================================================================== --- sys/arm/broadcom/bcm2835/dwc_otg_brcm.c (revision 0) +++ sys/arm/broadcom/bcm2835/dwc_otg_brcm.c (working copy) @@ -0,0 +1,211 @@ +/*- + * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +static device_probe_t dwc_otg_probe; +static device_attach_t dwc_otg_attach; +static device_detach_t dwc_otg_detach; + +struct dwc_otg_super_softc { + struct dwc_otg_softc sc_otg; /* must be first */ +}; + +static int +dwc_otg_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "synopsys,designware-hs-otg2")) + return (ENXIO); + + device_set_desc(dev, "DWC OTG 2.0 integrated USB controller"); + + return (0); +} + +static int +dwc_otg_attach(device_t dev) +{ + struct dwc_otg_super_softc *sc = device_get_softc(dev); + int err; + int rid; + + /* initialise some bus fields */ + sc->sc_otg.sc_bus.parent = dev; + sc->sc_otg.sc_bus.devices = sc->sc_otg.sc_devices; + sc->sc_otg.sc_bus.devices_max = DWC_OTG_MAX_DEVICES; + + /* get all DMA memory */ + if (usb_bus_mem_alloc_all(&sc->sc_otg.sc_bus, + USB_GET_DMA_TAG(dev), NULL)) { + return (ENOMEM); + } + rid = 0; + sc->sc_otg.sc_io_res = + bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + + if (!(sc->sc_otg.sc_io_res)) { + err = ENOMEM; + goto error; + } + sc->sc_otg.sc_io_tag = rman_get_bustag(sc->sc_otg.sc_io_res); + sc->sc_otg.sc_io_hdl = rman_get_bushandle(sc->sc_otg.sc_io_res); + sc->sc_otg.sc_io_size = rman_get_size(sc->sc_otg.sc_io_res); + + rid = 0; + sc->sc_otg.sc_irq_res = + bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); + if (sc->sc_otg.sc_irq_res == NULL) + goto error; + + sc->sc_otg.sc_bus.bdev = device_add_child(dev, "usbus", -1); + if (sc->sc_otg.sc_bus.bdev == NULL) + goto error; + + device_set_ivars(sc->sc_otg.sc_bus.bdev, &sc->sc_otg.sc_bus); + + err = bus_setup_intr(dev, sc->sc_otg.sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, + NULL, (driver_intr_t *)dwc_otg_interrupt, sc, &sc->sc_otg.sc_intr_hdl); + if (err) { + sc->sc_otg.sc_intr_hdl = NULL; + goto error; + } + err = dwc_otg_init(&sc->sc_otg); + if (err == 0) { + err = device_probe_and_attach(sc->sc_otg.sc_bus.bdev); + } + if (err) + goto error; + + + return (0); + +error: + dwc_otg_detach(dev); + return (ENXIO); +} + +static int +dwc_otg_detach(device_t dev) +{ + struct dwc_otg_super_softc *sc = device_get_softc(dev); + device_t bdev; + int err; + + if (sc->sc_otg.sc_bus.bdev) { + bdev = sc->sc_otg.sc_bus.bdev; + device_detach(bdev); + device_delete_child(dev, bdev); + } + /* during module unload there are lots of children leftover */ + device_delete_children(dev); + + if (sc->sc_otg.sc_irq_res && sc->sc_otg.sc_intr_hdl) { + /* + * only call dwc_otg_uninit() after dwc_otg_init() + */ + dwc_otg_uninit(&sc->sc_otg); + + err = bus_teardown_intr(dev, sc->sc_otg.sc_irq_res, + sc->sc_otg.sc_intr_hdl); + sc->sc_otg.sc_intr_hdl = NULL; + } + /* free IRQ channel, if any */ + if (sc->sc_otg.sc_irq_res) { + bus_release_resource(dev, SYS_RES_IRQ, 0, + sc->sc_otg.sc_irq_res); + sc->sc_otg.sc_irq_res = NULL; + } + /* free memory resource, if any */ + if (sc->sc_otg.sc_io_res) { + bus_release_resource(dev, SYS_RES_MEMORY, 0, + sc->sc_otg.sc_io_res); + sc->sc_otg.sc_io_res = NULL; + } + usb_bus_mem_free_all(&sc->sc_otg.sc_bus, NULL); + + return (0); +} + +static device_method_t dwc_otg_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, dwc_otg_probe), + DEVMETHOD(device_attach, dwc_otg_attach), + DEVMETHOD(device_detach, dwc_otg_detach), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + + DEVMETHOD_END +}; + +static driver_t dwc_otg_driver = { + .name = "dwcotg", + .methods = dwc_otg_methods, + .size = sizeof(struct dwc_otg_super_softc), +}; + +static devclass_t dwc_otg_devclass; + +DRIVER_MODULE(dwcotg, simplebus, dwc_otg_driver, dwc_otg_devclass, 0, 0); +MODULE_DEPEND(dwcotg, usb, 1, 1, 1); Property changes on: sys/arm/broadcom/bcm2835/dwc_otg_brcm.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/arm/broadcom/bcm2835/sdhci_brcm.c =================================================================== --- sys/arm/broadcom/bcm2835/sdhci_brcm.c (revision 0) +++ sys/arm/broadcom/bcm2835/sdhci_brcm.c (working copy) @@ -0,0 +1,391 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include "sdhci_if.h" + +#define DEBUG + +#ifdef DEBUG +#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ + printf(fmt,##args); } while (0) +#else +#define dprintf(fmt, args...) +#endif + +struct bcm_sdhci_dmamap_arg { + bus_addr_t sc_dma_busaddr; +}; + +struct bcm_sdhci_softc { + device_t sc_dev; + struct mtx sc_mtx; + struct resource * sc_mem_res; + struct resource * sc_irq_res; + bus_space_tag_t sc_bst; + bus_space_handle_t sc_bsh; + void * sc_intrhand; + struct mmc_request * sc_req; + struct mmc_data * sc_data; + uint32_t sc_flags; +#define LPC_SD_FLAGS_IGNORECRC (1 << 0) + int sc_xfer_direction; +#define DIRECTION_READ 0 +#define DIRECTION_WRITE 1 + int sc_xfer_done; + int sc_bus_busy; + bus_dma_tag_t sc_dma_tag; + bus_dmamap_t sc_dma_map; + bus_addr_t sc_buffer_phys; + void * sc_buffer; + struct sdhci_slot sc_slot; +}; + +#define SD_MAX_BLOCKSIZE 1024 +/* XXX */ + +static int bcm_sdhci_probe(device_t); +static int bcm_sdhci_attach(device_t); +static int bcm_sdhci_detach(device_t); +static void bcm_sdhci_intr(void *); + +static int bcm_sdhci_get_ro(device_t, device_t); + +static void bcm_sdhci_dmamap_cb(void *, bus_dma_segment_t *, int, int); + +#define bcm_sdhci_lock(_sc) \ + mtx_lock(&_sc->sc_mtx); +#define bcm_sdhci_unlock(_sc) \ + mtx_unlock(&_sc->sc_mtx); + +static int +bcm_sdhci_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) + return (ENXIO); + + device_set_desc(dev, "Broadcom 2708 SDHCI controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +bcm_sdhci_attach(device_t dev) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + struct bcm_sdhci_dmamap_arg ctx; + int rid, err; + + sc->sc_dev = dev; + sc->sc_req = NULL; + + mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); + + rid = 0; + sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->sc_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->sc_bst = rman_get_bustag(sc->sc_mem_res); + sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); + + rid = 0; + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (!sc->sc_irq_res) { + device_printf(dev, "cannot allocate interrupt\n"); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + return (ENXIO); + } + + if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) + { + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + +#if 0 + sc->sc_host.f_min = 312500; + sc->sc_host.f_max = 2500000; + sc->sc_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 | + MMC_OCR_320_330 | MMC_OCR_330_340; + sc->sc_host.caps = MMC_CAP_4_BIT_DATA; +#endif + + /* Alloc DMA memory */ + err = bus_dma_tag_create( + bus_get_dma_tag(sc->sc_dev), + 4, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + SD_MAX_BLOCKSIZE, 1, /* maxsize, nsegments */ + SD_MAX_BLOCKSIZE, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dma_tag); + + err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_buffer, + 0, &sc->sc_dma_map); + if (err) { + device_printf(dev, "cannot allocate DMA memory\n"); + goto fail; + } + + err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_buffer, + SD_MAX_BLOCKSIZE, bcm_sdhci_dmamap_cb, &ctx, BUS_DMA_NOWAIT); + if (err) { + device_printf(dev, "cannot load DMA map\n"); + goto fail; + } + + sc->sc_buffer_phys = ctx.sc_dma_busaddr; + + /* TODO: allocate DMA here */ + sdhci_init_slot(dev, &sc->sc_slot); + sc->sc_slot.mem_res = sc->sc_mem_res; + + bus_generic_probe(dev); + bus_generic_attach(dev); + + return (0); + +fail: + if (sc->sc_intrhand) + bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); + if (sc->sc_irq_res) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + if (sc->sc_mem_res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + return (err); +} + +static int +bcm_sdhci_detach(device_t dev) +{ + + return (EBUSY); +} + +static void +bcm_sdhci_intr(void *arg) +{ + struct bcm_sdhci_softc *sc = arg; + + sdhci_generic_intr(&sc->sc_slot); +} + +static int +bcm_sdhci_get_ro(device_t bus, device_t child) +{ + + return (0); +} + +static void +bcm_sdhci_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) +{ + struct bcm_sdhci_dmamap_arg *ctx; + + if (err) + return; + + ctx = (struct bcm_sdhci_dmamap_arg *)arg; + ctx->sc_dma_busaddr = segs[0].ds_addr; +} + +static inline uint32_t +RD4(struct bcm_sdhci_softc *sc, bus_size_t off) +{ + uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); + // printf("RD4 [%02x] == %08x\n", (unsigned int)off, val); + return val; +} + +static inline void +WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) +{ + // printf("WR4 [%02x] := %08x\n", (unsigned int)off, val); + bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); + + if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL)) + { + int timeout = 100000; + while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off) + && --timeout > 0) + continue; + + if (timeout <= 0) + printf("sdhci_brcm: writing 0x%X to reg 0x%X " + "always gives 0x%X\n", + val, (uint32_t)off, + bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)); + } +} + +static uint8_t +bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + uint32_t val = RD4(sc, off & ~3); + + return ((val >> (off & 3)*8) & 0xff); +} + +static uint16_t +bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + uint32_t val = RD4(sc, off & ~3); + + return ((val >> (off & 3)*8) & 0xffff); +} + +static uint32_t +bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + + return RD4(sc, off); +} + +static void +bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + uint32_t val32 = RD4(sc, off & ~3); + val32 &= ~(0xff << (off & 3)*8); + val32 |= (val << (off & 3)*8); + WR4(sc, off & ~3, val32); +} + +static void +bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + static uint32_t cmd_and_trandfer_mode; + uint32_t val32; + if (off == SDHCI_COMMAND_FLAGS) + val32 = cmd_and_trandfer_mode; + else + val32 = RD4(sc, off & ~3); + val32 &= ~(0xffff << (off & 3)*8); + val32 |= (val << (off & 3)*8); + if (off == SDHCI_TRANSFER_MODE) + cmd_and_trandfer_mode = val32; + else + WR4(sc, off & ~3, val32); +} + +static void +bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + WR4(sc, off, val); +} + +static device_method_t bcm_sdhci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bcm_sdhci_probe), + DEVMETHOD(device_attach, bcm_sdhci_attach), + DEVMETHOD(device_detach, bcm_sdhci_detach), + + /* Bus interface */ + DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), + DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), + DEVMETHOD(bus_print_child, bus_generic_print_child), + + /* MMC bridge interface */ + DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), + DEVMETHOD(mmcbr_request, sdhci_generic_request), + DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), + DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), + DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), + + + /* SDHCI registers accessors */ + DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), + DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), + DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), + DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), + DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), + DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), + + { 0, 0 } +}; + +static devclass_t bcm_sdhci_devclass; + +static driver_t bcm_sdhci_driver = { + "sdhci", + bcm_sdhci_methods, + sizeof(struct bcm_sdhci_softc), +}; + +DRIVER_MODULE(sdhci, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); Property changes on: sys/arm/broadcom/bcm2835/sdhci_brcm.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/conf/files =================================================================== --- sys/conf/files (revision 239664) +++ sys/conf/files (working copy) @@ -1887,7 +1887,9 @@ dev/scc/scc_dev_z8530.c optional scc dev/scd/scd.c optional scd isa dev/scd/scd_isa.c optional scd isa -dev/sdhci/sdhci.c optional sdhci pci +dev/sdhci/sdhci_if.m optional sdhci +dev/sdhci/sdhci.c optional sdhci +dev/sdhci/sdhci_pci.c optional sdhci pci dev/sf/if_sf.c optional sf pci dev/sge/if_sge.c optional sge pci dev/si/si.c optional si @@ -2064,6 +2066,7 @@ dev/uart/uart_dev_sab82532.c optional uart scc dev/uart/uart_dev_z8530.c optional uart uart_z8530 dev/uart/uart_dev_z8530.c optional uart scc +dev/uart/uart_dev_pl011.c optional uart pl011 dev/uart/uart_if.m optional uart dev/uart/uart_subr.c optional uart dev/uart/uart_tty.c optional uart @@ -2073,6 +2076,7 @@ # dev/usb/controller/at91dci.c optional at91dci dev/usb/controller/at91dci_atmelarm.c optional at91dci at91rm9200 +dev/usb/controller/dwc_otg.c optional dwc_otg dev/usb/controller/musb_otg.c optional musb dev/usb/controller/musb_otg_atmelarm.c optional musb at91rm9200 dev/usb/controller/ehci.c optional ehci Index: sys/conf/files.arm =================================================================== --- sys/conf/files.arm (revision 239664) +++ sys/conf/files.arm (working copy) @@ -1,4 +1,9 @@ # $FreeBSD$ +font.h optional sc \ + compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ + no-obj no-implicit-rule before-depend \ + clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" + crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb arm/arm/autoconf.c standard @@ -37,6 +42,7 @@ arm/arm/pl310.c optional pl310 arm/arm/pmap.c optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 | cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0 arm/arm/pmap-v6.c optional cpu_arm11 | cpu_cortexa | cpu_mv_pj4b +arm/arm/sc_machdep.c optional sc arm/arm/setcpsr.S standard arm/arm/setstack.s standard arm/arm/stack_machdep.c optional ddb | stack @@ -53,13 +59,18 @@ arm/fpe-arm/armfpe_init.c optional armfpe arm/fpe-arm/armfpe.S optional armfpe cddl/compat/opensolaris/kern/opensolaris_atomic.c optional zfs compile-with "${ZFS_C}" +dev/fb/fb.c optional sc dev/hwpmc/hwpmc_arm.c optional hwpmc +dev/kbd/kbd.c optional sc dev/ofw/openfirm.c optional fdt dev/ofw/openfirmio.c optional fdt dev/ofw/ofw_bus_if.m optional fdt dev/ofw/ofw_if.m optional fdt dev/ofw/ofw_bus_subr.c optional fdt dev/ofw/ofw_fdt.c optional fdt +dev/syscons/scgfbrndr.c optional sc +dev/syscons/scterm-teken.c optional sc +dev/syscons/scvtb.c optional sc geom/geom_bsd.c optional geom_bsd geom/geom_bsd_enc.c optional geom_bsd geom/geom_mbr.c optional geom_mbr Index: sys/conf/Makefile.arm =================================================================== --- sys/conf/Makefile.arm (revision 239664) +++ sys/conf/Makefile.arm (working copy) @@ -68,7 +68,7 @@ $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S KERNEL_EXTRA=trampoline -KERNEL_EXTRA_INSTALL=kernel.gz.tramp +# KERNEL_EXTRA_INSTALL= trampoline: ${KERNEL_KO}.tramp ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern.S $S/$M/$M/elf_trampoline.c echo "#define KERNNAME \"${KERNEL_KO}.tmp\"" >opt_kernname.h Index: sys/conf/options.arm =================================================================== --- sys/conf/options.arm (revision 239664) +++ sys/conf/options.arm (working copy) @@ -55,4 +55,7 @@ AT91_ATE_USE_RMII opt_at91.h AT91_MCI_HAS_4WIRE opt_at91.h AT91_MCI_SLOT_B opt_at91.h +GFB_DEBUG opt_gfb.h +GFB_NO_FONT_LOADING opt_gfb.h +GFB_NO_MODE_CHANGE opt_gfb.h AT91C_MAIN_CLOCK opt_at91.h Index: sys/kern/vfs_mountroot.c =================================================================== --- sys/kern/vfs_mountroot.c (revision 239664) +++ sys/kern/vfs_mountroot.c (working copy) @@ -721,6 +721,7 @@ delay = hz / 10; timeout = root_mount_timeout * hz; do { + printf("delay = %d, timeout = %d\n", delay, timeout); pause("rmdev", delay); timeout -= delay; } while (timeout > 0 && !parse_mount_dev_present(dev)); Index: sys/dev/uart/uart_bus_fdt.c =================================================================== --- sys/dev/uart/uart_bus_fdt.c (revision 239664) +++ sys/dev/uart/uart_bus_fdt.c (working copy) @@ -105,6 +105,8 @@ sc->sc_class = &uart_ns8250_class; else if (ofw_bus_is_compatible(dev, "lpc,uart")) sc->sc_class = &uart_lpc_class; + else if (ofw_bus_is_compatible(dev, "arm,pl011")) + sc->sc_class = &uart_pl011_class; else return (ENXIO); @@ -188,6 +190,8 @@ class = &uart_lpc_class; if (fdt_is_compatible(node, "ns16550")) class = &uart_ns8250_class; + if (fdt_is_compatible(node, "arm,pl011")) + class = &uart_pl011_class; di->bas.chan = 0; di->bas.regshft = (u_int)shift; Index: sys/dev/uart/uart_dev_pl011.c =================================================================== --- sys/dev/uart/uart_dev_pl011.c (revision 0) +++ sys/dev/uart/uart_dev_pl011.c (working copy) @@ -0,0 +1,433 @@ +/*- + * Copyright (c) 2012 Semihalf. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include +#include +#include +#include "uart_if.h" + +#include + +/* PL011 UART registers and masks*/ +#define UART_DR 0x00 /* Data register */ +#define DR_FE (1 << 8) /* Framing error */ +#define DR_PE (1 << 9) /* Parity error */ +#define DR_BE (1 << 10) /* Break error */ +#define DR_OE (1 << 11) /* Overrun error */ + +#define UART_FR 0x06 /* Flag register */ +#define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ +#define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ + +#define UART_IBRD 0x09 /* Integer baud rate register */ +#define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ + +#define UART_FBRD 0x0a /* Fractional baud rate register */ +#define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ + +#define UART_LCR_H 0x0b /* Line control register */ +#define LCR_H_WLEN8 (0x3 << 5) +#define LCR_H_WLEN7 (0x2 << 5) +#define LCR_H_WLEN6 (0x1 << 5) +#define LCR_H_FEN (1 << 4) /* FIFO mode enable */ +#define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ +#define LCR_H_EPS (1 << 2) /* Even parity select */ +#define LCR_H_PEN (1 << 1) /* Parity enable */ + +#define UART_CR 0x0c /* Control register */ +#define CR_RXE (1 << 9) /* Receive enable */ +#define CR_TXE (1 << 8) /* Transmit enable */ +#define CR_UARTEN (1 << 0) /* UART enable */ + +#define UART_IMSC 0x0e /* Interrupt mask set/clear register */ +#define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ + +#define UART_RIS 0x0f /* Raw interrupt status register */ +#define UART_RXREADY (1 << 4) /* RX buffer full */ +#define UART_TXEMPTY (1 << 5) /* TX buffer empty */ +#define RIS_FE (1 << 7) /* Framing error interrupt status */ +#define RIS_PE (1 << 8) /* Parity error interrupt status */ +#define RIS_BE (1 << 9) /* Break error interrupt status */ +#define RIS_OE (1 << 10) /* Overrun interrupt status */ + +#define UART_MIS 0x10 /* Masked interrupt status register */ +#define UART_ICR 0x11 /* Interrupt clear register */ + +#define __uart_getreg(bas, reg) \ + bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) +#define __uart_setreg(bas, reg, value) \ + bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) + +/* + * Low-level UART interface. + */ +static int uart_pl011_probe(struct uart_bas *bas); +static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); +static void uart_pl011_term(struct uart_bas *bas); +static void uart_pl011_putc(struct uart_bas *bas, int); +static int uart_pl011_rxready(struct uart_bas *bas); +static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); + +static struct uart_ops uart_pl011_ops = { + .probe = uart_pl011_probe, + .init = uart_pl011_init, + .term = uart_pl011_term, + .putc = uart_pl011_putc, + .rxready = uart_pl011_rxready, + .getc = uart_pl011_getc, +}; + +static int +uart_pl011_probe(struct uart_bas *bas) +{ + + return (0); +} + +static void +uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, + int parity) +{ + uint32_t ctrl, line; + uint32_t baud; + + /* Mask all interrupts */ + __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & + ~IMSC_MASK_ALL); + + /* + * Zero all settings to make sure + * UART is disabled and not configured + */ + ctrl = line = 0x0; + __uart_setreg(bas, UART_CR, ctrl); + + /* As we know UART is disabled we may setup the line */ + switch (databits) { + case 7: + line |= LCR_H_WLEN7; + break; + case 6: + line |= LCR_H_WLEN6; + break; + case 8: + default: + line |= LCR_H_WLEN8; + break; + } + + /* TODO: Calculate divisors */ + baud = (0x1 << 16) | 0x28; + + if (stopbits == 2) + line |= LCR_H_STP2; + else + line &= ~LCR_H_STP2; + + if (parity) + line |= LCR_H_PEN; + else + line &= ~LCR_H_PEN; + + /* Configure the rest */ + line &= ~LCR_H_FEN; + ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); + + __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 16)) & IBRD_BDIVINT); + __uart_setreg(bas, UART_FBRD, (uint32_t)(baud) & FBRD_BDIVFRAC); + + /* Add config. to line before reenabling UART */ + __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & + ~0xff) | line); + + __uart_setreg(bas, UART_CR, ctrl); +} + +static void +uart_pl011_term(struct uart_bas *bas) +{ +} + +static void +uart_pl011_putc(struct uart_bas *bas, int c) +{ + + while (!(__uart_getreg(bas, UART_FR) & FR_TXFE)) + ; + __uart_setreg(bas, UART_DR, c & 0xff); +} + +static int +uart_pl011_rxready(struct uart_bas *bas) +{ + + return (__uart_getreg(bas, UART_FR) & FR_RXFF); +} + +static int +uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) +{ + int c; + + while (!uart_pl011_rxready(bas)) + ; + c = __uart_getreg(bas, UART_DR) & 0xff; + + return (c); +} + +/* + * High-level UART interface. + */ +struct uart_pl011_softc { + struct uart_softc base; + uint8_t fcr; + uint8_t ier; + uint8_t mcr; + + uint8_t ier_mask; + uint8_t ier_rxbits; +}; + +static int uart_pl011_bus_attach(struct uart_softc *); +static int uart_pl011_bus_detach(struct uart_softc *); +static int uart_pl011_bus_flush(struct uart_softc *, int); +static int uart_pl011_bus_getsig(struct uart_softc *); +static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); +static int uart_pl011_bus_ipend(struct uart_softc *); +static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); +static int uart_pl011_bus_probe(struct uart_softc *); +static int uart_pl011_bus_receive(struct uart_softc *); +static int uart_pl011_bus_setsig(struct uart_softc *, int); +static int uart_pl011_bus_transmit(struct uart_softc *); + +static kobj_method_t uart_pl011_methods[] = { + KOBJMETHOD(uart_attach, uart_pl011_bus_attach), + KOBJMETHOD(uart_detach, uart_pl011_bus_detach), + KOBJMETHOD(uart_flush, uart_pl011_bus_flush), + KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), + KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), + KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), + KOBJMETHOD(uart_param, uart_pl011_bus_param), + KOBJMETHOD(uart_probe, uart_pl011_bus_probe), + KOBJMETHOD(uart_receive, uart_pl011_bus_receive), + KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), + KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), + { 0, 0 } +}; + +struct uart_class uart_pl011_class = { + "uart_pl011", + uart_pl011_methods, + sizeof(struct uart_pl011_softc), + .uc_ops = &uart_pl011_ops, + .uc_range = 0x48, + .uc_rclk = 0 +}; + +static int +uart_pl011_bus_attach(struct uart_softc *sc) +{ + struct uart_bas *bas; + + bas = &sc->sc_bas; + /* Enable RX & TX interrupts */ + __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY)); + /* Clear RX & TX interrupts */ + __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); + + sc->sc_rxfifosz = 1; + sc->sc_txfifosz = 1; + + return (0); +} + +static int +uart_pl011_bus_detach(struct uart_softc *sc) +{ + + return (0); +} + +static int +uart_pl011_bus_flush(struct uart_softc *sc, int what) +{ + + return (0); +} + +static int +uart_pl011_bus_getsig(struct uart_softc *sc) +{ + + return (0); +} + +static int +uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) +{ + struct uart_bas *bas; + int error; + + bas = &sc->sc_bas; + error = 0; + uart_lock(sc->sc_hwmtx); + switch (request) { + case UART_IOCTL_BREAK: + break; + case UART_IOCTL_BAUD: + *(int*)data = 115200; + break; + default: + error = EINVAL; + break; + } + uart_unlock(sc->sc_hwmtx); + + return (error); +} + +static int +uart_pl011_bus_ipend(struct uart_softc *sc) +{ + struct uart_bas *bas; + int ipend; + uint32_t ints; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + ints = __uart_getreg(bas, UART_MIS); + ipend = 0; + + if (ints & UART_RXREADY) + ipend |= SER_INT_RXREADY; + if (ints & RIS_BE) + ipend |= SER_INT_BREAK; + if (ints & RIS_OE) + ipend |= SER_INT_OVERRUN; + if (ints & UART_TXEMPTY) { + if (sc->sc_txbusy) + ipend |= SER_INT_TXIDLE; + + __uart_setreg(bas, UART_IMSC, UART_RXREADY); + } + + uart_unlock(sc->sc_hwmtx); + + return (ipend); +} + +static int +uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, + int stopbits, int parity) +{ + + uart_lock(sc->sc_hwmtx); + uart_pl011_init(&sc->sc_bas, baudrate, databits, stopbits, parity); + uart_unlock(sc->sc_hwmtx); + + return (0); +} + +static int +uart_pl011_bus_probe(struct uart_softc *sc) +{ + + device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); + + return (0); +} + +static int +uart_pl011_bus_receive(struct uart_softc *sc) +{ + struct uart_bas *bas; + int rx; + uint32_t ints, xc; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + + ints = __uart_getreg(bas, UART_MIS); + while (ints & UART_RXREADY) { + if (uart_rx_full(sc)) { + sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; + break; + } + xc = __uart_getreg(bas, UART_DR); + rx = xc & 0xff; + + if (xc & DR_FE) + rx |= UART_STAT_FRAMERR; + if (xc & DR_PE) + rx |= UART_STAT_PARERR; + + __uart_setreg(bas, UART_ICR, UART_RXREADY); + + uart_rx_put(sc, rx); + ints = __uart_getreg(bas, UART_MIS); + } + + uart_unlock(sc->sc_hwmtx); + + return (0); +} + +static int +uart_pl011_bus_setsig(struct uart_softc *sc, int sig) +{ + + return (0); +} + +static int +uart_pl011_bus_transmit(struct uart_softc *sc) +{ + struct uart_bas *bas; + int i; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + + for (i = 0; i < sc->sc_txdatasz; i++) { + __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); + uart_barrier(bas); + } + sc->sc_txbusy = 1; + __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY)); + uart_unlock(sc->sc_hwmtx); + + return (0); +} Property changes on: sys/dev/uart/uart_dev_pl011.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/dev/uart/uart.h =================================================================== --- sys/dev/uart/uart.h (revision 239664) +++ sys/dev/uart/uart.h (working copy) @@ -70,6 +70,7 @@ extern struct uart_class uart_sbbc_class __attribute__((weak)); extern struct uart_class uart_z8530_class __attribute__((weak)); extern struct uart_class uart_lpc_class __attribute__((weak)); +extern struct uart_class uart_pl011_class __attribute__((weak)); #ifdef PC98 struct uart_class *uart_pc98_getdev(u_long port); Index: sys/dev/mmc/mmc.c =================================================================== --- sys/dev/mmc/mmc.c (revision 239664) +++ sys/dev/mmc/mmc.c (working copy) @@ -180,8 +180,10 @@ static int mmc_send_status(struct mmc_softc *sc, uint16_t rca, uint32_t *status); static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len); +#ifdef NOT_YET_FOR_RPI static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width); +#endif static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp); static int mmc_set_timing(struct mmc_softc *sc, int timing); static int mmc_switch(struct mmc_softc *sc, uint8_t set, uint8_t index, @@ -301,9 +303,11 @@ (ivar->bus_width == bus_width_4) ? 4 : (ivar->bus_width == bus_width_8) ? 8 : 1); } +#ifdef NOT_YET_FOR_RPI mmc_set_card_bus_width(sc, rca, ivar->bus_width); mmcbr_set_bus_width(busdev, ivar->bus_width); mmcbr_update_ios(busdev); +#endif } } else { /* @@ -653,6 +657,7 @@ return (err); } +#ifdef NOT_YET_FOR_RPI static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width) { @@ -701,6 +706,7 @@ } return (err); } +#endif static int mmc_set_timing(struct mmc_softc *sc, int timing) Index: sys/dev/usb/controller/usb_controller.c =================================================================== --- sys/dev/usb/controller/usb_controller.c (revision 239664) +++ sys/dev/usb/controller/usb_controller.c (working copy) @@ -128,6 +128,7 @@ DRIVER_MODULE(usbus, musbotg, usb_driver, usb_devclass, 0, 0); DRIVER_MODULE(usbus, uss820, usb_driver, usb_devclass, 0, 0); DRIVER_MODULE(usbus, octusb, usb_driver, usb_devclass, 0, 0); +DRIVER_MODULE(usbus, dwcotg, usb_driver, usb_devclass, 0, 0); /*------------------------------------------------------------------------* * usb_probe Index: sys/dev/syscons/syscons.c =================================================================== --- sys/dev/syscons/syscons.c (revision 239664) +++ sys/dev/syscons/syscons.c (working copy) @@ -62,7 +62,7 @@ #include #include -#if defined(__sparc64__) || defined(__powerpc__) +#if defined(__sparc64__) || defined(__powerpc__) || defined(__arm__) #include #else #include Index: sys/dev/syscons/scterm-teken.c =================================================================== --- sys/dev/syscons/scterm-teken.c (revision 239664) +++ sys/dev/syscons/scterm-teken.c (working copy) @@ -40,7 +40,7 @@ #include #include -#if defined(__sparc64__) || defined(__powerpc__) +#if defined(__sparc64__) || defined(__powerpc__) || defined(__arm__) #include #else #include Index: sys/dev/syscons/schistory.c =================================================================== --- sys/dev/syscons/schistory.c (revision 239664) +++ sys/dev/syscons/schistory.c (working copy) @@ -42,7 +42,7 @@ #include #include -#if defined(__sparc64__) || defined(__powerpc__) +#if defined(__sparc64__) || defined(__powerpc__) || defined(__arm__) #include #else #include Index: sys/dev/fdt/fdt_common.c =================================================================== --- sys/dev/fdt/fdt_common.c (revision 239664) +++ sys/dev/fdt/fdt_common.c (working copy) @@ -524,7 +524,8 @@ debugf("no intr-cells defined, defaulting to 1\n"); intr_cells = 1; } - intr_cells = fdt32_to_cpu(intr_cells); + else + intr_cells = fdt32_to_cpu(intr_cells); intr_num = OF_getprop_alloc(node, "interrupts", intr_cells * sizeof(pcell_t), (void **)&intr); Index: sys/dev/sdhci/sdhci.h =================================================================== --- sys/dev/sdhci/sdhci.h (revision 239664) +++ sys/dev/sdhci/sdhci.h (working copy) @@ -25,26 +25,31 @@ * $FreeBSD$ */ -/* - * PCI registers - */ +#define DMA_BLOCK_SIZE 4096 +#define DMA_BOUNDARY 0 /* DMA reload every 4K */ -#define PCI_SDHCI_IFPIO 0x00 -#define PCI_SDHCI_IFDMA 0x01 -#define PCI_SDHCI_IFVENDOR 0x02 +/* Controller doesn't honor resets unless we touch the clock register */ +#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) +/* Controller really supports DMA */ +#define SDHCI_QUIRK_FORCE_DMA (1<<1) +/* Controller has unusable DMA engine */ +#define SDHCI_QUIRK_BROKEN_DMA (1<<2) +/* Controller doesn't like to be reset when there is no card inserted. */ +#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) +/* Controller has flaky internal state so reset it on each ios change */ +#define SDHCI_QUIRK_RESET_ON_IOS (1<<4) +/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ +#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) +/* Controller needs to be reset after each request to stay stable */ +#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) +/* Controller has an off-by-one issue with timeout value */ +#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) +/* Controller has broken read timings */ +#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) +/* Controller needs lowered frequency */ +#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) -#define PCI_SLOT_INFO 0x40 /* 8 bits */ -#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) -#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) -/* - * RICOH specific PCI registers - */ -#define SDHC_PCI_MODE_KEY 0xf9 -#define SDHC_PCI_MODE 0x150 -#define SDHC_PCI_MODE_SD20 0x10 -#define SDHC_PCI_BASE_FREQ_KEY 0xfc -#define SDHC_PCI_BASE_FREQ 0xe1 /* * Controller registers @@ -81,8 +86,6 @@ #define SDHCI_CMD_TYPE_ABORT 0xc0 #define SDHCI_CMD_TYPE_MASK 0xc0 -#define SDHCI_COMMAND 0x0F - #define SDHCI_RESPONSE 0x10 #define SDHCI_BUFFER 0x20 @@ -123,7 +126,11 @@ #define SDHCI_WAKE_UP_CONTROL 0x2B #define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_MASK 0xff +#define SDHCI_DIVIDER_MASK_LEN 8 #define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_MASK 3 +#define SDHCI_DIVIDER_HI_SHIFT 6 #define SDHCI_CLOCK_CARD_EN 0x0004 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 @@ -197,3 +204,57 @@ #define SDHCI_VENDOR_VER_SHIFT 8 #define SDHCI_SPEC_VER_MASK 0x00FF #define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 + + +struct sdhci_slot { + u_int quirks; /* Chip specific quirks */ + device_t bus; /* Bus device */ + device_t dev; /* Slot device */ + u_char num; /* Slot number */ + u_char opt; /* Slot options */ + u_char version; +#define SDHCI_HAVE_DMA 1 + uint32_t max_clk; /* Max possible freq */ + uint32_t timeout_clk; /* Timeout freq */ + struct resource *mem_res; /* Memory resource */ + int mem_rid; + bus_dma_tag_t dmatag; + bus_dmamap_t dmamap; + u_char *dmamem; + bus_addr_t paddr; /* DMA buffer address */ + struct task card_task; /* Card presence check task */ + struct callout card_callout; /* Card insert delay callout */ + struct mmc_host host; /* Host parameters */ + struct mmc_request *req; /* Current request */ + struct mmc_command *curcmd; /* Current command of current request */ + + uint32_t intmask; /* Current interrupt mask */ + uint32_t clock; /* Current clock freq. */ + size_t offset; /* Data buffer offset */ + uint8_t hostctrl; /* Current host control register */ + u_char power; /* Current power */ + u_char bus_busy; /* Bus busy status */ + u_char cmd_done; /* CMD command part done flag */ + u_char data_done; /* DAT command part done flag */ + u_char flags; /* Request execution flags */ +#define CMD_STARTED 1 +#define STOP_STARTED 2 +#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ + struct mtx mtx; /* Slot mutex */ +}; + +int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); +int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value); +int sdhci_init_slot(device_t dev, struct sdhci_slot *slot); +int sdhci_cleanup_slot(struct sdhci_slot *slot); +int sdhci_generic_suspend(struct sdhci_slot *slot); +int sdhci_generic_resume(struct sdhci_slot *slot); +int sdhci_generic_update_ios(device_t brdev, device_t reqdev); +int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req); +int sdhci_generic_get_ro(device_t brdev, device_t reqdev); +int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); +int sdhci_generic_release_host(device_t brdev, device_t reqdev); +void sdhci_generic_intr(struct sdhci_slot *slot); Index: sys/dev/sdhci/sdhci_if.m =================================================================== --- sys/dev/sdhci/sdhci_if.m (revision 0) +++ sys/dev/sdhci/sdhci_if.m (working copy) @@ -0,0 +1,105 @@ +#- +# Copyright (c) 2006 M. Warner Losh +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# Portions of this software may have been developed with reference to +# the SD Simplified Specification. The following disclaimer may apply: +# +# The following conditions apply to the release of the simplified +# specification ("Simplified Specification") by the SD Card Association and +# the SD Group. The Simplified Specification is a subset of the complete SD +# Specification which is owned by the SD Card Association and the SD +# Group. This Simplified Specification is provided on a non-confidential +# basis subject to the disclaimers below. Any implementation of the +# Simplified Specification may require a license from the SD Card +# Association, SD Group, SD-3C LLC or other third parties. +# +# Disclaimers: +# +# The information contained in the Simplified Specification is presented only +# as a standard specification for SD Cards and SD Host/Ancillary products and +# is provided "AS-IS" without any representations or warranties of any +# kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD +# Card Association for any damages, any infringements of patents or other +# right of the SD Group, SD-3C LLC, the SD Card Association or any third +# parties, which may result from its use. No license is granted by +# implication, estoppel or otherwise under any patent or other rights of the +# SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing +# herein shall be construed as an obligation by the SD Group, the SD-3C LLC +# or the SD Card Association to disclose or distribute any technical +# information, know-how or other confidential information to any third party. +# +# $FreeBSD: projects/armv6/sys/dev/mmc/mmcbus_if.m 170002 2007-05-26 05:23:36Z imp $ +# + +# +# This is the set of callbacks that mmc bridges call into the bus, or +# that mmc/sd card drivers call to make requests. +# + +#include +CODE { + struct sdhci_slot; +} + +INTERFACE sdhci; + +METHOD uint8_t read_1 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; +} + +METHOD uint16_t read_2 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; +} + +METHOD uint32_t read_4 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; +} + +METHOD void write_1 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; + uint8_t val; +} + +METHOD void write_2 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; + uint16_t val; +} + +METHOD void write_4 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; + uint32_t val; +} Index: sys/dev/sdhci/sdhci_pci.c =================================================================== --- sys/dev/sdhci/sdhci_pci.c (revision 0) +++ sys/dev/sdhci/sdhci_pci.c (working copy) @@ -0,0 +1,1599 @@ +/*- + * Copyright (c) 2008 Alexander Motin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "mmcbr_if.h" +#include "sdhci.h" + +/* + * PCI registers + */ + +#define PCI_SDHCI_IFPIO 0x00 +#define PCI_SDHCI_IFDMA 0x01 +#define PCI_SDHCI_IFVENDOR 0x02 + +#define PCI_SLOT_INFO 0x40 /* 8 bits */ +#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) +#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) + +/* + * RICOH specific PCI registers + */ +#define SDHC_PCI_MODE_KEY 0xf9 +#define SDHC_PCI_MODE 0x150 +#define SDHC_PCI_MODE_SD20 0x10 +#define SDHC_PCI_BASE_FREQ_KEY 0xfc +#define SDHC_PCI_BASE_FREQ 0xe1 + +static const struct sdhci_device { + uint32_t model; + uint16_t subvendor; + char *desc; + u_int quirks; +} sdhci_devices[] = { + { 0x08221180, 0xffff, "RICOH R5C822 SD", + SDHCI_QUIRK_FORCE_DMA }, + { 0xe8221180, 0xffff, "RICOH SD", + SDHCI_QUIRK_FORCE_DMA }, + { 0xe8231180, 0xffff, "RICOH R5CE823 SD", + SDHCI_QUIRK_LOWER_FREQUENCY }, + { 0x8034104c, 0xffff, "TI XX21/XX11 SD", + SDHCI_QUIRK_FORCE_DMA }, + { 0x05501524, 0xffff, "ENE CB712 SD", + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x05511524, 0xffff, "ENE CB712 SD 2", + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x07501524, 0xffff, "ENE CB714 SD", + SDHCI_QUIRK_RESET_ON_IOS | + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x07511524, 0xffff, "ENE CB714 SD 2", + SDHCI_QUIRK_RESET_ON_IOS | + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x410111ab, 0xffff, "Marvell CaFe SD", + SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, + { 0x2381197B, 0xffff, "JMicron JMB38X SD", + SDHCI_QUIRK_32BIT_DMA_SIZE | + SDHCI_QUIRK_RESET_AFTER_REQUEST }, + { 0, 0xffff, NULL, + 0 } +}; + +struct sdhci_softc; + +struct sdhci_slot { + struct sdhci_softc *sc; + device_t dev; /* Slot device */ + u_char num; /* Slot number */ + u_char opt; /* Slot options */ +#define SDHCI_HAVE_DMA 1 + uint32_t max_clk; /* Max possible freq */ + uint32_t timeout_clk; /* Timeout freq */ + struct resource *mem_res; /* Memory resource */ + int mem_rid; + bus_dma_tag_t dmatag; + bus_dmamap_t dmamap; + u_char *dmamem; + bus_addr_t paddr; /* DMA buffer address */ + struct task card_task; /* Card presence check task */ + struct callout card_callout; /* Card insert delay callout */ + struct mmc_host host; /* Host parameters */ + struct mmc_request *req; /* Current request */ + struct mmc_command *curcmd; /* Current command of current request */ + + uint32_t intmask; /* Current interrupt mask */ + uint32_t clock; /* Current clock freq. */ + size_t offset; /* Data buffer offset */ + uint8_t hostctrl; /* Current host control register */ + u_char power; /* Current power */ + u_char bus_busy; /* Bus busy status */ + u_char cmd_done; /* CMD command part done flag */ + u_char data_done; /* DAT command part done flag */ + u_char flags; /* Request execution flags */ +#define CMD_STARTED 1 +#define STOP_STARTED 2 +#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ + struct mtx mtx; /* Slot mutex */ +}; + +struct sdhci_softc { + device_t dev; /* Controller device */ + u_int quirks; /* Chip specific quirks */ + struct resource *irq_res; /* IRQ resource */ + int irq_rid; + void *intrhand; /* Interrupt handle */ + + int num_slots; /* Number of slots on this controller */ + struct sdhci_slot slots[6]; +}; + +static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); + +int sdhci_debug; +TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); +SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); + +static inline uint8_t +RD1(struct sdhci_slot *slot, bus_size_t off) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + return bus_read_1(slot->mem_res, off); +} + +static inline void +WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + bus_write_1(slot->mem_res, off, val); +} + +static inline uint16_t +RD2(struct sdhci_slot *slot, bus_size_t off) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + return bus_read_2(slot->mem_res, off); +} + +static inline void +WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + bus_write_2(slot->mem_res, off, val); +} + +static inline uint32_t +RD4(struct sdhci_slot *slot, bus_size_t off) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + return bus_read_4(slot->mem_res, off); +} + +static inline void +WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + bus_write_4(slot->mem_res, off, val); +} + +/* bus entry points */ +static int sdhci_probe(device_t dev); +static int sdhci_attach(device_t dev); +static int sdhci_detach(device_t dev); +static void sdhci_intr(void *); + +static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); +static void sdhci_start(struct sdhci_slot *slot); +static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); + +static void sdhci_card_task(void *, int); + +/* helper routines */ +#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) +#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) +#define SDHCI_LOCK_INIT(_slot) \ + mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) +#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); +#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); +#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); + +static int +slot_printf(struct sdhci_slot *slot, const char * fmt, ...) +{ + va_list ap; + int retval; + + retval = printf("%s-slot%d: ", + device_get_nameunit(slot->sc->dev), slot->num); + + va_start(ap, fmt); + retval += vprintf(fmt, ap); + va_end(ap); + return (retval); +} + +static void +sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + if (error != 0) { + printf("getaddr: error %d\n", error); + return; + } + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +static void +sdhci_dumpregs(struct sdhci_slot *slot) +{ + slot_printf(slot, + "============== REGISTER DUMP ==============\n"); + + slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", + RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); + slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", + RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); + slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", + RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); + slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", + RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); + slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", + RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); + slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", + RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); + slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", + RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); + slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", + RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); + slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", + RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); + slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", + RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); + + slot_printf(slot, + "===========================================\n"); +} + +static void +sdhci_reset(struct sdhci_slot *slot, uint8_t mask) +{ + int timeout; + uint8_t res; + + if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { + if (!(RD4(slot, SDHCI_PRESENT_STATE) & + SDHCI_CARD_PRESENT)) + return; + } + + /* Some controllers need this kick or reset won't work. */ + if ((mask & SDHCI_RESET_ALL) == 0 && + (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { + uint32_t clock; + + /* This is to force an update */ + clock = slot->clock; + slot->clock = 0; + sdhci_set_clock(slot, clock); + } + + WR1(slot, SDHCI_SOFTWARE_RESET, mask); + + if (mask & SDHCI_RESET_ALL) { + slot->clock = 0; + slot->power = 0; + } + + /* Wait max 100 ms */ + timeout = 100; + /* Controller clears the bits when it's done */ + while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { + if (timeout == 0) { + slot_printf(slot, + "Reset 0x%x never completed - 0x%x.\n", + (int)mask, (int)res); + sdhci_dumpregs(slot); + return; + } + timeout--; + DELAY(1000); + } +} + +static void +sdhci_init(struct sdhci_slot *slot) +{ + + sdhci_reset(slot, SDHCI_RESET_ALL); + + /* Enable interrupts. */ + slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | + SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | + SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | + SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | + SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | + SDHCI_INT_ACMD12ERR; + WR4(slot, SDHCI_INT_ENABLE, slot->intmask); + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); +} + +static void +sdhci_lower_frequency(device_t dev) +{ + + /* Enable SD2.0 mode. */ + pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); + pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); + pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); + + /* + * Some SD/MMC cards don't work with the default base + * clock frequency of 200MHz. Lower it to 50Hz. + */ + pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); + pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); + pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); +} + +static void +sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) +{ + uint32_t res; + uint16_t clk; + int timeout; + + if (clock == slot->clock) + return; + slot->clock = clock; + + /* Turn off the clock. */ + WR2(slot, SDHCI_CLOCK_CONTROL, 0); + /* If no clock requested - left it so. */ + if (clock == 0) + return; + /* Looking for highest freq <= clock. */ + res = slot->max_clk; + for (clk = 1; clk < 256; clk <<= 1) { + if (res <= clock) + break; + res >>= 1; + } + /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ + clk >>= 1; + /* Now we have got divider, set it. */ + clk <<= SDHCI_DIVIDER_SHIFT; + WR2(slot, SDHCI_CLOCK_CONTROL, clk); + /* Enable clock. */ + clk |= SDHCI_CLOCK_INT_EN; + WR2(slot, SDHCI_CLOCK_CONTROL, clk); + /* Wait up to 10 ms until it stabilize. */ + timeout = 10; + while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + slot_printf(slot, + "Internal clock never stabilised.\n"); + sdhci_dumpregs(slot); + return; + } + timeout--; + DELAY(1000); + } + /* Pass clock signal to the bus. */ + clk |= SDHCI_CLOCK_CARD_EN; + WR2(slot, SDHCI_CLOCK_CONTROL, clk); +} + +static void +sdhci_set_power(struct sdhci_slot *slot, u_char power) +{ + uint8_t pwr; + + if (slot->power == power) + return; + slot->power = power; + + /* Turn off the power. */ + pwr = 0; + WR1(slot, SDHCI_POWER_CONTROL, pwr); + /* If power down requested - left it so. */ + if (power == 0) + return; + /* Set voltage. */ + switch (1 << power) { + case MMC_OCR_LOW_VOLTAGE: + pwr |= SDHCI_POWER_180; + break; + case MMC_OCR_290_300: + case MMC_OCR_300_310: + pwr |= SDHCI_POWER_300; + break; + case MMC_OCR_320_330: + case MMC_OCR_330_340: + pwr |= SDHCI_POWER_330; + break; + } + WR1(slot, SDHCI_POWER_CONTROL, pwr); + /* Turn on the power. */ + pwr |= SDHCI_POWER_ON; + WR1(slot, SDHCI_POWER_CONTROL, pwr); +} + +static void +sdhci_read_block_pio(struct sdhci_slot *slot) +{ + uint32_t data; + char *buffer; + size_t left; + + buffer = slot->curcmd->data->data; + buffer += slot->offset; + /* Transfer one block at a time. */ + left = min(512, slot->curcmd->data->len - slot->offset); + slot->offset += left; + + /* If we are too fast, broken controllers return zeroes. */ + if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) + DELAY(10); + /* Handle unalligned and alligned buffer cases. */ + if ((intptr_t)buffer & 3) { + while (left > 3) { + data = RD4(slot, SDHCI_BUFFER); + buffer[0] = data; + buffer[1] = (data >> 8); + buffer[2] = (data >> 16); + buffer[3] = (data >> 24); + buffer += 4; + left -= 4; + } + } else { + bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + (uint32_t *)buffer, left >> 2); + left &= 3; + } + /* Handle uneven size case. */ + if (left > 0) { + data = RD4(slot, SDHCI_BUFFER); + while (left > 0) { + *(buffer++) = data; + data >>= 8; + left--; + } + } +} + +static void +sdhci_write_block_pio(struct sdhci_slot *slot) +{ + uint32_t data = 0; + char *buffer; + size_t left; + + buffer = slot->curcmd->data->data; + buffer += slot->offset; + /* Transfer one block at a time. */ + left = min(512, slot->curcmd->data->len - slot->offset); + slot->offset += left; + + /* Handle unalligned and alligned buffer cases. */ + if ((intptr_t)buffer & 3) { + while (left > 3) { + data = buffer[0] + + (buffer[1] << 8) + + (buffer[2] << 16) + + (buffer[3] << 24); + left -= 4; + buffer += 4; + WR4(slot, SDHCI_BUFFER, data); + } + } else { + bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + (uint32_t *)buffer, left >> 2); + left &= 3; + } + /* Handle uneven size case. */ + if (left > 0) { + while (left > 0) { + data <<= 8; + data += *(buffer++); + left--; + } + WR4(slot, SDHCI_BUFFER, data); + } +} + +static void +sdhci_transfer_pio(struct sdhci_slot *slot) +{ + + /* Read as many blocks as possible. */ + if (slot->curcmd->data->flags & MMC_DATA_READ) { + while (RD4(slot, SDHCI_PRESENT_STATE) & + SDHCI_DATA_AVAILABLE) { + sdhci_read_block_pio(slot); + if (slot->offset >= slot->curcmd->data->len) + break; + } + } else { + while (RD4(slot, SDHCI_PRESENT_STATE) & + SDHCI_SPACE_AVAILABLE) { + sdhci_write_block_pio(slot); + if (slot->offset >= slot->curcmd->data->len) + break; + } + } +} + +static void +sdhci_card_delay(void *arg) +{ + struct sdhci_slot *slot = arg; + + taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); +} + +static void +sdhci_card_task(void *arg, int pending) +{ + struct sdhci_slot *slot = arg; + + SDHCI_LOCK(slot); + if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { + if (slot->dev == NULL) { + /* If card is present - attach mmc bus. */ + slot->dev = device_add_child(slot->sc->dev, "mmc", -1); + device_set_ivars(slot->dev, slot); + SDHCI_UNLOCK(slot); + device_probe_and_attach(slot->dev); + } else + SDHCI_UNLOCK(slot); + } else { + if (slot->dev != NULL) { + /* If no card present - detach mmc bus. */ + device_t d = slot->dev; + slot->dev = NULL; + SDHCI_UNLOCK(slot); + device_delete_child(slot->sc->dev, d); + } else + SDHCI_UNLOCK(slot); + } +} + +static int +sdhci_probe(device_t dev) +{ + uint32_t model; + uint16_t subvendor; + uint8_t class, subclass; + int i, result; + + model = (uint32_t)pci_get_device(dev) << 16; + model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; + subvendor = pci_get_subvendor(dev); + class = pci_get_class(dev); + subclass = pci_get_subclass(dev); + + result = ENXIO; + for (i = 0; sdhci_devices[i].model != 0; i++) { + if (sdhci_devices[i].model == model && + (sdhci_devices[i].subvendor == 0xffff || + sdhci_devices[i].subvendor == subvendor)) { + device_set_desc(dev, sdhci_devices[i].desc); + result = BUS_PROBE_DEFAULT; + break; + } + } + if (result == ENXIO && class == PCIC_BASEPERIPH && + subclass == PCIS_BASEPERIPH_SDHC) { + device_set_desc(dev, "Generic SD HCI"); + result = BUS_PROBE_GENERIC; + } + + return (result); +} + +static int +sdhci_attach(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + uint32_t model; + uint16_t subvendor; + uint8_t class, subclass, progif; + int err, slots, bar, i; + + sc->dev = dev; + model = (uint32_t)pci_get_device(dev) << 16; + model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; + subvendor = pci_get_subvendor(dev); + class = pci_get_class(dev); + subclass = pci_get_subclass(dev); + progif = pci_get_progif(dev); + /* Apply chip specific quirks. */ + for (i = 0; sdhci_devices[i].model != 0; i++) { + if (sdhci_devices[i].model == model && + (sdhci_devices[i].subvendor == 0xffff || + sdhci_devices[i].subvendor == subvendor)) { + sc->quirks = sdhci_devices[i].quirks; + break; + } + } + /* Some controllers need to be bumped into the right mode. */ + if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) + sdhci_lower_frequency(dev); + /* Read slots info from PCI registers. */ + slots = pci_read_config(dev, PCI_SLOT_INFO, 1); + bar = PCI_SLOT_INFO_FIRST_BAR(slots); + slots = PCI_SLOT_INFO_SLOTS(slots); + if (slots > 6 || bar > 5) { + device_printf(dev, "Incorrect slots information (%d, %d).\n", + slots, bar); + return (EINVAL); + } + /* Allocate IRQ. */ + sc->irq_rid = 0; + sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->irq_res == NULL) { + device_printf(dev, "Can't allocate IRQ\n"); + return (ENOMEM); + } + /* Scan all slots. */ + for (i = 0; i < slots; i++) { + struct sdhci_slot *slot = &sc->slots[sc->num_slots]; + uint32_t caps; + + SDHCI_LOCK_INIT(slot); + slot->sc = sc; + slot->num = sc->num_slots; + /* Allocate memory. */ + slot->mem_rid = PCIR_BAR(bar + i); + slot->mem_res = bus_alloc_resource(dev, + SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); + if (slot->mem_res == NULL) { + device_printf(dev, "Can't allocate memory\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Allocate DMA tag. */ + err = bus_dma_tag_create(bus_get_dma_tag(dev), + DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, + DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, + BUS_DMA_ALLOCNOW, NULL, NULL, + &slot->dmatag); + if (err != 0) { + device_printf(dev, "Can't create DMA tag\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Allocate DMA memory. */ + err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, + BUS_DMA_NOWAIT, &slot->dmamap); + if (err != 0) { + device_printf(dev, "Can't alloc DMA memory\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Map the memory. */ + err = bus_dmamap_load(slot->dmatag, slot->dmamap, + (void *)slot->dmamem, DMA_BLOCK_SIZE, + sdhci_getaddr, &slot->paddr, 0); + if (err != 0 || slot->paddr == 0) { + device_printf(dev, "Can't load DMA memory\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Initialize slot. */ + sdhci_init(slot); + caps = RD4(slot, SDHCI_CAPABILITIES); + /* Calculate base clock frequency. */ + slot->max_clk = + (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; + if (slot->max_clk == 0) { + device_printf(dev, "Hardware doesn't specify base clock " + "frequency.\n"); + } + slot->max_clk *= 1000000; + /* Calculate timeout clock frequency. */ + slot->timeout_clk = + (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; + if (slot->timeout_clk == 0) { + device_printf(dev, "Hardware doesn't specify timeout clock " + "frequency.\n"); + } + if (caps & SDHCI_TIMEOUT_CLK_UNIT) + slot->timeout_clk *= 1000; + + slot->host.f_min = slot->max_clk / 256; + slot->host.f_max = slot->max_clk; + slot->host.host_ocr = 0; + if (caps & SDHCI_CAN_VDD_330) + slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; + if (caps & SDHCI_CAN_VDD_300) + slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; + if (caps & SDHCI_CAN_VDD_180) + slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; + if (slot->host.host_ocr == 0) { + device_printf(dev, "Hardware doesn't report any " + "support voltages.\n"); + } + slot->host.caps = MMC_CAP_4_BIT_DATA; + if (caps & SDHCI_CAN_DO_HISPD) + slot->host.caps |= MMC_CAP_HSPEED; + /* Decide if we have usable DMA. */ + if (caps & SDHCI_CAN_DO_DMA) + slot->opt |= SDHCI_HAVE_DMA; + if (class == PCIC_BASEPERIPH && + subclass == PCIS_BASEPERIPH_SDHC && + progif != PCI_SDHCI_IFDMA) + slot->opt &= ~SDHCI_HAVE_DMA; + if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) + slot->opt &= ~SDHCI_HAVE_DMA; + if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) + slot->opt |= SDHCI_HAVE_DMA; + + if (bootverbose || sdhci_debug) { + slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", + slot->max_clk / 1000000, + (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", + (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", + (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", + (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", + (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); + sdhci_dumpregs(slot); + } + + TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); + callout_init(&slot->card_callout, 1); + sc->num_slots++; + } + device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); + /* Activate the interrupt */ + err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, sdhci_intr, sc, &sc->intrhand); + if (err) + device_printf(dev, "Can't setup IRQ\n"); + pci_enable_busmaster(dev); + /* Process cards detection. */ + for (i = 0; i < sc->num_slots; i++) { + struct sdhci_slot *slot = &sc->slots[i]; + + sdhci_card_task(slot, 0); + } + + return (0); +} + +static int +sdhci_detach(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + int i; + + bus_teardown_intr(dev, sc->irq_res, sc->intrhand); + bus_release_resource(dev, SYS_RES_IRQ, + sc->irq_rid, sc->irq_res); + + for (i = 0; i < sc->num_slots; i++) { + struct sdhci_slot *slot = &sc->slots[i]; + device_t d; + + callout_drain(&slot->card_callout); + taskqueue_drain(taskqueue_swi_giant, &slot->card_task); + + SDHCI_LOCK(slot); + d = slot->dev; + slot->dev = NULL; + SDHCI_UNLOCK(slot); + if (d != NULL) + device_delete_child(dev, d); + + SDHCI_LOCK(slot); + sdhci_reset(slot, SDHCI_RESET_ALL); + SDHCI_UNLOCK(slot); + bus_dmamap_unload(slot->dmatag, slot->dmamap); + bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); + bus_dma_tag_destroy(slot->dmatag); + bus_release_resource(dev, SYS_RES_MEMORY, + slot->mem_rid, slot->mem_res); + SDHCI_LOCK_DESTROY(slot); + } + return (0); +} + +static int +sdhci_suspend(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + int i, err; + + err = bus_generic_suspend(dev); + if (err) + return (err); + for (i = 0; i < sc->num_slots; i++) + sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); + return (0); +} + +static int +sdhci_resume(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + int i; + + for (i = 0; i < sc->num_slots; i++) + sdhci_init(&sc->slots[i]); + return (bus_generic_resume(dev)); +} + +static int +sdhci_update_ios(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + struct mmc_ios *ios = &slot->host.ios; + + SDHCI_LOCK(slot); + /* Do full reset on bus power down to clear from any state. */ + if (ios->power_mode == power_off) { + WR4(slot, SDHCI_SIGNAL_ENABLE, 0); + sdhci_init(slot); + } + /* Configure the bus. */ + sdhci_set_clock(slot, ios->clock); + sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); + if (ios->bus_width == bus_width_4) + slot->hostctrl |= SDHCI_CTRL_4BITBUS; + else + slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; + if (ios->timing == bus_timing_hs) + slot->hostctrl |= SDHCI_CTRL_HISPD; + else + slot->hostctrl &= ~SDHCI_CTRL_HISPD; + WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); + /* Some controllers like reset after bus changes. */ + if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) + sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + + SDHCI_UNLOCK(slot); + return (0); +} + +static void +sdhci_set_transfer_mode(struct sdhci_slot *slot, + struct mmc_data *data) +{ + uint16_t mode; + + if (data == NULL) + return; + + mode = SDHCI_TRNS_BLK_CNT_EN; + if (data->len > 512) + mode |= SDHCI_TRNS_MULTI; + if (data->flags & MMC_DATA_READ) + mode |= SDHCI_TRNS_READ; + if (slot->req->stop) + mode |= SDHCI_TRNS_ACMD12; + if (slot->flags & SDHCI_USE_DMA) + mode |= SDHCI_TRNS_DMA; + + WR2(slot, SDHCI_TRANSFER_MODE, mode); +} + +static void +sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) +{ + struct mmc_request *req = slot->req; + int flags, timeout; + uint32_t mask, state; + + slot->curcmd = cmd; + slot->cmd_done = 0; + + cmd->error = MMC_ERR_NONE; + + /* This flags combination is not supported by controller. */ + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + slot_printf(slot, "Unsupported response type!\n"); + cmd->error = MMC_ERR_FAILED; + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); + return; + } + + /* Read controller present state. */ + state = RD4(slot, SDHCI_PRESENT_STATE); + /* Do not issue command if there is no card, clock or power. + * Controller will not detect timeout without clock active. */ + if ((state & SDHCI_CARD_PRESENT) == 0 || + slot->power == 0 || + slot->clock == 0) { + cmd->error = MMC_ERR_FAILED; + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); + return; + } + /* Always wait for free CMD bus. */ + mask = SDHCI_CMD_INHIBIT; + /* Wait for free DAT if we have data or busy signal. */ + if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) + mask |= SDHCI_DAT_INHIBIT; + /* We shouldn't wait for DAT for stop commands. */ + if (cmd == slot->req->stop) + mask &= ~SDHCI_DAT_INHIBIT; + /* Wait for bus no more then 10 ms. */ + timeout = 10; + while (state & mask) { + if (timeout == 0) { + slot_printf(slot, "Controller never released " + "inhibit bit(s).\n"); + sdhci_dumpregs(slot); + cmd->error = MMC_ERR_FAILED; + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); + return; + } + timeout--; + DELAY(1000); + state = RD4(slot, SDHCI_PRESENT_STATE); + } + + /* Prepare command flags. */ + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = SDHCI_CMD_RESP_SHORT; + if (cmd->flags & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + if (cmd->data) + flags |= SDHCI_CMD_DATA; + if (cmd->opcode == MMC_STOP_TRANSMISSION) + flags |= SDHCI_CMD_TYPE_ABORT; + /* Prepare data. */ + sdhci_start_data(slot, cmd->data); + /* + * Interrupt aggregation: To reduce total number of interrupts + * group response interrupt with data interrupt when possible. + * If there going to be data interrupt, mask response one. + */ + if (slot->data_done == 0) { + WR4(slot, SDHCI_SIGNAL_ENABLE, + slot->intmask &= ~SDHCI_INT_RESPONSE); + } + /* Set command argument. */ + WR4(slot, SDHCI_ARGUMENT, cmd->arg); + /* Set data transfer mode. */ + sdhci_set_transfer_mode(slot, cmd->data); + /* Set command flags. */ + WR1(slot, SDHCI_COMMAND_FLAGS, flags); + /* Start command. */ + WR1(slot, SDHCI_COMMAND, cmd->opcode); +} + +static void +sdhci_finish_command(struct sdhci_slot *slot) +{ + int i; + + slot->cmd_done = 1; + /* Interrupt aggregation: Restore command interrupt. + * Main restore point for the case when command interrupt + * happened first. */ + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); + /* In case of error - reset host and return. */ + if (slot->curcmd->error) { + sdhci_reset(slot, SDHCI_RESET_CMD); + sdhci_reset(slot, SDHCI_RESET_DATA); + sdhci_start(slot); + return; + } + /* If command has response - fetch it. */ + if (slot->curcmd->flags & MMC_RSP_PRESENT) { + if (slot->curcmd->flags & MMC_RSP_136) { + /* CRC is stripped so we need one byte shift. */ + uint8_t extra = 0; + for (i = 0; i < 4; i++) { + uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); + slot->curcmd->resp[3 - i] = (val << 8) + extra; + extra = val >> 24; + } + } else + slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); + } + /* If data ready - finish. */ + if (slot->data_done) + sdhci_start(slot); +} + +static void +sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) +{ + uint32_t target_timeout, current_timeout; + uint8_t div; + + if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { + slot->data_done = 1; + return; + } + + slot->data_done = 0; + + /* Calculate and set data timeout.*/ + /* XXX: We should have this from mmc layer, now assume 1 sec. */ + target_timeout = 1000000; + div = 0; + current_timeout = (1 << 13) * 1000 / slot->timeout_clk; + while (current_timeout < target_timeout) { + div++; + current_timeout <<= 1; + if (div >= 0xF) + break; + } + /* Compensate for an off-by-one error in the CaFe chip.*/ + if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) + div++; + if (div >= 0xF) { + slot_printf(slot, "Timeout too large!\n"); + div = 0xE; + } + WR1(slot, SDHCI_TIMEOUT_CONTROL, div); + + if (data == NULL) + return; + + /* Use DMA if possible. */ + if ((slot->opt & SDHCI_HAVE_DMA)) + slot->flags |= SDHCI_USE_DMA; + /* If data is small, broken DMA may return zeroes instead of data, */ + if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && + (data->len <= 512)) + slot->flags &= ~SDHCI_USE_DMA; + /* Some controllers require even block sizes. */ + if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && + ((data->len) & 0x3)) + slot->flags &= ~SDHCI_USE_DMA; + /* Load DMA buffer. */ + if (slot->flags & SDHCI_USE_DMA) { + if (data->flags & MMC_DATA_READ) + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); + else { + memcpy(slot->dmamem, data->data, + (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); + } + WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); + /* Interrupt aggregation: Mask border interrupt + * for the last page and unmask else. */ + if (data->len == DMA_BLOCK_SIZE) + slot->intmask &= ~SDHCI_INT_DMA_END; + else + slot->intmask |= SDHCI_INT_DMA_END; + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); + } + /* Current data offset for both PIO and DMA. */ + slot->offset = 0; + /* Set block size and request IRQ on 4K border. */ + WR2(slot, SDHCI_BLOCK_SIZE, + SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); + /* Set block count. */ + WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); +} + +static void +sdhci_finish_data(struct sdhci_slot *slot) +{ + struct mmc_data *data = slot->curcmd->data; + + slot->data_done = 1; + /* Interrupt aggregation: Restore command interrupt. + * Auxillary restore point for the case when data interrupt + * happened first. */ + if (!slot->cmd_done) { + WR4(slot, SDHCI_SIGNAL_ENABLE, + slot->intmask |= SDHCI_INT_RESPONSE); + } + /* Unload rest of data from DMA buffer. */ + if (slot->flags & SDHCI_USE_DMA) { + if (data->flags & MMC_DATA_READ) { + size_t left = data->len - slot->offset; + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); + memcpy((u_char*)data->data + slot->offset, slot->dmamem, + (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); + } else + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); + } + /* If there was error - reset the host. */ + if (slot->curcmd->error) { + sdhci_reset(slot, SDHCI_RESET_CMD); + sdhci_reset(slot, SDHCI_RESET_DATA); + sdhci_start(slot); + return; + } + /* If we already have command response - finish. */ + if (slot->cmd_done) + sdhci_start(slot); +} + +static void +sdhci_start(struct sdhci_slot *slot) +{ + struct mmc_request *req; + + req = slot->req; + if (req == NULL) + return; + + if (!(slot->flags & CMD_STARTED)) { + slot->flags |= CMD_STARTED; + sdhci_start_command(slot, req->cmd); + return; + } +/* We don't need this until using Auto-CMD12 feature + if (!(slot->flags & STOP_STARTED) && req->stop) { + slot->flags |= STOP_STARTED; + sdhci_start_command(slot, req->stop); + return; + } +*/ + if (sdhci_debug > 1) + slot_printf(slot, "result: %d\n", req->cmd->error); + if (!req->cmd->error && + (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { + sdhci_reset(slot, SDHCI_RESET_CMD); + sdhci_reset(slot, SDHCI_RESET_DATA); + } + + /* We must be done -- bad idea to do this while locked? */ + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); +} + +static int +sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + + SDHCI_LOCK(slot); + if (slot->req != NULL) { + SDHCI_UNLOCK(slot); + return (EBUSY); + } + if (sdhci_debug > 1) { + slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", + req->cmd->opcode, req->cmd->arg, req->cmd->flags, + (req->cmd->data)?(u_int)req->cmd->data->len:0, + (req->cmd->data)?req->cmd->data->flags:0); + } + slot->req = req; + slot->flags = 0; + sdhci_start(slot); + SDHCI_UNLOCK(slot); + if (dumping) { + while (slot->req != NULL) { + sdhci_intr(slot->sc); + DELAY(10); + } + } + return (0); +} + +static int +sdhci_get_ro(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + uint32_t val; + + SDHCI_LOCK(slot); + val = RD4(slot, SDHCI_PRESENT_STATE); + SDHCI_UNLOCK(slot); + return (!(val & SDHCI_WRITE_PROTECT)); +} + +static int +sdhci_acquire_host(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + int err = 0; + + SDHCI_LOCK(slot); + while (slot->bus_busy) + msleep(slot, &slot->mtx, 0, "sdhciah", 0); + slot->bus_busy++; + /* Activate led. */ + WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); + SDHCI_UNLOCK(slot); + return (err); +} + +static int +sdhci_release_host(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + + SDHCI_LOCK(slot); + /* Deactivate led. */ + WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); + slot->bus_busy--; + SDHCI_UNLOCK(slot); + wakeup(slot); + return (0); +} + +static void +sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) +{ + + if (!slot->curcmd) { + slot_printf(slot, "Got command interrupt 0x%08x, but " + "there is no active command.\n", intmask); + sdhci_dumpregs(slot); + return; + } + if (intmask & SDHCI_INT_TIMEOUT) + slot->curcmd->error = MMC_ERR_TIMEOUT; + else if (intmask & SDHCI_INT_CRC) + slot->curcmd->error = MMC_ERR_BADCRC; + else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) + slot->curcmd->error = MMC_ERR_FIFO; + + sdhci_finish_command(slot); +} + +static void +sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) +{ + + if (!slot->curcmd) { + slot_printf(slot, "Got data interrupt 0x%08x, but " + "there is no active command.\n", intmask); + sdhci_dumpregs(slot); + return; + } + if (slot->curcmd->data == NULL && + (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { + slot_printf(slot, "Got data interrupt 0x%08x, but " + "there is no active data operation.\n", + intmask); + sdhci_dumpregs(slot); + return; + } + if (intmask & SDHCI_INT_DATA_TIMEOUT) + slot->curcmd->error = MMC_ERR_TIMEOUT; + else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) + slot->curcmd->error = MMC_ERR_BADCRC; + if (slot->curcmd->data == NULL && + (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | + SDHCI_INT_DMA_END))) { + slot_printf(slot, "Got data interrupt 0x%08x, but " + "there is busy-only command.\n", intmask); + sdhci_dumpregs(slot); + slot->curcmd->error = MMC_ERR_INVALID; + } + if (slot->curcmd->error) { + /* No need to continue after any error. */ + sdhci_finish_data(slot); + return; + } + + /* Handle PIO interrupt. */ + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) + sdhci_transfer_pio(slot); + /* Handle DMA border. */ + if (intmask & SDHCI_INT_DMA_END) { + struct mmc_data *data = slot->curcmd->data; + size_t left; + + /* Unload DMA buffer... */ + left = data->len - slot->offset; + if (data->flags & MMC_DATA_READ) { + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_POSTREAD); + memcpy((u_char*)data->data + slot->offset, slot->dmamem, + (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); + } else { + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_POSTWRITE); + } + /* ... and reload it again. */ + slot->offset += DMA_BLOCK_SIZE; + left = data->len - slot->offset; + if (data->flags & MMC_DATA_READ) { + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_PREREAD); + } else { + memcpy(slot->dmamem, (u_char*)data->data + slot->offset, + (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_PREWRITE); + } + /* Interrupt aggregation: Mask border interrupt + * for the last page. */ + if (left == DMA_BLOCK_SIZE) { + slot->intmask &= ~SDHCI_INT_DMA_END; + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); + } + /* Restart DMA. */ + WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); + } + /* We have got all data. */ + if (intmask & SDHCI_INT_DATA_END) + sdhci_finish_data(slot); +} + +static void +sdhci_acmd_irq(struct sdhci_slot *slot) +{ + uint16_t err; + + err = RD4(slot, SDHCI_ACMD12_ERR); + if (!slot->curcmd) { + slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " + "there is no active command.\n", err); + sdhci_dumpregs(slot); + return; + } + slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); + sdhci_reset(slot, SDHCI_RESET_CMD); +} + +static void +sdhci_intr(void *arg) +{ + struct sdhci_softc *sc = (struct sdhci_softc *)arg; + int i; + + for (i = 0; i < sc->num_slots; i++) { + struct sdhci_slot *slot = &sc->slots[i]; + uint32_t intmask; + + SDHCI_LOCK(slot); + /* Read slot interrupt status. */ + intmask = RD4(slot, SDHCI_INT_STATUS); + if (intmask == 0 || intmask == 0xffffffff) { + SDHCI_UNLOCK(slot); + continue; + } + if (sdhci_debug > 2) + slot_printf(slot, "Interrupt %#x\n", intmask); + + /* Handle card presence interrupts. */ + if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + WR4(slot, SDHCI_INT_STATUS, intmask & + (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); + + if (intmask & SDHCI_INT_CARD_REMOVE) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card removed\n"); + callout_stop(&slot->card_callout); + taskqueue_enqueue(taskqueue_swi_giant, + &slot->card_task); + } + if (intmask & SDHCI_INT_CARD_INSERT) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card inserted\n"); + callout_reset(&slot->card_callout, hz / 2, + sdhci_card_delay, slot); + } + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); + } + /* Handle command interrupts. */ + if (intmask & SDHCI_INT_CMD_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); + sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); + } + /* Handle data interrupts. */ + if (intmask & SDHCI_INT_DATA_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); + sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); + } + /* Handle AutoCMD12 error interrupt. */ + if (intmask & SDHCI_INT_ACMD12ERR) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); + sdhci_acmd_irq(slot); + } + intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); + intmask &= ~SDHCI_INT_ACMD12ERR; + intmask &= ~SDHCI_INT_ERROR; + /* Handle bus power interrupt. */ + if (intmask & SDHCI_INT_BUS_POWER) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); + slot_printf(slot, + "Card is consuming too much power!\n"); + intmask &= ~SDHCI_INT_BUS_POWER; + } + /* The rest is unknown. */ + if (intmask) { + WR4(slot, SDHCI_INT_STATUS, intmask); + slot_printf(slot, "Unexpected interrupt 0x%08x.\n", + intmask); + sdhci_dumpregs(slot); + } + + SDHCI_UNLOCK(slot); + } +} + +static int +sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) +{ + struct sdhci_slot *slot = device_get_ivars(child); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + *result = slot->host.ios.bus_mode; + break; + case MMCBR_IVAR_BUS_WIDTH: + *result = slot->host.ios.bus_width; + break; + case MMCBR_IVAR_CHIP_SELECT: + *result = slot->host.ios.chip_select; + break; + case MMCBR_IVAR_CLOCK: + *result = slot->host.ios.clock; + break; + case MMCBR_IVAR_F_MIN: + *result = slot->host.f_min; + break; + case MMCBR_IVAR_F_MAX: + *result = slot->host.f_max; + break; + case MMCBR_IVAR_HOST_OCR: + *result = slot->host.host_ocr; + break; + case MMCBR_IVAR_MODE: + *result = slot->host.mode; + break; + case MMCBR_IVAR_OCR: + *result = slot->host.ocr; + break; + case MMCBR_IVAR_POWER_MODE: + *result = slot->host.ios.power_mode; + break; + case MMCBR_IVAR_VDD: + *result = slot->host.ios.vdd; + break; + case MMCBR_IVAR_CAPS: + *result = slot->host.caps; + break; + case MMCBR_IVAR_TIMING: + *result = slot->host.ios.timing; + break; + case MMCBR_IVAR_MAX_DATA: + *result = 65535; + break; + } + return (0); +} + +static int +sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) +{ + struct sdhci_slot *slot = device_get_ivars(child); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + slot->host.ios.bus_mode = value; + break; + case MMCBR_IVAR_BUS_WIDTH: + slot->host.ios.bus_width = value; + break; + case MMCBR_IVAR_CHIP_SELECT: + slot->host.ios.chip_select = value; + break; + case MMCBR_IVAR_CLOCK: + if (value > 0) { + uint32_t clock = slot->max_clk; + int i; + + for (i = 0; i < 8; i++) { + if (clock <= value) + break; + clock >>= 1; + } + slot->host.ios.clock = clock; + } else + slot->host.ios.clock = 0; + break; + case MMCBR_IVAR_MODE: + slot->host.mode = value; + break; + case MMCBR_IVAR_OCR: + slot->host.ocr = value; + break; + case MMCBR_IVAR_POWER_MODE: + slot->host.ios.power_mode = value; + break; + case MMCBR_IVAR_VDD: + slot->host.ios.vdd = value; + break; + case MMCBR_IVAR_TIMING: + slot->host.ios.timing = value; + break; + case MMCBR_IVAR_CAPS: + case MMCBR_IVAR_HOST_OCR: + case MMCBR_IVAR_F_MIN: + case MMCBR_IVAR_F_MAX: + case MMCBR_IVAR_MAX_DATA: + return (EINVAL); + } + return (0); +} + +static device_method_t sdhci_methods[] = { + /* device_if */ + DEVMETHOD(device_probe, sdhci_probe), + DEVMETHOD(device_attach, sdhci_attach), + DEVMETHOD(device_detach, sdhci_detach), + DEVMETHOD(device_suspend, sdhci_suspend), + DEVMETHOD(device_resume, sdhci_resume), + + /* Bus interface */ + DEVMETHOD(bus_read_ivar, sdhci_read_ivar), + DEVMETHOD(bus_write_ivar, sdhci_write_ivar), + + /* mmcbr_if */ + DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), + DEVMETHOD(mmcbr_request, sdhci_request), + DEVMETHOD(mmcbr_get_ro, sdhci_get_ro), + DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host), + DEVMETHOD(mmcbr_release_host, sdhci_release_host), + + {0, 0}, +}; + +static driver_t sdhci_driver = { + "sdhci", + sdhci_methods, + sizeof(struct sdhci_softc), +}; +static devclass_t sdhci_devclass; + + +DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); Property changes on: sys/dev/sdhci/sdhci_pci.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Added: svn:eol-style ## -0,0 +1 ## +native Index: sys/dev/sdhci/sdhci.c =================================================================== --- sys/dev/sdhci/sdhci.c (revision 239664) +++ sys/dev/sdhci/sdhci.c (working copy) @@ -39,9 +39,6 @@ #include #include -#include -#include - #include #include #include @@ -52,6 +49,7 @@ #include "mmcbr_if.h" #include "sdhci.h" +#include "sdhci_if.h" #define DMA_BLOCK_SIZE 4096 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ @@ -77,79 +75,10 @@ /* Controller needs lowered frequency */ #define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) -static const struct sdhci_device { - uint32_t model; - uint16_t subvendor; - char *desc; - u_int quirks; -} sdhci_devices[] = { - { 0x08221180, 0xffff, "RICOH R5C822 SD", - SDHCI_QUIRK_FORCE_DMA }, - { 0xe8221180, 0xffff, "RICOH SD", - SDHCI_QUIRK_FORCE_DMA }, - { 0xe8231180, 0xffff, "RICOH R5CE823 SD", - SDHCI_QUIRK_LOWER_FREQUENCY }, - { 0x8034104c, 0xffff, "TI XX21/XX11 SD", - SDHCI_QUIRK_FORCE_DMA }, - { 0x05501524, 0xffff, "ENE CB712 SD", - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x05511524, 0xffff, "ENE CB712 SD 2", - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x07501524, 0xffff, "ENE CB714 SD", - SDHCI_QUIRK_RESET_ON_IOS | - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x07511524, 0xffff, "ENE CB714 SD 2", - SDHCI_QUIRK_RESET_ON_IOS | - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x410111ab, 0xffff, "Marvell CaFe SD", - SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, - { 0x2381197B, 0xffff, "JMicron JMB38X SD", - SDHCI_QUIRK_32BIT_DMA_SIZE | - SDHCI_QUIRK_RESET_AFTER_REQUEST }, - { 0, 0xffff, NULL, - 0 } -}; - struct sdhci_softc; -struct sdhci_slot { - struct sdhci_softc *sc; - device_t dev; /* Slot device */ - u_char num; /* Slot number */ - u_char opt; /* Slot options */ -#define SDHCI_HAVE_DMA 1 - uint32_t max_clk; /* Max possible freq */ - uint32_t timeout_clk; /* Timeout freq */ - struct resource *mem_res; /* Memory resource */ - int mem_rid; - bus_dma_tag_t dmatag; - bus_dmamap_t dmamap; - u_char *dmamem; - bus_addr_t paddr; /* DMA buffer address */ - struct task card_task; /* Card presence check task */ - struct callout card_callout; /* Card insert delay callout */ - struct mmc_host host; /* Host parameters */ - struct mmc_request *req; /* Current request */ - struct mmc_command *curcmd; /* Current command of current request */ - - uint32_t intmask; /* Current interrupt mask */ - uint32_t clock; /* Current clock freq. */ - size_t offset; /* Data buffer offset */ - uint8_t hostctrl; /* Current host control register */ - u_char power; /* Current power */ - u_char bus_busy; /* Bus busy status */ - u_char cmd_done; /* CMD command part done flag */ - u_char data_done; /* DAT command part done flag */ - u_char flags; /* Request execution flags */ -#define CMD_STARTED 1 -#define STOP_STARTED 2 -#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ - struct mtx mtx; /* Slot mutex */ -}; - struct sdhci_softc { device_t dev; /* Controller device */ - u_int quirks; /* Chip specific quirks */ struct resource *irq_res; /* IRQ resource */ int irq_rid; void *intrhand; /* Interrupt handle */ @@ -160,64 +89,18 @@ static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); -int sdhci_debug; +int sdhci_debug = 0; TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); -static inline uint8_t -RD1(struct sdhci_slot *slot, bus_size_t off) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - return bus_read_1(slot->mem_res, off); -} +#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) +#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) +#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) -static inline void -WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - bus_write_1(slot->mem_res, off, val); -} +#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) +#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) +#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) -static inline uint16_t -RD2(struct sdhci_slot *slot, bus_size_t off) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - return bus_read_2(slot->mem_res, off); -} - -static inline void -WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - bus_write_2(slot->mem_res, off, val); -} - -static inline uint32_t -RD4(struct sdhci_slot *slot, bus_size_t off) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - return bus_read_4(slot->mem_res, off); -} - -static inline void -WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - bus_write_4(slot->mem_res, off, val); -} - -/* bus entry points */ -static int sdhci_probe(device_t dev); -static int sdhci_attach(device_t dev); -static int sdhci_detach(device_t dev); -static void sdhci_intr(void *); - static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); static void sdhci_start(struct sdhci_slot *slot); static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); @@ -240,7 +123,7 @@ int retval; retval = printf("%s-slot%d: ", - device_get_nameunit(slot->sc->dev), slot->num); + device_get_nameunit(slot->bus), slot->num); va_start(ap, fmt); retval += vprintf(fmt, ap); @@ -249,16 +132,6 @@ } static void -sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) -{ - if (error != 0) { - printf("getaddr: error %d\n", error); - return; - } - *(bus_addr_t *)arg = segs[0].ds_addr; -} - -static void sdhci_dumpregs(struct sdhci_slot *slot) { slot_printf(slot, @@ -295,7 +168,7 @@ int timeout; uint8_t res; - if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { + if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { if (!(RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) return; @@ -303,7 +176,7 @@ /* Some controllers need this kick or reset won't work. */ if ((mask & SDHCI_RESET_ALL) == 0 && - (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { + (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { uint32_t clock; /* This is to force an update */ @@ -354,28 +227,11 @@ } static void -sdhci_lower_frequency(device_t dev) -{ - - /* Enable SD2.0 mode. */ - pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); - pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); - pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); - - /* - * Some SD/MMC cards don't work with the default base - * clock frequency of 200MHz. Lower it to 50MHz. - */ - pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); - pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); - pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); -} - -static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) { uint32_t res; - uint16_t clk; + uint16_t clk = 0; + uint16_t div; int timeout; if (clock == slot->clock) @@ -387,18 +243,44 @@ /* If no clock requested - left it so. */ if (clock == 0) return; - /* Looking for highest freq <= clock. */ - res = slot->max_clk; - for (clk = 1; clk < 256; clk <<= 1) { - if (res <= clock) - break; - res >>= 1; + if (slot->version < SDHCI_SPEC_300) { + /* Looking for highest freq <= clock. */ + res = slot->max_clk; + for (div = 1; div < 256; div <<= 1) { + if (res <= clock) + break; + res >>= 1; + } + /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ + div >>= 1; + /* Now we have got divider, set it. */ + div <<= SDHCI_DIVIDER_SHIFT; + WR2(slot, SDHCI_CLOCK_CONTROL, div); } - /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ - clk >>= 1; - /* Now we have got divider, set it. */ - clk <<= SDHCI_DIVIDER_SHIFT; + else { + /* Version 3.0 divisors are multiple of two up to 1023*12 */ + if (clock > slot->max_clk) + div = 1; + else { + for (div = 2; div < 1023*2; div += 2) { + if ((slot->max_clk / div) <= clock) + break; + } + div /= 2; + } + div >>= 1; + } + + if (sdhci_debug) + slot_printf(slot, "Divider %d for freq %d (max %d)\n", + div, clock, slot->max_clk); + + /* Now we have got clkider, set it. */ + clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; + clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) + << SDHCI_DIVIDER_HI_SHIFT; WR2(slot, SDHCI_CLOCK_CONTROL, clk); + /* Enable clock. */ clk |= SDHCI_CLOCK_INT_EN; WR2(slot, SDHCI_CLOCK_CONTROL, clk); @@ -427,6 +309,7 @@ if (slot->power == power) return; + slot->power = power; /* Turn off the power. */ @@ -469,7 +352,7 @@ slot->offset += left; /* If we are too fast, broken controllers return zeroes. */ - if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) + if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) DELAY(10); /* Handle unalligned and alligned buffer cases. */ if ((intptr_t)buffer & 3) { @@ -483,7 +366,7 @@ left -= 4; } } else { - bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + bus_read_multi_4(slot->mem_res, SDHCI_BUFFER, (uint32_t *)buffer, left >> 2); left &= 3; } @@ -523,7 +406,7 @@ WR4(slot, SDHCI_BUFFER, data); } } else { - bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + bus_write_multi_4(slot->mem_res, SDHCI_BUFFER, (uint32_t *)buffer, left >> 2); left &= 3; } @@ -577,7 +460,7 @@ if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { if (slot->dev == NULL) { /* If card is present - attach mmc bus. */ - slot->dev = device_add_child(slot->sc->dev, "mmc", -1); + slot->dev = device_add_child(slot->bus, "mmc", -1); device_set_ivars(slot->dev, slot); SDHCI_UNLOCK(slot); device_probe_and_attach(slot->dev); @@ -589,281 +472,132 @@ device_t d = slot->dev; slot->dev = NULL; SDHCI_UNLOCK(slot); - device_delete_child(slot->sc->dev, d); + device_delete_child(slot->bus, d); } else SDHCI_UNLOCK(slot); } } -static int -sdhci_probe(device_t dev) +int +sdhci_init_slot(device_t dev, struct sdhci_slot *slot) { - uint32_t model; - uint16_t subvendor; - uint8_t class, subclass; - int i, result; - - model = (uint32_t)pci_get_device(dev) << 16; - model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; - subvendor = pci_get_subvendor(dev); - class = pci_get_class(dev); - subclass = pci_get_subclass(dev); - - result = ENXIO; - for (i = 0; sdhci_devices[i].model != 0; i++) { - if (sdhci_devices[i].model == model && - (sdhci_devices[i].subvendor == 0xffff || - sdhci_devices[i].subvendor == subvendor)) { - device_set_desc(dev, sdhci_devices[i].desc); - result = BUS_PROBE_DEFAULT; - break; - } - } - if (result == ENXIO && class == PCIC_BASEPERIPH && - subclass == PCIS_BASEPERIPH_SDHC) { - device_set_desc(dev, "Generic SD HCI"); - result = BUS_PROBE_GENERIC; - } - - return (result); -} + uint32_t caps; -static int -sdhci_attach(device_t dev) -{ - struct sdhci_softc *sc = device_get_softc(dev); - uint32_t model; - uint16_t subvendor; - uint8_t class, subclass, progif; - int err, slots, bar, i; + SDHCI_LOCK_INIT(slot); + slot->num = 0; /* XXX: add slot number */ + slot->bus = dev; - sc->dev = dev; - model = (uint32_t)pci_get_device(dev) << 16; - model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; - subvendor = pci_get_subvendor(dev); - class = pci_get_class(dev); - subclass = pci_get_subclass(dev); - progif = pci_get_progif(dev); - /* Apply chip specific quirks. */ - for (i = 0; sdhci_devices[i].model != 0; i++) { - if (sdhci_devices[i].model == model && - (sdhci_devices[i].subvendor == 0xffff || - sdhci_devices[i].subvendor == subvendor)) { - sc->quirks = sdhci_devices[i].quirks; - break; - } + /* Initialize slot. */ + sdhci_init(slot); + slot->version = (RD2(slot, SDHCI_HOST_VERSION) + >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; + caps = RD4(slot, SDHCI_CAPABILITIES); + /* Calculate base clock frequency. */ + slot->max_clk = + (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; + if (slot->max_clk == 0) { + slot->max_clk = 50; + device_printf(dev, "Hardware doesn't specify base clock " + "frequency.\n"); } - /* Some controllers need to be bumped into the right mode. */ - if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) - sdhci_lower_frequency(dev); - /* Read slots info from PCI registers. */ - slots = pci_read_config(dev, PCI_SLOT_INFO, 1); - bar = PCI_SLOT_INFO_FIRST_BAR(slots); - slots = PCI_SLOT_INFO_SLOTS(slots); - if (slots > 6 || bar > 5) { - device_printf(dev, "Incorrect slots information (%d, %d).\n", - slots, bar); - return (EINVAL); + slot->max_clk *= 1000000; + /* Calculate timeout clock frequency. */ + slot->timeout_clk = + (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; + if (slot->timeout_clk == 0) { + device_printf(dev, "Hardware doesn't specify timeout clock " + "frequency.\n"); } - /* Allocate IRQ. */ - sc->irq_rid = 0; - sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, - RF_SHAREABLE | RF_ACTIVE); - if (sc->irq_res == NULL) { - device_printf(dev, "Can't allocate IRQ\n"); - return (ENOMEM); + if (caps & SDHCI_TIMEOUT_CLK_UNIT) + slot->timeout_clk *= 1000; + + slot->host.f_min = slot->max_clk / 256; + slot->host.f_max = slot->max_clk; + if (1 /*FIXME: SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK*/) + slot->timeout_clk = slot->max_clk / 1000; + slot->host.host_ocr = 0; + caps |= SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; + if (caps & SDHCI_CAN_VDD_330) + slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; + if (caps & SDHCI_CAN_VDD_300) + slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; + if (caps & SDHCI_CAN_VDD_180) + slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; + if (slot->host.host_ocr == 0) { + device_printf(dev, "Hardware doesn't report any " + "support voltages.\n"); } - /* Scan all slots. */ - for (i = 0; i < slots; i++) { - struct sdhci_slot *slot = &sc->slots[sc->num_slots]; - uint32_t caps; + slot->host.caps = MMC_CAP_4_BIT_DATA; + if (caps & SDHCI_CAN_DO_HISPD) + slot->host.caps |= MMC_CAP_HSPEED; + /* Decide if we have usable DMA. */ + if (caps & SDHCI_CAN_DO_DMA) + slot->opt |= SDHCI_HAVE_DMA; - SDHCI_LOCK_INIT(slot); - slot->sc = sc; - slot->num = sc->num_slots; - /* Allocate memory. */ - slot->mem_rid = PCIR_BAR(bar + i); - slot->mem_res = bus_alloc_resource(dev, - SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); - if (slot->mem_res == NULL) { - device_printf(dev, "Can't allocate memory\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Allocate DMA tag. */ - err = bus_dma_tag_create(bus_get_dma_tag(dev), - DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, - BUS_SPACE_MAXADDR, NULL, NULL, - DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, - BUS_DMA_ALLOCNOW, NULL, NULL, - &slot->dmatag); - if (err != 0) { - device_printf(dev, "Can't create DMA tag\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Allocate DMA memory. */ - err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, - BUS_DMA_NOWAIT, &slot->dmamap); - if (err != 0) { - device_printf(dev, "Can't alloc DMA memory\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Map the memory. */ - err = bus_dmamap_load(slot->dmatag, slot->dmamap, - (void *)slot->dmamem, DMA_BLOCK_SIZE, - sdhci_getaddr, &slot->paddr, 0); - if (err != 0 || slot->paddr == 0) { - device_printf(dev, "Can't load DMA memory\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Initialize slot. */ - sdhci_init(slot); - caps = RD4(slot, SDHCI_CAPABILITIES); - /* Calculate base clock frequency. */ - slot->max_clk = - (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; - if (slot->max_clk == 0) { - device_printf(dev, "Hardware doesn't specify base clock " - "frequency.\n"); - } - slot->max_clk *= 1000000; - /* Calculate timeout clock frequency. */ - slot->timeout_clk = - (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; - if (slot->timeout_clk == 0) { - device_printf(dev, "Hardware doesn't specify timeout clock " - "frequency.\n"); - } - if (caps & SDHCI_TIMEOUT_CLK_UNIT) - slot->timeout_clk *= 1000; + if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) + slot->opt &= ~SDHCI_HAVE_DMA; + if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) + slot->opt |= SDHCI_HAVE_DMA; - slot->host.f_min = slot->max_clk / 256; - slot->host.f_max = slot->max_clk; - slot->host.host_ocr = 0; - if (caps & SDHCI_CAN_VDD_330) - slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; - if (caps & SDHCI_CAN_VDD_300) - slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; - if (caps & SDHCI_CAN_VDD_180) - slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; - if (slot->host.host_ocr == 0) { - device_printf(dev, "Hardware doesn't report any " - "support voltages.\n"); - } - slot->host.caps = MMC_CAP_4_BIT_DATA; - if (caps & SDHCI_CAN_DO_HISPD) - slot->host.caps |= MMC_CAP_HSPEED; - /* Decide if we have usable DMA. */ - if (caps & SDHCI_CAN_DO_DMA) - slot->opt |= SDHCI_HAVE_DMA; - if (class == PCIC_BASEPERIPH && - subclass == PCIS_BASEPERIPH_SDHC && - progif != PCI_SDHCI_IFDMA) - slot->opt &= ~SDHCI_HAVE_DMA; - if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) - slot->opt &= ~SDHCI_HAVE_DMA; - if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) - slot->opt |= SDHCI_HAVE_DMA; - - if (bootverbose || sdhci_debug) { - slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", - slot->max_clk / 1000000, - (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", - (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", - (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", - (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", - (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); - sdhci_dumpregs(slot); - } - - TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); - callout_init(&slot->card_callout, 1); - sc->num_slots++; + if (bootverbose || sdhci_debug) { + slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", + slot->max_clk / 1000000, + (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", + (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", + (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", + (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", + (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); + sdhci_dumpregs(slot); } - device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); - /* Activate the interrupt */ - err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, - NULL, sdhci_intr, sc, &sc->intrhand); - if (err) - device_printf(dev, "Can't setup IRQ\n"); - pci_enable_busmaster(dev); - /* Process cards detection. */ - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - - sdhci_card_task(slot, 0); - } + + TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); + callout_init(&slot->card_callout, 1); + sdhci_card_task(slot, 0); return (0); } -static int -sdhci_detach(device_t dev) +int +sdhci_cleanup_slot(struct sdhci_slot *slot) { - struct sdhci_softc *sc = device_get_softc(dev); - int i; + device_t d; - bus_teardown_intr(dev, sc->irq_res, sc->intrhand); - bus_release_resource(dev, SYS_RES_IRQ, - sc->irq_rid, sc->irq_res); + callout_drain(&slot->card_callout); + taskqueue_drain(taskqueue_swi_giant, &slot->card_task); - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - device_t d; + SDHCI_LOCK(slot); + d = slot->dev; + slot->dev = NULL; + SDHCI_UNLOCK(slot); + if (d != NULL) + device_delete_child(slot->bus, d); - callout_drain(&slot->card_callout); - taskqueue_drain(taskqueue_swi_giant, &slot->card_task); + SDHCI_LOCK(slot); + sdhci_reset(slot, SDHCI_RESET_ALL); + SDHCI_UNLOCK(slot); + SDHCI_LOCK_DESTROY(slot); - SDHCI_LOCK(slot); - d = slot->dev; - slot->dev = NULL; - SDHCI_UNLOCK(slot); - if (d != NULL) - device_delete_child(dev, d); - - SDHCI_LOCK(slot); - sdhci_reset(slot, SDHCI_RESET_ALL); - SDHCI_UNLOCK(slot); - bus_dmamap_unload(slot->dmatag, slot->dmamap); - bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); - bus_dma_tag_destroy(slot->dmatag); - bus_release_resource(dev, SYS_RES_MEMORY, - slot->mem_rid, slot->mem_res); - SDHCI_LOCK_DESTROY(slot); - } return (0); } -static int -sdhci_suspend(device_t dev) +int +sdhci_generic_suspend(struct sdhci_slot *slot) { - struct sdhci_softc *sc = device_get_softc(dev); - int i, err; + sdhci_reset(slot, SDHCI_RESET_ALL); - err = bus_generic_suspend(dev); - if (err) - return (err); - for (i = 0; i < sc->num_slots; i++) - sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); return (0); } -static int -sdhci_resume(device_t dev) +int +sdhci_generic_resume(struct sdhci_slot *slot) { - struct sdhci_softc *sc = device_get_softc(dev); - int i; + sdhci_init(slot); - for (i = 0; i < sc->num_slots; i++) - sdhci_init(&sc->slots[i]); - return (bus_generic_resume(dev)); + return (0); } -static int -sdhci_update_ios(device_t brdev, device_t reqdev) +int +sdhci_generic_update_ios(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); struct mmc_ios *ios = &slot->host.ios; @@ -887,7 +621,7 @@ slot->hostctrl &= ~SDHCI_CTRL_HISPD; WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); /* Some controllers like reset after bus changes. */ - if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) + if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); SDHCI_UNLOCK(slot); @@ -945,6 +679,7 @@ if ((state & SDHCI_CARD_PRESENT) == 0 || slot->power == 0 || slot->clock == 0) { + printf("NO SD CARD\n"); cmd->error = MMC_ERR_FAILED; slot->req = NULL; slot->curcmd = NULL; @@ -1009,10 +744,8 @@ WR4(slot, SDHCI_ARGUMENT, cmd->arg); /* Set data transfer mode. */ sdhci_set_transfer_mode(slot, cmd->data); - /* Set command flags. */ - WR1(slot, SDHCI_COMMAND_FLAGS, flags); /* Start command. */ - WR1(slot, SDHCI_COMMAND, cmd->opcode); + WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); } static void @@ -1075,12 +808,14 @@ break; } /* Compensate for an off-by-one error in the CaFe chip.*/ - if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) + if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) div++; if (div >= 0xF) { slot_printf(slot, "Timeout too large!\n"); div = 0xE; } + /* FIXME: SDHCI_QUIRK_BROKEN_TIMEOUT_VAL */ + div = 0x0e; WR1(slot, SDHCI_TIMEOUT_CONTROL, div); if (data == NULL) @@ -1090,11 +825,11 @@ if ((slot->opt & SDHCI_HAVE_DMA)) slot->flags |= SDHCI_USE_DMA; /* If data is small, broken DMA may return zeroes instead of data, */ - if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && + if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && (data->len <= 512)) slot->flags &= ~SDHCI_USE_DMA; /* Some controllers require even block sizes. */ - if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && + if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && ((data->len) & 0x3)) slot->flags &= ~SDHCI_USE_DMA; /* Load DMA buffer. */ @@ -1183,7 +918,7 @@ if (sdhci_debug > 1) slot_printf(slot, "result: %d\n", req->cmd->error); if (!req->cmd->error && - (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { + (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { sdhci_reset(slot, SDHCI_RESET_CMD); sdhci_reset(slot, SDHCI_RESET_DATA); } @@ -1194,8 +929,8 @@ req->done(req); } -static int -sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) +int +sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) { struct sdhci_slot *slot = device_get_ivars(reqdev); @@ -1216,15 +951,15 @@ SDHCI_UNLOCK(slot); if (dumping) { while (slot->req != NULL) { - sdhci_intr(slot->sc); + /* XXX: Fixme intr here? */ DELAY(10); } } return (0); } -static int -sdhci_get_ro(device_t brdev, device_t reqdev) +int +sdhci_generic_get_ro(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); uint32_t val; @@ -1235,8 +970,8 @@ return (!(val & SDHCI_WRITE_PROTECT)); } -static int -sdhci_acquire_host(device_t brdev, device_t reqdev) +int +sdhci_generic_acquire_host(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); int err = 0; @@ -1251,8 +986,8 @@ return (err); } -static int -sdhci_release_host(device_t brdev, device_t reqdev) +int +sdhci_generic_release_host(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); @@ -1322,8 +1057,9 @@ } /* Handle PIO interrupt. */ - if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { sdhci_transfer_pio(slot); + } /* Handle DMA border. */ if (intmask & SDHCI_INT_DMA_END) { struct mmc_data *data = slot->curcmd->data; @@ -1382,85 +1118,79 @@ sdhci_reset(slot, SDHCI_RESET_CMD); } -static void -sdhci_intr(void *arg) +void +sdhci_generic_intr(struct sdhci_slot *slot) { - struct sdhci_softc *sc = (struct sdhci_softc *)arg; - int i; + uint32_t intmask; + + SDHCI_LOCK(slot); + /* Read slot interrupt status. */ + intmask = RD4(slot, SDHCI_INT_STATUS); + if (intmask == 0 || intmask == 0xffffffff) { + SDHCI_UNLOCK(slot); + return; + } + if (sdhci_debug > 2) + slot_printf(slot, "Interrupt %#x\n", intmask); - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - uint32_t intmask; - - SDHCI_LOCK(slot); - /* Read slot interrupt status. */ - intmask = RD4(slot, SDHCI_INT_STATUS); - if (intmask == 0 || intmask == 0xffffffff) { - SDHCI_UNLOCK(slot); - continue; - } - if (sdhci_debug > 2) - slot_printf(slot, "Interrupt %#x\n", intmask); + /* Handle card presence interrupts. */ + if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + WR4(slot, SDHCI_INT_STATUS, intmask & + (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); - /* Handle card presence interrupts. */ - if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { - WR4(slot, SDHCI_INT_STATUS, intmask & - (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); - - if (intmask & SDHCI_INT_CARD_REMOVE) { - if (bootverbose || sdhci_debug) - slot_printf(slot, "Card removed\n"); - callout_stop(&slot->card_callout); - taskqueue_enqueue(taskqueue_swi_giant, - &slot->card_task); - } - if (intmask & SDHCI_INT_CARD_INSERT) { - if (bootverbose || sdhci_debug) - slot_printf(slot, "Card inserted\n"); - callout_reset(&slot->card_callout, hz / 2, - sdhci_card_delay, slot); - } - intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); + if (intmask & SDHCI_INT_CARD_REMOVE) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card removed\n"); + callout_stop(&slot->card_callout); + taskqueue_enqueue(taskqueue_swi_giant, + &slot->card_task); } - /* Handle command interrupts. */ - if (intmask & SDHCI_INT_CMD_MASK) { - WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); - sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); + if (intmask & SDHCI_INT_CARD_INSERT) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card inserted\n"); + callout_reset(&slot->card_callout, hz / 2, + sdhci_card_delay, slot); } - /* Handle data interrupts. */ - if (intmask & SDHCI_INT_DATA_MASK) { - WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); - sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); - } - /* Handle AutoCMD12 error interrupt. */ - if (intmask & SDHCI_INT_ACMD12ERR) { - WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); - sdhci_acmd_irq(slot); - } - intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); - intmask &= ~SDHCI_INT_ACMD12ERR; - intmask &= ~SDHCI_INT_ERROR; - /* Handle bus power interrupt. */ - if (intmask & SDHCI_INT_BUS_POWER) { - WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); - slot_printf(slot, - "Card is consuming too much power!\n"); - intmask &= ~SDHCI_INT_BUS_POWER; - } - /* The rest is unknown. */ - if (intmask) { - WR4(slot, SDHCI_INT_STATUS, intmask); - slot_printf(slot, "Unexpected interrupt 0x%08x.\n", - intmask); - sdhci_dumpregs(slot); - } - - SDHCI_UNLOCK(slot); + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); } + /* Handle command interrupts. */ + if (intmask & SDHCI_INT_CMD_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); + sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); + } + /* Handle data interrupts. */ + if (intmask & SDHCI_INT_DATA_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); + sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); + } + /* Handle AutoCMD12 error interrupt. */ + if (intmask & SDHCI_INT_ACMD12ERR) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); + sdhci_acmd_irq(slot); + } + intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); + intmask &= ~SDHCI_INT_ACMD12ERR; + intmask &= ~SDHCI_INT_ERROR; + /* Handle bus power interrupt. */ + if (intmask & SDHCI_INT_BUS_POWER) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); + slot_printf(slot, + "Card is consuming too much power!\n"); + intmask &= ~SDHCI_INT_BUS_POWER; + } + /* The rest is unknown. */ + if (intmask) { + WR4(slot, SDHCI_INT_STATUS, intmask); + slot_printf(slot, "Unexpected interrupt 0x%08x.\n", + intmask); + sdhci_dumpregs(slot); + } + + SDHCI_UNLOCK(slot); } -static int -sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) +int +sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct sdhci_slot *slot = device_get_ivars(child); @@ -1513,8 +1243,8 @@ return (0); } -static int -sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) +int +sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { struct sdhci_slot *slot = device_get_ivars(child); @@ -1569,18 +1299,14 @@ return (0); } +#if 0 static device_method_t sdhci_methods[] = { /* device_if */ - DEVMETHOD(device_probe, sdhci_probe), DEVMETHOD(device_attach, sdhci_attach), DEVMETHOD(device_detach, sdhci_detach), DEVMETHOD(device_suspend, sdhci_suspend), DEVMETHOD(device_resume, sdhci_resume), - /* Bus interface */ - DEVMETHOD(bus_read_ivar, sdhci_read_ivar), - DEVMETHOD(bus_write_ivar, sdhci_write_ivar), - /* mmcbr_if */ DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), DEVMETHOD(mmcbr_request, sdhci_request), @@ -1590,13 +1316,4 @@ {0, 0}, }; - -static driver_t sdhci_driver = { - "sdhci", - sdhci_methods, - sizeof(struct sdhci_softc), -}; -static devclass_t sdhci_devclass; - - -DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); +#endif Index: sys/dev/fb/fbreg.h =================================================================== --- sys/dev/fb/fbreg.h (revision 239664) +++ sys/dev/fb/fbreg.h (working copy) @@ -34,7 +34,7 @@ #define V_MAX_ADAPTERS 8 /* XXX */ /* some macros */ -#if defined(__amd64__) || defined(__i386__) +#if defined(__amd64__) || defined(__i386__) || defined(__arm__) static __inline void copyw(uint16_t *src, uint16_t *dst, size_t size) @@ -49,6 +49,16 @@ #define bzero_io(d, c) bzero((void *)(d), (c)) #define fill_io(p, d, c) fill((p), (void *)(d), (c)) #define fillw_io(p, d, c) fillw((p), (void *)(d), (c)) +#if defined(__arm__) +#define readw(a) (*(uint16_t*)(a)) +#define writew(a, v) (*(uint16_t*)(a) = (v)) +static __inline void +fillw(int val, uint16_t *buf, size_t size) +{ + while (size--) + *buf++ = val; +} +#endif #elif defined(__ia64__) || defined(__sparc64__) #if defined(__ia64__) #include