Driver features include support for twin and wide busses, fast, ultra, ultra2, and double transition(U160) synchronous transfers depending on controller type, and tagged queuing. The driver can support target mode in Operating System environments such as facilities exist in the SCSI layer.
Per target configuration performed in the SCSI-Select menu, accessible at boot in non-EISA models, or through an EISA configuration utility for EISA models, is honored by this driver. This includes synchronous/asynchronous transfers, maximum synchronous negotiation rate, wide transfers, disconnection, the host adapter's SCSI ID, and, PCI controllers, the primary channel selection. For systems that store non-volatile settings in a system specific manner rather than a serial eeprom directly connected to the aic7xxx controller, the BIOS must be enabled for the driver to access this information. This restriction applies to all EISA and many motherboard configurations.
Note that I/O addresses are determined automatically by the probe routines, but care should be taken when using a 284x (VESA local bus controller) in an EISA system. The jumpers setting the I/O area for the 284x should match the EISA slot into which the card is inserted to prevent conflicts with other EISA cards.
Performance and feature sets vary throughout the aic7xxx product line. The following table provides a comparison of the different chips supported by the ahc driver. Note that wide and twin channel features, although always supported by a particular chip, may be disabled in a particular motherboard or card design.
Chip | MIPS | Bus | MaxSync | MaxWidth | SCBs | Features |
---|---|---|---|---|---|---|
aic7770 | 10 | EISA/VL | 10MHz | 16Bit | 4 | 1 |
aic7850 | 10 | PCI/32 | 10MHz | 8Bit | 3 | |
aic7860 | 10 | PCI/32 | 20MHz | 8Bit | 3 | |
aic7870 | 10 | PCI/32 | 10MHz | 16Bit | 16 | |
aic7880 | 10 | PCI/32 | 20MHz | 16Bit | 16 | |
aic7890 | 20 | PCI/32 | 40MHz | 16Bit | 32 | 3 4 5 6 7 8 |
aic7891 | 20 | PCI/64 | 40MHz | 16Bit | 32 | 3 4 5 6 7 8 |
aic7892 | 20 | PCI/64 | 80MHz | 16Bit | 32 | 3 4 5 6 7 8 |
aic7895 | 10/15/20 | PCI/32 | 20MHz | 16Bit | 32 | 2 3 4 5 |
aic7895C | 10/15/20 | PCI/32 | 20MHz | 16Bit | 32 | 2 3 4 5 8 |
aic7896 | 20 | PCI/32 | 40MHz | 16Bit | 32 | 2 3 4 5 6 7 8 |
aic7897 | 20 | PCI/64 | 40MHz | 16Bit | 32 | 2 3 4 5 6 7 8 |
aic7899 | 20 | PCI/64 | 80MHz | 16Bit | 32 | 2 3 4 5 6 7 8 |
If external SRAM is not available, SCBs are a limited resource. Using the SCBs in a straight forward manner would only allow the driver to handle as many concurrent transactions as there are physical SCBs. To fully utilize the SCSI bus and the devices on it, requires much more concurrency. The solution to this problem is SCB Paging, a concept similar to memory paging. SCB paging takes advantage of the fact that devices usually disconnect from the SCSI bus for long periods of time without talking to the controller. The SCBs for disconnected transactions are only of use to the controller when the transfer is resumed. When the host queues another transaction for the controller to execute, the controller firmware will use a free SCB if one is available. Otherwise, the state of the most recently disconnected (and therefor most likely to stay disconnected) SCB is saved, via dma, to host memory, and the local SCB reused to start the new transaction. This allows the controller to queue up to 253 transactions regardless of the amount of SCB space. Since the local SCB space serves as a cache for disconnected transactions, the more SCB space available, the less host bus traffic consumed saving and restoring SCB data.