./kerberosV/src/lib/krb5/krb5.h:#define KDC_OPT_VALIDATE (1 << 31) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKO_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKH_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKK_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKC_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKA_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKM_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKF_EXTENSION ((unsigned long) (1 << 31)) ./kerberosV/src/lib/hx509/ref/pkcs11.h:#define CKR_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./lib/libc/rpc/xdr_rec.c:#define LAST_FRAG ((u_int32_t)(1 << 31)) ./lib/libc/arch/sparc64/fpu/fpu_div.c: * q = 0, bit = 1 << 31; ./lib/libc/arch/sparc64/fpu/fpu_div.c: bit = 1 << 31; \ ./lib/libc/arch/sparc64/fpu/fpu_sqrt.c: * save work. To avoid `(1 << 31) << 1', we also do the top bit ./lib/libc/arch/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; ./lib/libc/arch/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; ./lib/libc/arch/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; ./lib/libc/arch/sparc64/fpu/fpu_mul.c: a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 ./usr.bin/ssh/pkcs11.h:#define CKO_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./usr.bin/ssh/pkcs11.h:#define CKH_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./usr.bin/ssh/pkcs11.h:#define CKK_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./usr.bin/ssh/pkcs11.h:#define CKC_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./usr.bin/ssh/pkcs11.h:#define CKA_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./usr.bin/ssh/pkcs11.h:#define CKM_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./usr.bin/ssh/pkcs11.h:#define CKF_EXTENSION ((unsigned long) (1 << 31)) ./usr.bin/ssh/pkcs11.h:#define CKR_VENDOR_DEFINED ((unsigned long) (1 << 31)) ./gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/xpp.c: printf ("%d\n", foo ((1 << 31) - 1)); ./gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/band.c: return (a & (1 << 31)) != 0; ./gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/conv.c: printf ("%lf, %lf, %lf\n", u2d (~0), u2d (1 << 31), u2d (1)); ./gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/conv.c: printf ("%lf, %lf, %lf\n", i2d (~0), i2d (1 << 31), i2d (1)); ./gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/conv.c: printf ("%u, %u, %u\n", d2u (u2d (~0)), d2u (u2d (1 << 31)), d2u (u2d (1))); ./gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/conv.c: printf ("%d, %d, %d\n", d2i (i2d (~0)), d2i (i2d (1 << 31)), d2i (i2d (1))); ./gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/compile/950612-1.c: return (acc >> 32) + (((((unsigned long long) acc) & 0xffffffff) & (1 << 31)) != 0); ./gnu/usr.bin/gcc/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; ./gnu/usr.bin/gcc/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; ./gnu/usr.bin/gcc/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; ./gnu/usr.bin/gcc/gcc/real.c: sig = sig << 1 << 31; ./gnu/usr.bin/gcc/gcc/final.c: if (l[0] & ((long) 1 << 31)) ./gnu/usr.bin/gcc/gcc/final.c: if (l[1] & ((long) 1 << 31)) ./gnu/usr.bin/gcc/gcc/java/javaop.h: n ^= (jint)1 << 31; ./gnu/usr.bin/gcc/gcc/java/javaop.h: n -= (jint)1 << 31; /* Sign extend lower 32 bits to upper. */ ./gnu/usr.bin/gcc/gcc/config/pa/pa.h: : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \ ./gnu/usr.bin/gcc/gcc/config/pa/pa.h: || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \ ./gnu/usr.bin/gcc/gcc/config/pa/pa.h: == (HOST_WIDE_INT) -1 << 31)) \ ./gnu/usr.bin/gcc/gcc/config/pa/pa.c: ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); ./gnu/usr.bin/gcc/gcc/config/alpha/alpha.c: frame_size >= ((HOST_WIDE_INT) 1 << 31) ? 0 : frame_size); ./gnu/usr.bin/gcc/gcc/config/mips/mips.c:#define RA_MASK BITMASK_HIGH /* 1 << 31 */ ./gnu/usr.bin/gcc/gcc/config/mmix/mmix.c: && value < ((HOST_WIDEST_INT) 1 << 31) * 2) ./gnu/usr.bin/gcc/gcc/config/v850/v850.c: sprintf (buff, "callt ctoff(__callt_return_r2_r%d)", (mask & (1 << 31)) ? 31 : 29); ./gnu/usr.bin/gcc/gcc/config/v850/v850.c: i, (mask & (1 << 31)) ? 31 : 29, stack_bytes ? "c" : ""); ./gnu/usr.bin/gcc/gcc/config/v850/v850.c: sprintf (buff, "callt ctoff(__callt_save_r2_r%d)", (mask & (1 << 31)) ? 31 : 29 ); ./gnu/usr.bin/gcc/gcc/config/v850/v850.c: i, (mask & (1 << 31)) ? 31 : 29, stack_bytes ? "c" : ""); ./gnu/usr.bin/gcc/gcc/config/c4x/c4x.md: && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > ((unsigned) 1 << 31)) ./gnu/usr.bin/gcc/gcc/config/c4x/c4x.c: if (IS_INT16_CONST (val & (1 << 31) ? (val >> i) | ~mask ./gnu/usr.bin/gcc/gcc/config/cris/cris.md: operands[3] = GEN_INT (1 << 31); ./gnu/usr.bin/binutils/bfd/elfxx-mips.c: if (addend & ((bfd_vma) 1 << 31)) ./gnu/usr.bin/binutils/bfd/elfxx-mips.c: if (value & ((bfd_vma) 1 << 31)) ./gnu/usr.bin/binutils/bfd/versados.c: for (shift = ((unsigned long) 1 << 31); shift && srcp < endp; shift >>= 1) ./gnu/usr.bin/binutils/bfd/elf64-ppc.c: ok_tprel = (value + TP_OFFSET + ((bfd_vma) 1 << 31) ./gnu/usr.bin/binutils/gas/config/tc-mcore.c: op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31); ./gnu/usr.bin/binutils/gas/config/tc-mcore.c: op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31); ./gnu/usr.bin/binutils/gas/config/tc-ia64.c: && ((val & ((bfd_vma) 1 << 31)) != 0)) ./gnu/usr.bin/binutils/gas/config/tc-ia64.c: && ((val & ((bfd_vma) 1 << 31)) != 0)) ./gnu/usr.bin/binutils/gas/config/tc-i386.c: return (!(((offsetT) -1 << 31) & num) ./gnu/usr.bin/binutils/gas/config/tc-i386.c: || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); ./gnu/usr.bin/binutils/gas/config/tc-i386.c: val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); ./gnu/usr.bin/binutils/gas/config/tc-i386.c: ^ ((offsetT) 1 << 31)) ./gnu/usr.bin/binutils/gas/config/tc-i386.c: - ((offsetT) 1 << 31)); ./gnu/usr.bin/binutils/gas/config/tc-i386.c: disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); ./gnu/usr.bin/binutils/gas/config/tc-i386.c: exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); ./gnu/usr.bin/binutils/gas/config/tc-sparc.c: bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; ./gnu/usr.bin/binutils/include/opcode/tic80.h:#define TIC80_OPERAND_BITNUM (1 << 31) ./gnu/usr.bin/binutils/opcodes/i386-dis.c: x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); ./gnu/usr.bin/binutils/gdb/go32-nat.c: if ((cpuid_edx & (1 << 31)) != 0) ./gnu/usr.bin/binutils/gdb/arm-tdep.c: (status & (1 << 31)) ? "Hardware" : "Software", ./gnu/usr.bin/binutils/gdb/rdi-share/sys.h:#define TtoH ((unsigned)1 << 31) /* Target-to-Host message */ ./gnu/usr.bin/binutils/gdb/rdi-share/adp.h:#define TtoH ((unsigned)1 << 31) /* Target-to-Host message */ ./gnu/usr.bin/perl/t/op/sprintf2.t: my $fmt = join('', map("%$_\$s%" . ((1 << 31)-$_) . '$s', 1..20)); ./gnu/usr.bin/binutils-2.17/include/opcode/tic80.h:#define TIC80_OPERAND_BITNUM (1 << 31) ./gnu/usr.bin/binutils-2.17/cpu/frv.opc: if (value >= - ((bfd_vma)1 << 31) ./gnu/usr.bin/binutils-2.17/cpu/frv.opc: || value <= ((bfd_vma)1 << 31) - (bfd_vma)1) ./gnu/usr.bin/binutils-2.17/opcodes/i386-dis.c: x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); ./gnu/usr.bin/binutils-2.17/opcodes/sh-opc.h:#define arch_sh_has_dsp (1 << 31) ./gnu/usr.bin/binutils-2.17/opcodes/frv-asm.c: if (value >= - ((bfd_vma)1 << 31) ./gnu/usr.bin/binutils-2.17/opcodes/frv-asm.c: || value <= ((bfd_vma)1 << 31) - (bfd_vma)1) ./gnu/usr.bin/binutils-2.17/gas/config/tc-sparc.c: bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: return (!(((offsetT) -1 << 31) & num) ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: ^ ((offsetT) 1 << 31)) ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: - ((offsetT) 1 << 31)); ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); ./gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c: + ((addressT) 1 << 31)) ./gnu/usr.bin/binutils-2.17/gas/config/tc-mcore.c: op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31); ./gnu/usr.bin/binutils-2.17/gas/config/tc-mcore.c: op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31); ./gnu/usr.bin/binutils-2.17/gas/config/tc-ia64.c: && ((val & ((bfd_vma) 1 << 31)) != 0)) ./gnu/usr.bin/binutils-2.17/gas/config/tc-ia64.c: && ((val & ((bfd_vma) 1 << 31)) != 0)) ./gnu/usr.bin/binutils-2.17/bfd/elf64-ppc.c: ok_tprel = (value + TP_OFFSET + ((bfd_vma) 1 << 31) ./gnu/usr.bin/binutils-2.17/bfd/elfxx-sparc.c: (((bfd_vma)1 << 31) << 1) : 0x400000)) ./gnu/usr.bin/binutils-2.17/bfd/versados.c: for (shift = ((unsigned long) 1 << 31); shift && srcp < endp; shift >>= 1) ./gnu/usr.bin/binutils-2.17/bfd/elfxx-mips.c: if (addend & ((bfd_vma) 1 << 31)) ./gnu/usr.bin/binutils-2.17/bfd/elfxx-mips.c: if (value & ((bfd_vma) 1 << 31)) ./gnu/gcc/gcc/config/s390/s390.c: && INTVAL (op1) < (HOST_WIDE_INT)1 << 31 ./gnu/gcc/gcc/config/s390/s390.c: && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31)) ./gnu/gcc/gcc/config/s390/predicates.md: if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31 ./gnu/gcc/gcc/config/s390/predicates.md: || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31)) ./gnu/gcc/gcc/config/i386/driver-i386.c:#define bit_3DNOW (1 << 31) ./gnu/gcc/gcc/config/mips/mips.c:#define RA_MASK BITMASK_HIGH /* 1 << 31 */ ./gnu/gcc/gcc/config/cris/cris.md: operands[3] = GEN_INT (1 << 31); ./gnu/gcc/gcc/config/frv/frv.md: >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31) ./gnu/gcc/gcc/config/frv/frv.md: - ((unsigned HOST_WIDE_INT)1 << 31)); ./gnu/gcc/gcc/config/frv/frv.md: >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31) ./gnu/gcc/gcc/config/frv/frv.md: - ((unsigned HOST_WIDE_INT)1 << 31)); ./gnu/gcc/gcc/config/v850/v850.c: sprintf (buff, "callt ctoff(__callt_return_r2_r%d)", (mask & (1 << 31)) ? 31 : 29); ./gnu/gcc/gcc/config/v850/v850.c: i, (mask & (1 << 31)) ? 31 : 29, stack_bytes ? "c" : ""); ./gnu/gcc/gcc/config/v850/v850.c: sprintf (buff, "callt ctoff(__callt_save_r2_r%d)", (mask & (1 << 31)) ? 31 : 29 ); ./gnu/gcc/gcc/config/v850/v850.c: i, (mask & (1 << 31)) ? 31 : 29, stack_bytes ? "c" : ""); ./gnu/gcc/gcc/config/mmix/mmix.c: && value < ((HOST_WIDEST_INT) 1 << 31) * 2) ./gnu/gcc/gcc/config/pa/pa.c: ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); ./gnu/gcc/gcc/config/pa/pa.h: : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \ ./gnu/gcc/gcc/config/pa/pa.h: || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \ ./gnu/gcc/gcc/config/pa/pa.h: == (HOST_WIDE_INT) -1 << 31)) \ ./gnu/gcc/gcc/config/pa/pa.h: ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \ ./gnu/gcc/gcc/config/c4x/c4x.c: if (IS_INT16_CONST (val & (1 << 31) ? (val >> i) | ~mask ./gnu/gcc/gcc/config/c4x/c4x.md: && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > ((unsigned) 1 << 31)) ./gnu/gcc/gcc/final.c: if (l[0] & ((long) 1 << 31)) ./gnu/gcc/gcc/final.c: if (l[1] & ((long) 1 << 31)) ./gnu/gcc/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; ./gnu/gcc/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; ./gnu/gcc/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; ./gnu/gcc/gcc/real.c: sig = sig << 1 << 31; ./sys/dev/sbus/rfx.c: if (offset & (1 << 31)) { ./sys/dev/sbus/rfx.c: offset = (offset & ~(1 << 31)) - RFX_RAMDAC_ADDR; ./sys/dev/ic/rtsxreg.h:#define RTSX_START_CMD (1 << 31) ./sys/dev/ic/rtsxreg.h:#define RTSX_TRIG_DMA (1 << 31) ./sys/dev/ic/rtsxreg.h:#define RTSX_CMD_DONE_INT (1 << 31) ./sys/dev/ic/rtsxreg.h:#define RTSX_CMD_DONE_INT_EN (1 << 31) ./sys/dev/ic/silireg.h:#define SILI_PREG_PSS_ATTENTION (1 << 31) ./sys/dev/ic/rt2661reg.h:#define RT2661_RF_BUSY (1 << 31) ./sys/dev/ic/tcic2reg.h:#define TCIC_ADDR_DIAG_NREG ((u_int32_t) 1 << 31) /* inverted! */ ./sys/dev/ic/bwivar.h:#define BWI_DESC32_C_FRAME_START (1 << 31) ./sys/dev/ic/rt2560reg.h:#define RT2560_RF_BUSY (1 << 31) ./sys/dev/ic/rt2860reg.h:#define RT2860_TXDLY_INT_EN (1 << 31) ./sys/dev/ic/rt2860reg.h:#define RT2860_USB_TX_BUSY (1 << 31) ./sys/dev/ic/rt2860reg.h:#define RT2860_CAP_ADC_FEQ (1 << 31) ./sys/dev/ic/rt2860reg.h:#define RT3070_SEL_EFUSE (1 << 31) ./sys/dev/ic/rt2860reg.h:#define RT2860_RF_REG_CTRL (1 << 31) ./sys/dev/ic/rt2860reg.h:#define RT2860_NAV_UPD (1 << 31) ./sys/dev/ic/rt2860reg.h:#define RT3593_LNA_PE_G2_POL (1 << 31) ./sys/dev/ic/bwireg.h:#define BWI_MAC_STATUS_PHYLNK (1 << 31) ./sys/dev/pci/drm/radeon/evergreen_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); ./sys/dev/pci/drm/radeon/evergreen_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); ./sys/dev/pci/drm/radeon/r500_reg.h:# define R300_PIPE_AUTO_CONFIG (1 << 31) ./sys/dev/pci/drm/radeon/r500_reg.h:# define RS480_PDC_EN (1 << 31) ./sys/dev/pci/drm/radeon/r500_reg.h:# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) ./sys/dev/pci/drm/radeon/r500_reg.h:# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) ./sys/dev/pci/drm/radeon/r600_cs.c: if (idx_value & (1 << 31)) { ./sys/dev/pci/drm/radeon/r600d.h:#define RB_RPTR_WR_ENA (1 << 31) ./sys/dev/pci/drm/radeon/r600d.h:#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) ./sys/dev/pci/drm/radeon/r600d.h:#define BILINEAR_PRECISION_8_BIT (1 << 31) ./sys/dev/pci/drm/radeon/r600d.h:# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) ./sys/dev/pci/drm/radeon/r600d.h:# define RB_INT_ENABLE (1 << 31) ./sys/dev/pci/drm/radeon/r600d.h:# define RB_INT_STAT (1 << 31) ./sys/dev/pci/drm/radeon/r600d.h:# define DTO_LOAD (1 << 31) ./sys/dev/pci/drm/radeon/r600d.h:# define PACKET3_CP_DMA_CP_SYNC (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:#define SE_BROADCAST_WRITES (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:#define RB_RPTR_WR_ENA (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:# define HDMI_ACR_AUDIO_PRIORITY (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:# define AFMT_RAMP_DATA_SIGN (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:# define AUDIO_ENABLED (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:#define GUI_ACTIVE (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:#define SE_CB_BUSY (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:# define RB_INT_ENABLE (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:# define RB_INT_STAT (1 << 31) ./sys/dev/pci/drm/radeon/evergreend.h:# define PACKET3_CP_DMA_CP_SYNC (1 << 31) ./sys/dev/pci/drm/radeon/r200.c: radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); ./sys/dev/pci/drm/radeon/rv770d.h:#define RB_RPTR_WR_ENA (1 << 31) ./sys/dev/pci/drm/radeon/rv770d.h:#define BILINEAR_PRECISION_8_BIT (1 << 31) ./sys/dev/pci/drm/radeon/rv770d.h:# define AFMT_RAMP_DATA_SIGN (1 << 31) ./sys/dev/pci/drm/radeon/rv770d.h:# define AUDIO_ENABLED (1 << 31) ./sys/dev/pci/drm/radeon/nid.h:#define GUI_ACTIVE (1 << 31) ./sys/dev/pci/drm/radeon/nid.h:#define SE_CB_BUSY (1 << 31) ./sys/dev/pci/drm/radeon/nid.h:#define SE_BROADCAST_WRITES (1 << 31) ./sys/dev/pci/drm/radeon/nid.h:#define RB_RPTR_WR_ENA (1 << 31) ./sys/dev/pci/drm/radeon/nid.h:# define CMD_VMID_FORCE (1 << 31) ./sys/dev/pci/drm/radeon/r600_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); ./sys/dev/pci/drm/radeon/r600_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); ./sys/dev/pci/drm/radeon/sid.h:#define TRAIN_DONE_D1 (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:#define GUI_ACTIVE (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:#define SE_CB_BUSY (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:#define SE_BROADCAST_WRITES (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:#define RB_RPTR_WR_ENA (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:# define CP_RINGID0_INT_ENABLE (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:# define CP_RINGID0_INT_STAT (1 << 31) ./sys/dev/pci/drm/radeon/sid.h:# define PACKET3_CP_DMA_CP_SYNC (1 << 31) ./sys/dev/pci/drm/radeon/r300_reg.h:# define R300_FPI0_INSERT_NOP (1 << 31) ./sys/dev/pci/drm/radeon/r300_reg.h:# define R300_FPI2_UNKNOWN_31 (1 << 31) ./sys/dev/pci/drm/radeon/r300_reg.h:# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_TVCLK_TURNOFF (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_CUR_LOCK (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_CUR2_LOCK (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_TV_DAC_BDACDET (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_MM_APER (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_RBBM_ACTIVE (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_RB2D_DC_BUSY (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_RB3D_DC_BUSY (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_MC_ENABLE (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_SIGNED_ALPHA_MASK (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_TCL_VTX_Z0 (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_FORCE_W_TO_ONE (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_RB_RPTR_WR_ENA (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define R600_RB_RPTR_WR_ENA (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_TV_ON (1 << 31) ./sys/dev/pci/drm/radeon/radeon_reg.h:# define RADEON_TVPLL_TEST_DIS (1 << 31) ./sys/dev/pci/drm/radeon/r300.c: tmp = idx_value & (1 << 31); ./sys/dev/pci/drm/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { ./sys/dev/pci/drm/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { ./sys/dev/pci/drm/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { ./sys/dev/pci/drm/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { ./sys/dev/pci/drm/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { ./sys/dev/pci/drm/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { ./sys/dev/pci/drm/i915/i915_reg.h:#define DPLL_VCO_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define SDVO_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define DVO_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define LVDS_PORT_EN (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define VIDEO_DIP_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define PP_ON (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define PFIT_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define BLM_PWM_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define BLM_PCH_PWM_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TV_ENC_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TVDAC_STATE_CHG (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TV_BURST_ENA (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TV_EQUAL_ENA (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TV_SC_DDA1_EN (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TV_AUTO_SCALE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TV_CC_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define TV_CC_RDY (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define DP_PORT_EN (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:# define VGA_DISP_DISABLE (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define DE_MASTER_IRQ_CONTROL (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define SDE_AUDIO_POWER_D_CPT (1 << 31) ./sys/dev/pci/drm/i915/i915_reg.h:#define PORT_ENABLE (1 << 31) ./sys/dev/pci/drm/i915/intel_pm.c: I915_WRITE(GEN6_RPNSWREQ, 1 << 31); ./sys/dev/pci/drm/ttm/ttm_bo.c: if (unlikely(sequence - bo->val_seq < (1 << 31))) ./sys/dev/pci/drm/ttm/ttm_bo.c: if (unlikely((bo->val_seq - sequence < (1 << 31)) ./sys/dev/pci/if_wpireg.h:#define WPI_FH_RX_CONFIG_DMA_ENA (1 << 31) ./sys/dev/pci/if_wpireg.h:#define WPI_BSM_WR_CTRL_START (1 << 31) ./sys/dev/pci/if_wpireg.h:#define WPI_INT_FH_RX (1 << 31) ./sys/dev/pci/if_wpireg.h:#define WPI_FW_UPDATED (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_BSM_WR_CTRL_START (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_INT_FH_RX (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_FH_RX_CONFIG_ENA (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) ./sys/dev/pci/if_iwnreg.h:#define IWN_FW_UPDATED (1 << 31) ./sys/dev/pci/pciidereg.h:#define SCH_TIM_SYNCDMA (1 << 31) ./sys/dev/pci/bktr/bktr_core.c:#define BKTR_TEST_RISC_STATUS_BIT3 (1 << 31) ./sys/dev/pci/tcpcib.c: if (reg & (1 << 31) && wdtbase) { ./sys/dev/pci/if_etreg.h:#define ET_SWRST_SELFCLR_DISABLE (1 << 31) ./sys/dev/pci/if_etreg.h:#define ET_MAC_CFG1_SOFT_RST (1 << 31) ./sys/dev/pci/if_etreg.h:#define ET_MII_CFG_RST (1 << 31) ./sys/dev/usb/if_axenreg.h:#define AXEN_RXHDR_CRC_ERR (1 << 31) ./sys/dev/usb/if_rumreg.h:#define RT2573_RF_BUSY (1 << 31) ./sys/dev/usb/if_urtwreg.h:#define URTW_TX_CWMIN (1 << 31) ./sys/dev/usb/if_urtwreg.h:#define URTW_RCR_ONLYERLPKT (1 << 31) ./sys/dev/usb/if_otus.c: hi |= 1 << 31; /* Make sure the broadcast bit is set. */ ./sys/dev/usb/if_zyd.c: hi |= 1 << 31; /* make sure the broadcast bit is set */ ./sys/dev/usb/if_ralreg.h:#define RAL_RF_BUSY (1 << 31) ./sys/dev/usb/if_otusreg.h:#define AR_TX_PHY_SHGI (1 << 31) ./sys/dev/usb/if_zydreg.h:#define ZYD_FILTER_CFE_A (1 << 31) ./sys/kern/kern_workq.c:#define WQT_F_POOL (1 << 31) ./sys/scsi/scsi_disk.h:#define SI_PG_DISK_LIMITS_UGAVALID (1 << 31) ./sys/arch/sparc64/fpu/fpu.c: fs->fs_regs[rd] = fs->fs_regs[rd] & ~(1 << 31); ./sys/arch/sparc64/fpu/fpu.c: fs->fs_regs[rd] = fs->fs_regs[rd] ^ (1 << 31); ./sys/arch/sparc64/fpu/fpu_sqrt.c: * save work. To avoid `(1 << 31) << 1', we also do the top bit ./sys/arch/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; ./sys/arch/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; ./sys/arch/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; ./sys/arch/sparc64/fpu/fpu_div.c: * q = 0, bit = 1 << 31; ./sys/arch/sparc64/fpu/fpu_div.c: bit = 1 << 31; \ ./sys/arch/sparc64/fpu/fpu_mul.c: a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 ./sys/arch/mips64/mips64/cache_r5k.c:#define CF_7_SC (1 << 31) /* Secondary cache not present */ ./sys/arch/arm/include/armreg.h:#define PSR_N_bit (1 << 31) /* negative */ ./sys/arch/hppa/spmath/sgl_float.h:#define Sgl_setnegativezero(sgl_value) Sall(sgl_value) = 1 << 31 ./sys/arch/hppa/spmath/dbl_float.h: Dallp1(dbl_value) = 1 << 31; Dallp2(dbl_value) = 0 ./sys/arch/hppa/spmath/dbl_float.h:#define Dbl_setnegativezerop1(dbl_value) Dallp1(dbl_value) = 1 << 31 ./sys/arch/hppa/hppa/intr.c: mtctl(mask & (1 << 31), CR_EIRR); ./sys/arch/hppa/dev/cpu.c: mtctl((1 << 31), CR_EIRR); ./sys/arch/hppa/dev/cpu.c: ci->ci_mask |= (1 << 31); ./sys/arch/mvme88k/include/m8820x.h:#define CMMU_SRAM (1 << 31) ./sys/arch/mvme88k/include/m8820x.h:#define CMMU_SRAM_MASK ((1 << 31) | (1 << 30)) ./sys/arch/armv7/imx/imxccm.c:#define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) ./sys/arch/armv7/imx/imxccm.c:#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) ./sys/arch/armv7/imx/imxehci.c:#define USBPHY_CTRL_SFTRST (1 << 31) ./sys/arch/armv7/omap/if_cpsw.c: cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | ./sys/arch/armv7/omap/if_cpsw.c: cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) | ./sys/arch/armv7/sunxi/sxiccmu.c:#define CCMU_SCLK_GATING (1 << 31) ./sys/arch/armv7/sunxi/sxiccmu.c:#define CCMU_PLL6_EN (1 << 31) ./sys/arch/sparc/fpu/fpu_mul.c: a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 ./sys/arch/sparc/fpu/fpu_div.c: * q = 0, bit = 1 << 31; ./sys/arch/sparc/fpu/fpu_div.c: bit = 1 << 31; \ ./sys/arch/sparc/fpu/fpu.c: rs1 = fs->fs_regs[rs2] ^ (1 << 31); ./sys/arch/sparc/fpu/fpu.c: rs1 = fs->fs_regs[rs2] & ~(1 << 31); ./sys/arch/sparc/fpu/fpu_sqrt.c: * save work. To avoid `(1 << 31) << 1', we also do the top bit ./sys/arch/sparc/fpu/fpu_sqrt.c: bit = 1 << 31; ./sys/arch/sparc/fpu/fpu_sqrt.c: bit = 1 << 31; ./sys/arch/sparc/fpu/fpu_sqrt.c: bit = 1 << 31; ./sys/arch/sparc/dev/rfx.c: if (offset & (1 << 31)) { ./sys/arch/sparc/dev/rfx.c: offset = (offset & ~(1 << 31)) - RFX_RAMDAC_ADDR; ./sys/arch/i386/pci/pciide_gcsc_reg.h:#define GCSC_ATAC_PIO_FORMAT (1 << 31) /* PIO Mode Format 1 */