contrib/binutils/bfd/elf64-ppc.c: ok_tprel = (value + TP_OFFSET + ((bfd_vma) 1 << 31) contrib/binutils/bfd/elfxx-mips.c: if (addend & ((bfd_vma) 1 << 31)) contrib/binutils/bfd/elfxx-mips.c: if (value & ((bfd_vma) 1 << 31)) contrib/binutils/bfd/elfxx-sparc.c: (((bfd_vma)1 << 31) << 1) : 0x400000)) contrib/binutils/gas/config/tc-i386.c: return (!(((offsetT) -1 << 31) & num) contrib/binutils/gas/config/tc-i386.c: || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); contrib/binutils/gas/config/tc-i386.c: val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); contrib/binutils/gas/config/tc-i386.c: ^ ((offsetT) 1 << 31)) contrib/binutils/gas/config/tc-i386.c: - ((offsetT) 1 << 31)); contrib/binutils/gas/config/tc-i386.c: disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); contrib/binutils/gas/config/tc-i386.c: = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); contrib/binutils/gas/config/tc-i386.c: + ((addressT) 1 << 31)) contrib/binutils/gas/config/tc-ia64.c: && ((val & ((bfd_vma) 1 << 31)) != 0)) contrib/binutils/gas/config/tc-ia64.c: && ((val & ((bfd_vma) 1 << 31)) != 0)) contrib/binutils/gas/config/tc-sparc.c: bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; contrib/binutils/include/opcode/score-inst.h: {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}}, contrib/binutils/opcodes/i386-dis.c: x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); contrib/binutils/opcodes/sh-opc.h:#define arch_sh_has_dsp (1 << 31) contrib/gcc/config/i386/driver-i386.c:#define bit_3DNOW (1 << 31) contrib/gcc/config/mips/mips.c:#define RA_MASK BITMASK_HIGH /* 1 << 31 */ contrib/gcc/config/s390/predicates.md: if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31 contrib/gcc/config/s390/predicates.md: || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31)) contrib/gcc/config/s390/s390.c: && INTVAL (op1) < (HOST_WIDE_INT)1 << 31 contrib/gcc/config/s390/s390.c: && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31)) contrib/gcc/final.c: if (l[0] & ((long) 1 << 31)) contrib/gcc/final.c: if (l[1] & ((long) 1 << 31)) contrib/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; contrib/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; contrib/gcc/real.c: r->sig[0] = (image1 << 31 << 1) | image0; contrib/gcc/real.c: sig = sig << 1 << 31; contrib/gdb/gdb/arm-tdep.c: (status & (1 << 31)) ? "Hardware" : "Software", contrib/gdb/gdb/go32-nat.c: if ((cpuid_edx & (1 << 31)) != 0) contrib/llvm/include/llvm-c/Core.h: LLVMNonLazyBind = 1 << 31 contrib/llvm/include/llvm/CodeGen/MachORelocation.h: return (1 << 31) | (r_pcrel << 30) | ((r_length & 3) << 28) | contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp: int FrameIdx = 1 << 31; contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp: if (FrameIdx != (1 << 31)) { contrib/llvm/tools/clang/lib/CodeGen/CGBlocks.h: BLOCK_HAS_EXTENDED_LAYOUT = (1 << 31) contrib/llvm/tools/lldb/include/lldb/Core/Communication.h: kHiUserBroadcastBit = (1 << 31), contrib/ofed/libmlx4/fixes/rocee_add_support.patch:+ ah->av.port_pd |= htonl(1 << 31); contrib/ofed/libmlx4/src/qp.c: ctrl->owner_opcode = htonl(1 << 31); contrib/ofed/libmlx4/src/qp.c: (ind & qp->sq.wqe_cnt ? htonl(1 << 31) : 0); contrib/ofed/libmlx4/src/verbs.c: ah->av.port_pd |= htonl(1 << 31); contrib/ofed/libmlx4/src/wqe.h: MLX4_INLINE_SEG = 1 << 31, contrib/ofed/libmthca/src/wqe.h: MTHCA_INLINE_SEG = 1 << 31 contrib/ofed/management/infiniband-diags/src/saquery.c: cl_hton32(1 << 31), IB_PIR_COMPMASK_CAPMASK, contrib/ofed/management/opensm/opensm/osm_sa_multipath_record.c: cl_ntoh32(p_mpr->hop_flow_raw) & (1 << 31)) contrib/ofed/management/opensm/opensm/osm_sa_multipath_record.c: cl_ntoh32(p_mpr->hop_flow_raw) & (1 << 31)) contrib/ofed/management/opensm/opensm/osm_sa_multipath_record.c: p_pr->hop_flow_raw &= cl_hton32(1 << 31); contrib/ofed/management/opensm/opensm/osm_sa_path_record.c: (cl_ntoh32(p_pr->hop_flow_raw) & (1 << 31))) contrib/ofed/management/opensm/opensm/osm_sa_path_record.c: cl_ntoh32(p_pr->hop_flow_raw) & (1 << 31)) contrib/ofed/management/opensm/opensm/osm_sa_path_record.c: p_pr->hop_flow_raw &= cl_hton32(1 << 31); contrib/ofed/management/opensm/opensm/osm_sa_portinfo_record.c: cl_ntoh32(p_rcvd_mad->attr_mod) & (1 << 31); contrib/wpa/src/drivers/driver_ndis.c: wep->KeyIndex |= 1 << 31; contrib/wpa/src/drivers/driver_ndis.c: nkey->KeyIndex |= 1 << 31; crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKO_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKH_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKK_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKC_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKA_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKM_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKF_EXTENSION ((unsigned long) (1 << 31)) crypto/heimdal/lib/hx509/ref/pkcs11.h:#define CKR_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/heimdal/lib/krb5/krb5.h:#define KDC_OPT_VALIDATE (1 << 31) crypto/openssh/pkcs11.h:#define CKO_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/openssh/pkcs11.h:#define CKH_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/openssh/pkcs11.h:#define CKK_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/openssh/pkcs11.h:#define CKC_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/openssh/pkcs11.h:#define CKA_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/openssh/pkcs11.h:#define CKM_VENDOR_DEFINED ((unsigned long) (1 << 31)) crypto/openssh/pkcs11.h:#define CKF_EXTENSION ((unsigned long) (1 << 31)) crypto/openssh/pkcs11.h:#define CKR_VENDOR_DEFINED ((unsigned long) (1 << 31)) lib/libc/sparc64/fpu/fpu.c: * only!) using this functions, too, by passing (1 << 31) for one of the lib/libc/sparc64/fpu/fpu.c: __fpu_mov(fe, type, rd, rs2, 0, (1 << 31)); lib/libc/sparc64/fpu/fpu.c: __fpu_mov(fe, type, rd, rs2, (1 << 31), 0); lib/libc/sparc64/fpu/fpu_div.c: * q = 0, bit = 1 << 31; lib/libc/sparc64/fpu/fpu_div.c: bit = 1 << 31; \ lib/libc/sparc64/fpu/fpu_mul.c: a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 lib/libc/sparc64/fpu/fpu_sqrt.c: * save work. To avoid `(1 << 31) << 1', we also do the top bit lib/libc/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; lib/libc/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; lib/libc/sparc64/fpu/fpu_sqrt.c: bit = 1 << 31; lib/libc/xdr/xdr_rec.c:#define LAST_FRAG ((u_int32_t)(1 << 31)) release/picobsd/tinyware/ns/ns.c: u_int index = 1 << 31; sys/amd64/pci/pci_cfgreg.c: outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11) sys/amd64/vmm/intel/vmcs.h:#define VMCS_IDT_VEC_VALID (1 << 31) sys/amd64/vmm/intel/vmx_controls.h:#define PROCBASED_SECONDARY_CONTROLS (1 << 31) sys/amd64/vmm/intel/vtd.c:#define VTD_GCR_TE (1 << 31) sys/amd64/vmm/intel/vtd.c:#define VTD_GSR_TES (1 << 31) sys/arm/arm/cpufunc_asm_pj4b.S: orr r0, r0, #(1 << 31) /* Enable write evict */ sys/arm/arm/db_trace.c: if (index->insn & (1 << 31)) { sys/arm/arm/pl190.c: intc_vic_write_4(VICINTENABLE, (1 << 31)); sys/arm/at91/if_macbvar.h:#define TD_OWN (1 << 31) sys/arm/at91/if_macbvar.h:#define RD_BROADCAST (1 << 31) sys/arm/broadcom/bcm2835/bcm2835_dma.c:#define CS_RESET (1 << 31) sys/arm/econa/if_ece.c: cpu_port_config &= ~(1 << 31); sys/arm/freescale/imx/imx6_anatopreg.h:#define IMX6_ANALOG_CCM_PLL_USB_LOCK (1 << 31) sys/arm/freescale/imx/imx6_usbphy.c:#define CTRL_SFTRST (1 << 31) sys/arm/freescale/imx/imx_gptreg.h:#define GPT_CR_FO3 (1 << 31) sys/arm/freescale/vybrid/vf_anadig.c:#define ANADIG_PLL_LOCKED (1 << 31) sys/arm/freescale/vybrid/vf_ccm.c:#define PLL3_PFD4_EN (1 << 31) sys/arm/freescale/vybrid/vf_ehci.c:#define USBPHY_CTRL_SFTRST (1 << 31) sys/arm/include/armreg.h:#define CPUV7_CT_CTYPE_WT (1 << 31) sys/arm/lpc/if_lpereg.h:#define LPE_HWDESC_INTERRUPT (1 << 31) sys/arm/lpc/if_lpereg.h:#define LPE_HWDESC_ERROR (1 << 31) sys/arm/lpc/if_lpereg.h:#define LPE_HWDESC_ERROR (1 << 31) sys/arm/lpc/lpcreg.h:#define LPC_DMAC_CH_CONTROL_I (1 << 31) sys/arm/mv/mv_pci.c:#define PCI_CFG_ENA (1 << 31) sys/arm/samsung/exynos/ehci_exynos5.c:#define HOST_CTRL_RESET_PHY_ALL (1 << 31) sys/arm/ti/cpsw/if_cpsw.c: cpsw_write_4(sc, CPSW_ALE_CONTROL, 1 << 31 | 1 << 4); sys/arm/ti/cpsw/if_cpsw.c: if ((r & 1 << 31) == 0) sys/arm/ti/cpsw/if_cpsw.c: cmd = 1 << 31 | (reg & 0x1F) << 21 | (phy & 0x1F) << 16; sys/arm/ti/cpsw/if_cpsw.c: cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); sys/arm/xscale/i80321/i80321_aau.c: desc->descr_ctrl = 2 << 1 | 1 << 31; /* Fill, enable dest write */ sys/arm/xscale/i80321/i80321_aau.c: desc->descr_ctrl = 2 << 1 | 1 << 31; /* Fill, enable dest write */; sys/arm/xscale/i8134x/i81342reg.h:#define IOP34X_ADMA_NSE (1 << 31) /* No Snoop Enable */ sys/arm/xscale/i8134x/i81342reg.h: | (1 << 31)) sys/arm/xscale/i8134x/i81342reg.h: | (1 << 31)) sys/arm/xscale/i8134x/i81342reg.h:#define ATUX_CORE_RST ((1 << 30) | (1 << 31)) /* Core Processor Reset */ sys/arm/xscale/i8134x/i81342reg.h:#define ATU_OUMBAR_EN (1 << 31) sys/arm/xscale/ixp425/ixp425reg.h:#define EXP_CNFG0_MEM_MAP (1 << 31) sys/boot/arm/at91/libat91/mci_device.h:#define AT91C_CARD_POWER_UP_BUSY (1 << 31) sys/boot/i386/libfirewire/fwohci.c: OWRITE(sc, OHCI_AREQHI, 1 << 31); sys/boot/i386/libfirewire/fwohci.h:#define OHCI_BUSIRMC (1 << 31) sys/boot/i386/libfirewire/fwohci.h:#define OHCI_SID_ERR (1 << 31) sys/boot/i386/libfirewire/fwohcireg.h:#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) sys/boot/i386/libfirewire/fwohcireg.h:#define OHCI_CNTL_BUFFIL (0x1 << 31) sys/boot/i386/libfirewire/fwohcireg.h:#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ sys/boot/i386/libfirewire/fwohcireg.h:#define OHCI_NODE_VALID (1 << 31) sys/boot/i386/libfirewire/fwohcireg.h:#define OHCI_INT_EN (0x1 << 31) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: mac_hi |= ((mac_lo & (1 << 31) )) >> 31; sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: | (0x1 << 31) | (0x5 << 15) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: | (0x1 << 31) | (0x5 << 15) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: | (0x1 << 31) | (0x5 << 15) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: | (0x1 << 31) | (0x1 << 27) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: | (0x1 << 31) | (0x1 << 27) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: | (0x1 << 31) | (0x1 << 27) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c: OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31) | (0x5 << 15) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31) | (0x5 << 15) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31) | (0x5 << 15) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31) | (0x1 << 27) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31) | (0x1 << 27) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31)); sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31) | (0x1 << 27) sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c: | (0x1 << 31)); sys/contrib/octeon-sdk/cvmx-ixf18201.c: cmd_val |= 1 << 31; // enable in progress bit sys/contrib/octeon-sdk/cvmx-ixf18201.c: cmd_val |= 1 << 31; // enable in progress bit sys/contrib/octeon-sdk/cvmx-ixf18201.c: cmd_val |= 1 << 31; // enable in progress bit sys/contrib/octeon-sdk/cvmx-ixf18201.c: cmd_val |= 1 << 31; // enable in progress bit sys/dev/aac/aacvar.h:#define AAC_FLAGS_NOMSI (1 << 31) /* Broken MSI */ sys/dev/acpica/acpi_video.c:#define DOD_DEVID_SCHEME_STD (1 << 31) sys/dev/acpica/acpi_video.c:#define DSS_COMMIT (1 << 31) sys/dev/agp/agp_i810.c: bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1 << 31)); sys/dev/agp/agp_i810.c: if ((hic & (1 << 31)) == 0) sys/dev/ahci/ahci.h:#define AHCI_PRD_IPC (1 << 31) sys/dev/ata/chipsets/ata-intel.c: tim |= (0x1 << 31); sys/dev/ata/chipsets/ata-intel.c: tim &= ~(0x1 << 31); sys/dev/bktr/bktr_core.c:#define BKTR_TEST_RISC_STATUS_BIT3 (1 << 31) sys/dev/cxgb/common/cxgb_t3_hw.c: t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31); sys/dev/drm/i915_reg.h:#define DPLL_VCO_ENABLE (1 << 31) sys/dev/drm/i915_reg.h:#define SDVO_ENABLE (1 << 31) sys/dev/drm/i915_reg.h:#define DVO_ENABLE (1 << 31) sys/dev/drm/i915_reg.h:#define LVDS_PORT_EN (1 << 31) sys/dev/drm/i915_reg.h:#define PP_ON (1 << 31) sys/dev/drm/i915_reg.h:#define PFIT_ENABLE (1 << 31) sys/dev/drm/i915_reg.h:# define TV_ENC_ENABLE (1 << 31) sys/dev/drm/i915_reg.h:# define TVDAC_STATE_CHG (1 << 31) sys/dev/drm/i915_reg.h:# define TV_BURST_ENA (1 << 31) sys/dev/drm/i915_reg.h:# define TV_EQUAL_ENA (1 << 31) sys/dev/drm/i915_reg.h:# define TV_SC_DDA1_EN (1 << 31) sys/dev/drm/i915_reg.h:# define TV_AUTO_SCALE (1 << 31) sys/dev/drm/i915_reg.h:# define TV_CC_ENABLE (1 << 31) sys/dev/drm/i915_reg.h:# define TV_CC_RDY (1 << 31) sys/dev/drm/i915_reg.h:# define VGA_DISP_DISABLE (1 << 31) sys/dev/drm/mach64_drv.h:# define MACH64_LAST_DESCRIPTOR (1 << 31) sys/dev/drm/mach64_drv.h:# define MACH64_FIFO_ERR (1 << 31) sys/dev/drm/mach64_drv.h:# define MACH64_CRTC_VBLANK2_INT (1 << 31) sys/dev/drm/mga_drv.h:# define MGA_CLIPDIS (1 << 31) sys/dev/drm/mga_drv.h:# define MGA_MAP1_ENABLE (1 << 31) sys/dev/drm/r128_drv.h:# define R128_DST_TILE (1 << 31) sys/dev/drm/r128_drv.h:# define R128_GUI_ACTIVE (1 << 31) sys/dev/drm/r128_drv.h:# define R128_PC_BUSY (1 << 31) sys/dev/drm/r128_drv.h:# define R128_PM4_BUFFER_DL_DONE (1 << 31) sys/dev/drm/r128_drv.h:# define R128_PM4_GUI_ACTIVE (1 << 31) sys/dev/drm/r300_reg.h:# define R300_FPI0_INSERT_NOP (1 << 31) sys/dev/drm/r300_reg.h:# define R300_FPI2_UNKNOWN_31 (1 << 31) sys/dev/drm/r300_reg.h:# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) sys/dev/drm/r600_blit.c: OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm/r600_blit.c: OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm/radeon_cp.c: tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); sys/dev/drm/radeon_drv.h:# define RS480_PDC_EN (1 << 31) sys/dev/drm/radeon_drv.h:# define R300_PIPE_AUTO_CONFIG (1 << 31) sys/dev/drm/radeon_drv.h:# define R300_RB2D_DC_BUSY (1 << 31) sys/dev/drm/radeon_drv.h:# define RADEON_RB3D_ZC_BUSY (1 << 31) sys/dev/drm/radeon_drv.h:# define R300_ZC_BUSY (1 << 31) sys/dev/drm/radeon_drv.h:# define RADEON_RB3D_DC_BUSY (1 << 31) sys/dev/drm/radeon_drv.h:# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) sys/dev/drm/radeon_drv.h:# define RADEON_RBBM_ACTIVE (1 << 31) sys/dev/drm/radeon_drv.h:# define RADEON_RB_RPTR_WR_ENA (1 << 31) sys/dev/drm/radeon_drv.h:#define RADEON_VTX_Z_PRESENT (1 << 31) sys/dev/drm/radeon_drv.h:# define R600_GUI_ACTIVE (1 << 31) sys/dev/drm/radeon_drv.h:# define R600_RB_RPTR_WR_ENA (1 << 31) sys/dev/drm/radeon_drv.h:# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) sys/dev/drm/radeon_drv.h:# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) sys/dev/drm/radeon_drv.h:# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) sys/dev/drm/via_irq.c:#define VIA_IRQ_GLOBAL (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define DPLL_VCO_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define SDVO_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define DVO_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define LVDS_PORT_EN (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define VIDEO_DIP_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define PP_ON (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define PFIT_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TV_ENC_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TVDAC_STATE_CHG (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TV_BURST_ENA (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TV_EQUAL_ENA (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TV_SC_DDA1_EN (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TV_AUTO_SCALE (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TV_CC_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define TV_CC_RDY (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define DP_PORT_EN (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) sys/dev/drm2/i915/i915_reg.h:# define VGA_DISP_DISABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define DE_MASTER_IRQ_CONTROL (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define PORT_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define PWM_ENABLE (1 << 31) sys/dev/drm2/i915/i915_reg.h:#define PWM_PCH_ENABLE (1 << 31) sys/dev/drm2/i915/intel_display.c: I915_WRITE(GEN6_RPNSWREQ, 1 << 31); sys/dev/drm2/radeon/evergreen_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm2/radeon/evergreen_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm2/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { sys/dev/drm2/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { sys/dev/drm2/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { sys/dev/drm2/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { sys/dev/drm2/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { sys/dev/drm2/radeon/evergreen_cs.c: if (idx_value & (1 << 31)) { sys/dev/drm2/radeon/evergreend.h:#define SE_BROADCAST_WRITES (1 << 31) sys/dev/drm2/radeon/evergreend.h:#define RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/evergreend.h:# define HDMI_ACR_AUDIO_PRIORITY (1 << 31) sys/dev/drm2/radeon/evergreend.h:# define AFMT_RAMP_DATA_SIGN (1 << 31) sys/dev/drm2/radeon/evergreend.h:# define AUDIO_ENABLED (1 << 31) sys/dev/drm2/radeon/evergreend.h:#define GUI_ACTIVE (1 << 31) sys/dev/drm2/radeon/evergreend.h:#define SE_CB_BUSY (1 << 31) sys/dev/drm2/radeon/evergreend.h:# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) sys/dev/drm2/radeon/evergreend.h:# define RB_INT_ENABLE (1 << 31) sys/dev/drm2/radeon/evergreend.h:# define RB_INT_STAT (1 << 31) sys/dev/drm2/radeon/evergreend.h:# define PACKET3_CP_DMA_CP_SYNC (1 << 31) sys/dev/drm2/radeon/nid.h:#define GUI_ACTIVE (1 << 31) sys/dev/drm2/radeon/nid.h:#define SE_CB_BUSY (1 << 31) sys/dev/drm2/radeon/nid.h:#define SE_BROADCAST_WRITES (1 << 31) sys/dev/drm2/radeon/nid.h:#define RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/nid.h:# define CMD_VMID_FORCE (1 << 31) sys/dev/drm2/radeon/r200.c: radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); sys/dev/drm2/radeon/r300.c: tmp = idx_value & (1 << 31); sys/dev/drm2/radeon/r300_reg.h:# define R300_FPI0_INSERT_NOP (1 << 31) sys/dev/drm2/radeon/r300_reg.h:# define R300_FPI2_UNKNOWN_31 (1 << 31) sys/dev/drm2/radeon/r300_reg.h:# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) sys/dev/drm2/radeon/r500_reg.h:# define R300_PIPE_AUTO_CONFIG (1 << 31) sys/dev/drm2/radeon/r500_reg.h:# define RS480_PDC_EN (1 << 31) sys/dev/drm2/radeon/r500_reg.h:# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) sys/dev/drm2/radeon/r500_reg.h:# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) sys/dev/drm2/radeon/r600_blit.c: OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm2/radeon/r600_blit.c: OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm2/radeon/r600_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm2/radeon/r600_blit_kms.c: radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); sys/dev/drm2/radeon/r600_cs.c: if (idx_value & (1 << 31)) { sys/dev/drm2/radeon/r600d.h:#define RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/r600d.h:#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) sys/dev/drm2/radeon/r600d.h:#define BILINEAR_PRECISION_8_BIT (1 << 31) sys/dev/drm2/radeon/r600d.h:# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) sys/dev/drm2/radeon/r600d.h:# define RB_INT_ENABLE (1 << 31) sys/dev/drm2/radeon/r600d.h:# define RB_INT_STAT (1 << 31) sys/dev/drm2/radeon/r600d.h:# define DTO_LOAD (1 << 31) sys/dev/drm2/radeon/r600d.h:# define PACKET3_CP_DMA_CP_SYNC (1 << 31) sys/dev/drm2/radeon/radeon_cp.c: tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); sys/dev/drm2/radeon/radeon_drv.h:# define RS480_PDC_EN (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R300_PIPE_AUTO_CONFIG (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R300_RB2D_DC_BUSY (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define RADEON_RB3D_ZC_BUSY (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R300_ZC_BUSY (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define RADEON_RB3D_DC_BUSY (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define RADEON_RBBM_ACTIVE (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define RADEON_RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:#define RADEON_VTX_Z_PRESENT (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R600_GUI_ACTIVE (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R600_RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) sys/dev/drm2/radeon/radeon_drv.h:# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_TVCLK_TURNOFF (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_CUR_LOCK (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_CUR2_LOCK (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_TV_DAC_BDACDET (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_MM_APER (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_RBBM_ACTIVE (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_RB2D_DC_BUSY (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_RB3D_DC_BUSY (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_MC_ENABLE (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_SIGNED_ALPHA_MASK (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_TCL_VTX_Z0 (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_FORCE_W_TO_ONE (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define R600_RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_TV_ON (1 << 31) sys/dev/drm2/radeon/radeon_reg.h:# define RADEON_TVPLL_TEST_DIS (1 << 31) sys/dev/drm2/radeon/rv770d.h:#define RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/rv770d.h:#define BILINEAR_PRECISION_8_BIT (1 << 31) sys/dev/drm2/radeon/rv770d.h:# define AFMT_RAMP_DATA_SIGN (1 << 31) sys/dev/drm2/radeon/rv770d.h:# define AUDIO_ENABLED (1 << 31) sys/dev/drm2/radeon/sid.h:#define TRAIN_DONE_D1 (1 << 31) sys/dev/drm2/radeon/sid.h:# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) sys/dev/drm2/radeon/sid.h:#define GUI_ACTIVE (1 << 31) sys/dev/drm2/radeon/sid.h:#define SE_CB_BUSY (1 << 31) sys/dev/drm2/radeon/sid.h:#define SE_BROADCAST_WRITES (1 << 31) sys/dev/drm2/radeon/sid.h:#define RB_RPTR_WR_ENA (1 << 31) sys/dev/drm2/radeon/sid.h:# define CP_RINGID0_INT_ENABLE (1 << 31) sys/dev/drm2/radeon/sid.h:# define CP_RINGID0_INT_STAT (1 << 31) sys/dev/drm2/radeon/sid.h:# define PACKET3_CP_DMA_CP_SYNC (1 << 31) sys/dev/drm2/ttm/ttm_bo.c: if (unlikely(sequence - bo->val_seq < (1 << 31))) sys/dev/drm2/ttm/ttm_bo.c: if (unlikely((bo->val_seq - sequence < (1 << 31)) sys/dev/drm2/ttm/ttm_bo.c: if ((bo->val_seq - sequence < (1 << 31)) || !bo->seq_valid) sys/dev/e1000/e1000_82575.h:#define E1000_ETQF_QUEUE_ENABLE (1 << 31) sys/dev/e1000/e1000_82575.h:#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ sys/dev/e1000/e1000_ich8lan.c: reg &= ~(1 << 31); sys/dev/e1000/e1000_regs.h:#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ sys/dev/etherswitch/arswitch/arswitchreg.h:#define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31) sys/dev/etherswitch/arswitch/arswitchreg.h:#define AR8X16_VLAN_PRIO_EN (1 << 31) sys/dev/etherswitch/arswitch/arswitchreg.h:#define AR8X16_MDIO_CTRL_BUSY (1 << 31) sys/dev/etherswitch/arswitch/arswitchreg.h:#define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1 << 31) sys/dev/etherswitch/arswitch/arswitchreg.h:#define AR8327_ATU_FUNC_BUSY (1 << 31) sys/dev/etherswitch/arswitch/arswitchreg.h:#define AR8327_VTU_FUNC1_BUSY (1 << 31) sys/dev/ffec/if_ffecreg.h:#define FEC_IER_HBERR (1 << 31) sys/dev/ffec/if_ffecreg.h:#define FEC_MIBC_DIS (1 << 31) sys/dev/ffec/if_ffecreg.h:#define FEC_RCR_GRS (1 << 31) sys/dev/ffec/if_ffecreg.h:#define FEC_TXDESC_READY (1 << 31) sys/dev/ffec/if_ffecreg.h:#define FEC_RXDESC_EMPTY (1 << 31) sys/dev/firewire/firewire.c: CSRARC(fc, IP_CHANNELS) = (1 << 31); sys/dev/firewire/firewire.c: CSRARC(fc, CONF_ROM + 8) = 1 << 31 | 1 << 30 | 1 << 29 | sys/dev/firewire/fwohci.c:uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; sys/dev/firewire/fwohci.c:#define OHCI_BUSIRMC (1 << 31) sys/dev/firewire/fwohci.c:#define OHCI_SID_ERR (1 << 31) sys/dev/firewire/fwohci.c: OWRITE(sc, OHCI_AREQHI, 1 << 31); sys/dev/firewire/fwohcireg.h:#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) sys/dev/firewire/fwohcireg.h:#define OHCI_CNTL_BUFFIL (0x1 << 31) sys/dev/firewire/fwohcireg.h:#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ sys/dev/firewire/fwohcireg.h:#define OHCI_NODE_VALID (1 << 31) sys/dev/firewire/fwohcireg.h:#define OHCI_INT_EN (0x1 << 31) sys/dev/firewire/sbp.c: ocb->orb[0] = htonl(1 << 31); sys/dev/firewire/sbp.h:#define ORB_NOTIFY (1 << 31) sys/dev/firewire/sbp_targ.c: if ((orb0 & (1 << 31)) != 0) { sys/dev/hatm/if_hatmreg.h:#define HE_REGM_TSR4_FLUSH (1 << 31) sys/dev/hatm/if_hatmreg.h:#define HE_REGM_TSR14_CBR_DELETE (1 << 31) sys/dev/hwpmc/hwpmc_mpc7xxx.c:#define MPC7XXX_PMC_HAS_OVERFLOWED(x) (mpc7xxx_pmcn_read(x) & (0x1 << 31)) sys/dev/hwpmc/hwpmc_piv.h:#define P4_CCCR_OVF (1 << 31) sys/dev/hwpmc/hwpmc_powerpc.h:#define POWERPC_PMC_USER_ENABLE (0x1 << 31) sys/dev/if_ndis/if_ndis.c: rkey.nk_keyidx |= 1 << 31; sys/dev/mge/if_mgevar.h:#define MGE_PORT_INT_SUM (1 << 31) sys/dev/mge/if_mgevar.h:#define MGE_PORT_INT_EXT_SUM (1 << 31) sys/dev/mge/if_mgevar.h:#define MGE_DMA_OWNED (1 << 31) sys/dev/mpt/mpt_cam.c: addr |= (1 << 31); sys/dev/mpt/mpt_cam.c: addr |= (1 << 31); sys/dev/msk/if_mskreg.h:#define BIT_31 (1 << 31) sys/dev/mvs/mvs.h:#define EDMA_IE_TRANSPROTERR (1 << 31) /* Transport Proto E */ sys/dev/mxge/mxge_mcp.h:#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) sys/dev/qlxgb/qla_def.h:#define BIT_31 (0x1 << 31) sys/dev/qlxgbe/ql_def.h:#define BIT_31 (0x1 << 31) sys/dev/qlxge/qls_dump.c: Q81_MAC_TX_PARAMS_JUMBO = (1 << 31), /*Control*/ sys/dev/qlxge/qls_hw.h:#define BIT_31 (0x1 << 31) sys/dev/ral/rt2560reg.h:#define RT2560_RF_BUSY (1 << 31) sys/dev/ral/rt2661reg.h:#define RT2661_RF_BUSY (1 << 31) sys/dev/ral/rt2860reg.h:#define RT2860_TXDLY_INT_EN (1 << 31) sys/dev/ral/rt2860reg.h:#define RT2860_USB_TX_BUSY (1 << 31) sys/dev/ral/rt2860reg.h:#define RT2860_CAP_ADC_FEQ (1 << 31) sys/dev/ral/rt2860reg.h:#define RT3070_SEL_EFUSE (1 << 31) sys/dev/ral/rt2860reg.h:#define RT2860_RF_REG_CTRL (1 << 31) sys/dev/ral/rt2860reg.h:#define RT2860_NAV_UPD (1 << 31) sys/dev/ral/rt2860reg.h:#define RT3593_LNA_PE_G2_POL (1 << 31) sys/dev/sound/pci/hda/hdaa.h:#define HDAA_QUIRK_OVREF100 (1 << 31) sys/dev/usb/controller/ehci.h:#define EHCI_ITD_ACTIVE (1 << 31) sys/dev/usb/controller/ehci.h:#define EHCI_SITD_SET_DIR_IN (1 << 31) sys/dev/usb/wlan/if_rumreg.h:#define RT2573_RF_BUSY (1 << 31) sys/dev/usb/wlan/if_runreg.h:#define RT2860_TXDLY_INT_EN (1 << 31) sys/dev/usb/wlan/if_runreg.h:#define RT2860_USB_TX_BUSY (1 << 31) sys/dev/usb/wlan/if_runreg.h:#define RT2860_CAP_ADC_FEQ (1 << 31) sys/dev/usb/wlan/if_runreg.h:#define RT3070_SEL_EFUSE (1 << 31) sys/dev/usb/wlan/if_runreg.h:#define RT2860_RF_REG_CTRL (1 << 31) sys/dev/usb/wlan/if_runreg.h:#define RT2860_NAV_UPD (1 << 31) sys/dev/usb/wlan/if_uralreg.h:#define RAL_RF_BUSY (1 << 31) sys/dev/usb/wlan/if_urtwreg.h:#define URTW_TX_CWMIN (1 << 31) sys/dev/usb/wlan/if_urtwreg.h:#define URTW_RCR_ONLYERLPKT (1 << 31) sys/dev/usb/wlan/if_urtwreg.h:#define URTW_RX_FLAG_OWN (1 << 31) sys/dev/usb/wlan/if_urtwreg.h:#define URTW_TX_FLAG_OWN (1 << 31) sys/dev/usb/wlan/if_zydreg.h:#define ZYD_FILTER_CFE_A (1 << 31) sys/dev/wpi/if_wpireg.h:#define WPI_UC_RUN (1 << 31) sys/dev/wpi/if_wpireg.h:#define WPI_RX_INTR (1 << 31) sys/dev/wpi/if_wpireg.h:#define WPI_FW_UPDATED (1 << 31 ) sys/geom/raid/tr_raid1e.c: mask |= 1 << 31; sys/geom/raid/tr_raid1e.c: if ((mask & (1 << 31)) != 0) sys/geom/raid/tr_raid1e.c: (mask & (1 << 31)) != 0) { sys/geom/raid/tr_raid1e.c: if ((mask & (1 << 31)) != 0) { sys/i386/pci/pci_cfgreg.c: outl(CONF1_ADDR_PORT, (1 << 31) sys/mips/atheros/ar71xxreg.h:#define PLL_SW_UPDATE (1 << 31) sys/mips/atheros/ar71xxreg.h:#define RST_WDOG_LAST (1 << 31) sys/mips/atheros/ar71xxreg.h:#define MAC_CFG1_SOFT_RESET (1 << 31) sys/mips/atheros/ar71xxreg.h:#define MAC_MII_CFG_RESET (1 << 31) sys/mips/atheros/ar934xreg.h:#define AR934X_RESET_HOST (1 << 31) sys/mips/atheros/if_argevar.h:#define ARGE_DESC_EMPTY (1 << 31) sys/mips/malta/gt_pci.c: GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1 << 31) | addr); sys/mips/malta/gt_pci.c: GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1 << 31) | addr); sys/mips/nlm/dev/net/nae.c: (1 << 31) | /* soft reset */ sys/mips/nlm/dev/net/nae.c: nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1 << 31)); sys/mips/nlm/dev/net/sgmii.c: data1 = (0x1 << 31); /* soft reset */ sys/mips/nlm/dev/net/sgmii.c: data1 &= ~(0x01 << 31); sys/mips/nlm/dev/net/sgmii.c: mac_cfg1 &= ~(0x1 << 31); /* remove reset */ sys/mips/nlm/dev/net/sgmii.c: mac_cfg1 |= (0x1 << 31); /* set reset */ sys/mips/nlm/xlp_machdep.c: pagegrain |= (1 << 31) | /* RIE */ sys/mips/rmi/pic.h: xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1 << 31) | (level << 30) | sys/ofed/drivers/infiniband/hw/mlx4/mlx4_ib.h: MLX4_IB_SRIOV_SQP = 1 << 31, sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: ctrl->owner_opcode = cpu_to_be32(1 << 31); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | header_size); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | spc); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | header_size); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | spc); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | spc); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: iseg->byte_count = cpu_to_be32((1 << 31) | 4); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: inl->byte_count = cpu_to_be32(1 << 31); sys/ofed/drivers/infiniband/hw/mlx4/qp.c: (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; sys/ofed/drivers/infiniband/hw/mthca/mthca_mcg.c: if (mgm->qp[i] == cpu_to_be32(ibqp->qp_num | (1 << 31))) { sys/ofed/drivers/infiniband/hw/mthca/mthca_mcg.c: } else if (!(mgm->qp[i] & cpu_to_be32(1 << 31))) { sys/ofed/drivers/infiniband/hw/mthca/mthca_mcg.c: mgm->qp[i] = cpu_to_be32(ibqp->qp_num | (1 << 31)); sys/ofed/drivers/infiniband/hw/mthca/mthca_mcg.c: if (mgm->qp[i] == cpu_to_be32(ibqp->qp_num | (1 << 31))) sys/ofed/drivers/infiniband/hw/mthca/mthca_mcg.c: if (!(mgm->qp[i] & cpu_to_be32(1 << 31))) sys/ofed/drivers/infiniband/hw/mthca/mthca_provider.c: shift = __ffs(mask | 1 << 31); sys/ofed/drivers/infiniband/hw/mthca/mthca_qp.c: sqd_event = 1 << 31; sys/ofed/drivers/infiniband/hw/mthca/mthca_qp.c: cpu_to_be32((1 << 31) | 4); sys/ofed/drivers/infiniband/hw/mthca/mthca_qp.c: cpu_to_be32((1 << 31) | 4); sys/ofed/drivers/net/mlx4/en_tx.c: inl->byte_count = cpu_to_be32(1 << 31 | len); sys/ofed/drivers/net/mlx4/en_tx.c: inl->byte_count = cpu_to_be32(1 << 31 | spc); sys/ofed/drivers/net/mlx4/en_tx.c: inl->byte_count = cpu_to_be32(1 << 31 | (len - spc)); sys/ofed/drivers/net/mlx4/mcg.c: qpn |= (1 << 31); sys/ofed/include/linux/mlx4/qp.h: MLX4_WQE_FMR_PERM_ATOMIC = 1 << 31 sys/ofed/include/linux/mlx4/qp.h: MLX4_INLINE_SEG = 1 << 31, sys/ofed/include/rdma/ib_verbs.h: IB_QP_CREATE_RESERVED_END = 1 << 31, sys/powerpc/fpu/fpu_div.c: * q = 0, bit = 1 << 31; sys/powerpc/fpu/fpu_div.c: bit = 1 << 31; \ sys/powerpc/fpu/fpu_emu.c: *a ^= (1 << 31); sys/powerpc/fpu/fpu_emu.c: *a |= (1 << 31); sys/powerpc/fpu/fpu_emu.c: *a &= ~(1 << 31); sys/powerpc/fpu/fpu_mul.c: a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 sys/powerpc/fpu/fpu_sqrt.c: * save work. To avoid `(1 << 31) << 1', we also do the top bit sys/powerpc/fpu/fpu_sqrt.c: bit = 1 << 31; sys/powerpc/fpu/fpu_sqrt.c: bit = 1 << 31; sys/powerpc/fpu/fpu_sqrt.c: bit = 1 << 31; sys/powerpc/powermac/nvbl.c:#define NVIDIA_PMC_BL_EN (1 << 31) sys/sys/consio.h:#define CONS_LOCAL_CURSOR (1 << 31) sys/x86/iommu/intel_reg.h:#define DMAR_GCMD_TE (1 << 31) /* Translation Enable */ sys/x86/iommu/intel_reg.h:#define DMAR_GSTS_TES (1 << 31) /* Translation Enable Status */ sys/x86/iommu/intel_reg.h:#define DMAR_CCMD_ICC32 (1 << 31) sys/x86/iommu/intel_reg.h:#define DMAR_IOTLB_IVT32 (1 << 31) sys/x86/iommu/intel_reg.h:#define DMAR_FECTL_IM (1 << 31) /* Interrupt Mask */ sys/x86/iommu/intel_reg.h:#define DMAR_FRCD2_F32 (1 << 31) sys/x86/iommu/intel_reg.h:#define DMAR_PMEN_EPM (1 << 31) /* Enable Protected Memory */ sys/x86/iommu/intel_reg.h:#define DMAR_IECTL_IM (1 << 31) /* Interrupt Mask */ usr.sbin/bluetooth/bthidd/kbd.c:#define E0PREFIX (1 << 31)