Index: sys/dev/alc/if_alc.c
===================================================================
--- sys/dev/alc/if_alc.c	(revision 250664)
+++ sys/dev/alc/if_alc.c	(working copy)
@@ -110,6 +110,8 @@
 		"Atheros AR8152 v1.1 PCIe Fast Ethernet" },
 	{ VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024,
 		"Atheros AR8152 v2.0 PCIe Fast Ethernet" },
+	{ VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 6 * 1024,
+		"Atheros AR8161 PCIe Fast Ethernet" },
 	{ 0, 0, 0, NULL}
 };
 
@@ -433,6 +435,7 @@
 		case DEVICEID_ATHEROS_AR8151_V2:
 		case DEVICEID_ATHEROS_AR8152_B:
 		case DEVICEID_ATHEROS_AR8152_B2:
+		case DEVICEID_ATHEROS_AR8161:
 			alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
 			    ALC_MII_DBG_ADDR, 0x00);
 			val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
@@ -484,6 +487,7 @@
 		case DEVICEID_ATHEROS_AR8151_V2:
 		case DEVICEID_ATHEROS_AR8152_B:
 		case DEVICEID_ATHEROS_AR8152_B2:
+		case DEVICEID_ATHEROS_AR8161:
 			alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
 			    ALC_MII_DBG_ADDR, 0x00);
 			val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
@@ -541,8 +545,10 @@
 	CSR_READ_2(sc, ALC_GPHY_CFG);
 	DELAY(10 * 1000);
 
+	/* Will the AR8161 also need this? XXX */
 	/* DSP fixup, Vendor magic. */
-	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
+	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161) {
 		alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
 		    ALC_MII_DBG_ADDR, 0x000A);
 		data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
@@ -553,7 +559,8 @@
 	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
 	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
 	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
-	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2 ||
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161) {
 		alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
 		    ALC_MII_DBG_ADDR, 0x003B);
 		data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
@@ -571,7 +578,8 @@
 	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
 	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 ||
 	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
-	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2 ||
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161) {
 		alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
 		    ALC_MII_DBG_ADDR, 0x0029);
 		alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
@@ -694,10 +702,14 @@
 
 	if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
 		/* Disable extended sync except AR8152 B v1.0 */
+		/* Will AR8161 also need this ? XXX */
 		linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC;
 		if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
 		    sc->alc_rev == ATHEROS_AR8152_B_V10)
 			linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
+		/* XXX 8161 ? */
+		if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161)
+			linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
 		CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
 		    linkcfg);
 		pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
@@ -715,10 +727,15 @@
 			pmcfg |= PM_CFG_ASPM_L0S_ENB;
 		if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
 			pmcfg |= PM_CFG_ASPM_L1_ENB;
+		/* AR8161 need this ? XXX */
 		if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
 			if (sc->alc_ident->deviceid ==
 			    DEVICEID_ATHEROS_AR8152_B)
 				pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+			/* XXX 8161 */
+			if (sc->alc_ident->deviceid ==
+			    DEVICEID_ATHEROS_AR8161)
+				pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
 			pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
 			    PM_CFG_SERDES_PLL_L1_ENB |
 			    PM_CFG_SERDES_BUDS_RX_L1_ENB);
@@ -727,11 +744,16 @@
 				pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
 				switch (sc->alc_ident->deviceid) {
 				case DEVICEID_ATHEROS_AR8152_B:
+				  /*  AR8161 is either closer to 8162_B or B2 */
+#if 0
+				case DEVICEID_ATHEROS_AR8161:	/* XXX ? */
+#endif
 					pmcfg |= (7 <<
 					    PM_CFG_L1_ENTRY_TIMER_SHIFT);
 					break;
 				case DEVICEID_ATHEROS_AR8152_B2:
-				case DEVICEID_ATHEROS_AR8151_V2:
+				case DEVICEID_ATHEROS_AR8151_V2: /*XXX ?*/
+				case DEVICEID_ATHEROS_AR8161:
 					pmcfg |= (4 <<
 					    PM_CFG_L1_ENTRY_TIMER_SHIFT);
 					break;
@@ -830,6 +852,15 @@
 			val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
 			CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
 		}
+		/* XXX 8161 ? */
+		if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161) {
+			val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
+			val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
+			    PCIE_PHYMISC2_SERDES_TH_MASK);
+			val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
+			val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
+			CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
+		}
 		/* Disable ASPM L0S and L1. */
 		cap = CSR_READ_2(sc, base + PCIER_LINK_CAP);
 		if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
@@ -872,6 +903,7 @@
 	switch (sc->alc_ident->deviceid) {
 	case DEVICEID_ATHEROS_AR8152_B:
 	case DEVICEID_ATHEROS_AR8152_B2:
+	case DEVICEID_ATHEROS_AR8161:	/* XXX ? */
 		sc->alc_flags |= ALC_FLAG_APS;
 		/* FALLTHROUGH */
 	case DEVICEID_ATHEROS_AR8132:
@@ -2047,7 +2079,7 @@
 
 		if (M_WRITABLE(m) == 0) {
 			/* Get a writable copy. */
-			m = m_dup(*m_head, M_NOWAIT);
+			m = m_dup(*m_head, M_DONTWAIT);
 			/* Release original mbufs. */
 			m_freem(*m_head);
 			if (m == NULL) {
@@ -2125,7 +2157,7 @@
 	error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
 	    *m_head, txsegs, &nsegs, 0);
 	if (error == EFBIG) {
-		m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS);
+		m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS);
 		if (m == NULL) {
 			m_freem(*m_head);
 			*m_head = NULL;
@@ -2467,7 +2499,8 @@
 	    MAC_CFG_SPEED_MASK);
 	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
 	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
-	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2 ||
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161)
 		reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
 	/* Reprogram MAC with resolved speed/duplex. */
 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
@@ -2803,7 +2836,7 @@
 	bus_dmamap_t map;
 	int nsegs;
 
-	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 	if (m == NULL)
 		return (ENOBUFS);
 	m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
@@ -2923,7 +2956,7 @@
 	 * header from the mbuf chain. This can save lots of CPU
 	 * cycles for jumbo frame.
 	 */
-	MGETHDR(n, M_NOWAIT, MT_DATA);
+	MGETHDR(n, M_DONTWAIT, MT_DATA);
 	if (n == NULL) {
 		ifp->if_iqdrops++;
 		m_freem(m);
@@ -3104,8 +3137,9 @@
 		device_printf(sc->alc_dev, "master reset timeout!\n");
 
 	for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
-		if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0)
-			break;
+		reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
+			if ((reg & IDLE_STATUS_RXMAC) == 0)
+				break;
 		DELAY(10);
 	}
 
@@ -3238,6 +3272,17 @@
 		CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
 		CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
 		CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
+	} else	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161) {
+		/* looks similar might be identical to 8152_B XXX */
+		/* Reconfigure SRAM - Vendor magic. */
+		CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
+		CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
+		CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
+		CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
+		CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
+		CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
+		CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
+		CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
 	}
 
 	/* Tell hardware that we're ready to load DMA blocks. */
@@ -3325,7 +3370,8 @@
 	reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
 	    TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
 	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
-	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2 ||
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161)
 		reg >>= 1;
 	reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
 	    TXQ_CFG_TD_BURST_MASK;
@@ -3355,8 +3401,10 @@
 		     RX_FIFO_PAUSE_THRESH_HI_MASK));
 	}
 
+	/* XXX 8161 ? */
 	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
-	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2)
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161)
 		CSR_WRITE_4(sc, ALC_SERDES_LOCK,
 		    CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
 		    SERDES_PHY_CLK_SLOWDOWN);
@@ -3410,7 +3458,8 @@
 	    MAC_CFG_PREAMBLE_MASK);
 	if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
 	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
-	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2 ||
+	    sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8161)
 		reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
 	if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
 		reg |= MAC_CFG_SPEED_10_100;
Index: sys/dev/alc/if_alcreg.h
===================================================================
--- sys/dev/alc/if_alcreg.h	(revision 250664)
+++ sys/dev/alc/if_alcreg.h	(working copy)
@@ -44,6 +44,7 @@
 #define	DEVICEID_ATHEROS_AR8151_V2	0x1083	/* L1D V2.0 */
 #define	DEVICEID_ATHEROS_AR8152_B	0x2060	/* L2C V1.1 */
 #define	DEVICEID_ATHEROS_AR8152_B2	0x2062	/* L2C V2.0 */
+#define DEVICEID_ATHEROS_AR8161		0x1091	/* ??? */
 
 #define	ATHEROS_AR8152_B_V10		0xC0
 #define	ATHEROS_AR8152_B_V11		0xC1