Index: mips/atheros/uart_bus_ar71xx.c =================================================================== --- mips/atheros/uart_bus_ar71xx.c (revision 211426) +++ mips/atheros/uart_bus_ar71xx.c (working copy) @@ -41,6 +41,7 @@ #include #include +#include #include "uart_if.h" Index: mips/atheros/ar91xxreg.h =================================================================== --- mips/atheros/ar91xxreg.h (revision 211440) +++ mips/atheros/ar91xxreg.h (working copy) @@ -34,6 +34,8 @@ /* reset block */ #define AR91XX_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c +#define AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE (1 << 10) + /* PLL block */ #define AR91XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 #define AR91XX_PLL_REG_ETH_CONFIG AR71XX_PLL_CPU_BASE + 0x04 Index: mips/atheros/ar724x_chip.h =================================================================== --- mips/atheros/ar724x_chip.h (revision 0) +++ mips/atheros/ar724x_chip.h (revision 0) @@ -0,0 +1,6 @@ +#ifndef __AR724X_CHIP_H__ +#define __AR724X_CHIP_H__ + +extern struct ar71xx_cpu_def ar724x_chip_def; + +#endif Index: mips/atheros/files.ar71xx =================================================================== --- mips/atheros/files.ar71xx (revision 211426) +++ mips/atheros/files.ar71xx (working copy) @@ -15,3 +15,8 @@ mips/atheros/ar71xx_bus_space_reversed.c standard mips/mips/intr_machdep.c standard mips/mips/tick.c standard + +mips/atheros/ar71xx_chip.c standard +mips/atheros/ar724x_chip.c standard +mips/atheros/ar91xx_chip.c standard +mips/atheros/ar71xx_setup.c standard Index: mips/atheros/ar71xx_machdep.c =================================================================== --- mips/atheros/ar71xx_machdep.c (revision 211426) +++ mips/atheros/ar71xx_machdep.c (working copy) @@ -56,7 +56,12 @@ #include #include +#include +#include +#include +#include + extern char edata[], end[]; uint32_t ar711_base_mac[ETHER_ADDR_LEN]; @@ -118,9 +123,7 @@ void platform_reset(void) { - uint32_t reg = ATH_READ_REG(AR71XX_RST_RESET); - - ATH_WRITE_REG(AR71XX_RST_RESET, reg | RST_RESET_FULL_CHIP); + ar71xx_device_stop(RST_RESET_FULL_CHIP); /* Wait for reset */ while(1) ; @@ -143,7 +146,6 @@ __register_t a2 __unused, __register_t a3 __unused) { uint64_t platform_counter_freq; - uint32_t reg; int argc, i, count = 0; char **argv, **envp; vm_offset_t kernend; @@ -202,12 +204,21 @@ * should be called first. */ init_param1(); + + /* Detect the system type - this is needed for subsequent chipset-specific calls */ + ar71xx_detect_sys_type(); + ar71xx_detect_sys_frequency(); + platform_counter_freq = ar71xx_cpu_freq(); mips_timer_init_params(platform_counter_freq, 1); cninit(); init_static_kenv(boot1_env, sizeof(boot1_env)); - printf("platform frequency: %lld\n", platform_counter_freq); + printf("CPU platform: %s\n", ar71xx_get_system_type()); + printf("CPU Frequency=%d MHz\n", u_ar71xx_cpu_freq / 1000000); + printf("CPU DDR Frequency=%d MHz\n", u_ar71xx_ddr_freq / 1000000); + printf("CPU AHB Frequency=%d MHz\n", u_ar71xx_ahb_freq / 1000000); + printf("arguments: \n"); printf(" a0 = %08x\n", a0); printf(" a1 = %08x\n", a1); @@ -244,23 +255,8 @@ /* * Reset USB devices */ - reg = ATH_READ_REG(AR71XX_RST_RESET); - reg |= - RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY; - ATH_WRITE_REG(AR71XX_RST_RESET, reg); - DELAY(1000); - reg &= - ~(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY); - ATH_WRITE_REG(AR71XX_RST_RESET, reg); - - ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG, - USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP | - USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP); + ar71xx_init_usb_peripheral(); - ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, - (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT)); - DELAY(1000); - kdb_init(); #ifdef KDB if (boothowto & RB_KDB) Index: mips/atheros/ar71xx_cpudef.h =================================================================== --- mips/atheros/ar71xx_cpudef.h (revision 0) +++ mips/atheros/ar71xx_cpudef.h (revision 0) @@ -0,0 +1,71 @@ +#ifndef __AR71XX_CPUDEF_H__ +#define __AR71XX_CPUDEF_H__ + + +struct ar71xx_cpu_def { + void (* detect_mem_size) (void); + void (* detect_sys_frequency) (void); + void (* ar71xx_chip_device_stop) (uint32_t); + void (* ar71xx_chip_device_start) (uint32_t); + int (* ar71xx_chip_device_stopped) (uint32_t); + void (* ar71xx_chip_set_pll_ge0) (int); + void (* ar71xx_chip_set_pll_ge1) (int); + void (* ar71xx_chip_ddr_flush_ge0) (int); + void (* ar71xx_chip_ddr_flush_ge1) (int); + uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int); + + /* + * From Linux - Handling this IRQ is a bit special. + * AR71xx - AR71XX_DDR_REG_FLUSH_PCI + * AR724x - AR724X_DDR_REG_FLUSH_PCIE + * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC + * + * These are set when STATUSF_IP2 is set in regiser c0. + * This flush is done before the IRQ is handled to make + * sure the driver correctly sees any memory updates. + */ + void (* ar71xx_chip_irq_flush_ip2) (void); + /* + * The USB peripheral init code is subtly different for + * each chip. + */ + void (* ar71xx_chip_init_usb_peripheral) (void); +}; + +extern struct ar71xx_cpu_def * ar71xx_cpu_ops; + +static inline void ar71xx_detect_sys_frequency(void) +{ + ar71xx_cpu_ops->detect_sys_frequency(); +} + +static inline void ar71xx_device_stop(uint32_t mask) +{ + ar71xx_cpu_ops->ar71xx_chip_device_stop(mask); +} + +static inline void ar71xx_device_start(uint32_t mask) +{ + ar71xx_cpu_ops->ar71xx_chip_device_start(mask); +} + +static inline int ar71xx_device_stopped(uint32_t mask) +{ + return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask); +} + +static inline void ar71xx_init_usb_peripheral(void) +{ + ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral(); +} + +/* XXX shouldn't be here! */ +extern uint32_t u_ar71xx_cpu_freq; +extern uint32_t u_ar71xx_ahb_freq; +extern uint32_t u_ar71xx_ddr_freq; + +static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; } +static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; } +static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; } + +#endif Index: mips/atheros/ar71xx_pci.c =================================================================== --- mips/atheros/ar71xx_pci.c (revision 211426) +++ mips/atheros/ar71xx_pci.c (working copy) @@ -56,6 +56,8 @@ #include #include +#include + #undef AR71XX_PCI_DEBUG #ifdef AR71XX_PCI_DEBUG #define dprintf printf @@ -258,7 +260,6 @@ { int busno = 0; int rid = 0; - uint32_t reset; struct ar71xx_pci_softc *sc = device_get_softc(dev); sc->sc_mem_rman.rm_type = RMAN_ARRAY; @@ -295,15 +296,10 @@ } /* reset PCI core and PCI bus */ - reset = ATH_READ_REG(AR71XX_RST_RESET); - reset |= (RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); - ATH_WRITE_REG(AR71XX_RST_RESET, reset); - ATH_READ_REG(AR71XX_RST_RESET); + ar71xx_device_stop(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); DELAY(100000); - reset &= ~(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); - ATH_WRITE_REG(AR71XX_RST_RESET, reset); - ATH_READ_REG(AR71XX_RST_RESET); + ar71xx_device_start(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); DELAY(100000); /* Init PCI windows */ Index: mips/atheros/if_arge.c =================================================================== --- mips/atheros/if_arge.c (revision 211426) +++ mips/atheros/if_arge.c (working copy) @@ -79,6 +79,7 @@ #include #include +#include #undef ARGE_DEBUG #ifdef ARGE_DEBUG @@ -181,14 +182,8 @@ static void arge_flush_ddr(struct arge_softc *sc) { - - ATH_WRITE_REG(sc->arge_ddr_flush_reg, 1); - while (ATH_READ_REG(sc->arge_ddr_flush_reg) & 1) - ; - - ATH_WRITE_REG(sc->arge_ddr_flush_reg, 1); - while (ATH_READ_REG(sc->arge_ddr_flush_reg) & 1) - ; + /* XXX this should eventually call the CPU ops to flush the specific NIC -adrian */ + ar71xx_ddr_flush(sc->arge_ddr_flush_reg); } static int @@ -236,6 +231,7 @@ KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), ("if_arge: Only MAC0 and MAC1 supported")); + /* XXX these should eventually be replaced with calls to the CPU ops, not hard-coded -adrian */ if (sc->arge_mac_unit == 0) { sc->arge_ddr_flush_reg = AR71XX_WB_FLUSH_GE0; sc->arge_pll_reg = AR71XX_PLL_ETH_INT0_CLK; @@ -381,19 +377,9 @@ DELAY(20); /* Step 2. Punt the MAC core from the central reset register */ - reg = ATH_READ_REG(AR71XX_RST_RESET); - if (sc->arge_mac_unit == 0) - reg |= RST_RESET_GE0_MAC; - else if (sc->arge_mac_unit == 1) - reg |= RST_RESET_GE1_MAC; - ATH_WRITE_REG(AR71XX_RST_RESET, reg); + ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); DELAY(100); - reg = ATH_READ_REG(AR71XX_RST_RESET); - if (sc->arge_mac_unit == 0) - reg &= ~RST_RESET_GE0_MAC; - else if (sc->arge_mac_unit == 1) - reg &= ~RST_RESET_GE1_MAC; - ATH_WRITE_REG(AR71XX_RST_RESET, reg); + ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); /* Step 3. Reconfigure MAC block */ ARGE_WRITE(sc, AR71XX_MAC_CFG1, @@ -680,6 +666,7 @@ ARGE_UNLOCK(sc); } +/* XXX this should be replaced with a call through CPU ops to set the PLL -adrian */ static void arge_set_pll(struct arge_softc *sc, int media, int duplex) { Index: mips/atheros/uart_cpu_ar71xx.c =================================================================== --- mips/atheros/uart_cpu_ar71xx.c (revision 211426) +++ mips/atheros/uart_cpu_ar71xx.c (working copy) @@ -40,6 +40,7 @@ #include #include +#include bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; Index: mips/atheros/ar71xx_chip.c =================================================================== --- mips/atheros/ar71xx_chip.c (revision 0) +++ mips/atheros/ar71xx_chip.c (revision 0) @@ -0,0 +1,190 @@ +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +#include + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +/* XXX these should replace the current definitions in ar71xxreg.h */ +/* XXX perhaps an ar71xx_chip.h header file? */ +#define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +/* XXX these shouldn't be in here - this file is a per-chip file */ +/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */ +uint32_t u_ar71xx_cpu_freq; +uint32_t u_ar71xx_ahb_freq; +uint32_t u_ar71xx_ddr_freq; + +static void +ar71xx_chip_detect_mem_size(void) +{ +#if 0 + unsigned long size; + + for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; + size <<= 1 ) { + if (!memcmp(ar71xx_detect_mem_size, + ar71xx_detect_mem_size + size, 1024)) + break; + } + add_memory_region(0, size, BOOT_MEM_RAM); +#endif +} + +static void +ar71xx_chip_detect_sys_frequency(void) +{ + uint32_t pll; + uint32_t freq; + uint32_t div; + + pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; + freq = div * AR71XX_BASE_FREQ; + + div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; + u_ar71xx_cpu_freq = freq / div; + + div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; + u_ar71xx_ddr_freq = freq / div; + + div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; + u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; +} + + +/* + * This does not lock the CPU whilst doing the work! + */ +static void +ar71xx_chip_device_stop(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR71XX_RST_RESET); + ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask); +} + +static void +ar71xx_chip_device_start(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR71XX_RST_RESET); + ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask); +} + +static int +ar71xx_chip_device_stopped(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR71XX_RST_RESET); + return ((reg & mask) == mask); +} + +static void +ar71xx_chip_set_pll_ge0(int speed) +{ +} + +static void +ar71xx_chip_set_pll_ge1(int speed) +{ +} + +static void +ar71xx_chip_ddr_flush_ge0(int speed) +{ +} + +static void +ar71xx_chip_ddr_flush_ge1(int speed) +{ +} + +static uint32_t +ar71xx_chip_get_eth_pll(unsigned int mac, int speed) +{ + return 0; +} + +static void +ar71xx_chip_init_usb_peripheral(void) +{ + ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY); + DELAY(1000); + + ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY); + DELAY(1000); + + ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG, + USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP | + USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP); + + ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, + (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT)); + + DELAY(1000); +} + +struct ar71xx_cpu_def ar71xx_chip_def = { + &ar71xx_chip_detect_mem_size, + &ar71xx_chip_detect_sys_frequency, + &ar71xx_chip_device_stop, + &ar71xx_chip_device_start, + &ar71xx_chip_device_stopped, + &ar71xx_chip_set_pll_ge0, + &ar71xx_chip_set_pll_ge1, + &ar71xx_chip_ddr_flush_ge0, + &ar71xx_chip_ddr_flush_ge1, + &ar71xx_chip_get_eth_pll, + NULL, + &ar71xx_chip_init_usb_peripheral, +}; Index: mips/atheros/ar91xx_chip.c =================================================================== --- mips/atheros/ar91xx_chip.c (revision 0) +++ mips/atheros/ar91xx_chip.c (revision 0) @@ -0,0 +1,156 @@ +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +#include + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +static void +ar91xx_chip_detect_mem_size(void) +{ +#if 0 + unsigned long size; + + for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; + size <<= 1 ) { + if (!memcmp(ar71xx_detect_mem_size, + ar71xx_detect_mem_size + size, 1024)) + break; + } + add_memory_region(0, size, BOOT_MEM_RAM); +#endif +} + +static void +ar91xx_chip_detect_sys_frequency(void) +{ + uint32_t pll; + uint32_t freq; + uint32_t div; + + pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); + freq = div * AR91XX_BASE_FREQ; + + u_ar71xx_cpu_freq = freq; + + div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; + u_ar71xx_ddr_freq = freq / div; + + div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; + u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; +} + +static void +ar91xx_chip_device_stop(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); + ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask); +} + +static void +ar91xx_chip_device_start(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); + ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask); +} + +static int +ar91xx_chip_device_stopped(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); + return ((reg & mask) == mask); +} + +static void +ar91xx_chip_set_pll_ge0(int speed) +{ +} + +static void +ar91xx_chip_set_pll_ge1(int speed) +{ +} + +static void +ar91xx_chip_ddr_flush_ge0(int speed) +{ + ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); +} + +static void +ar91xx_chip_ddr_flush_ge1(int speed) +{ + ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); +} + +static uint32_t +ar91xx_chip_get_eth_pll(unsigned int mac, int speed) +{ + return 0; +} + +static void +ar91xx_chip_init_usb_peripheral(void) +{ + ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE); + DELAY(100); + + ar71xx_device_start(RST_RESET_USB_HOST); + DELAY(100); + + ar71xx_device_start(RST_RESET_USB_PHY); + DELAY(100); +} + +struct ar71xx_cpu_def ar91xx_chip_def = { + &ar91xx_chip_detect_mem_size, + &ar91xx_chip_detect_sys_frequency, + &ar91xx_chip_device_stop, + &ar91xx_chip_device_start, + &ar91xx_chip_device_stopped, + &ar91xx_chip_set_pll_ge0, + &ar91xx_chip_set_pll_ge1, + &ar91xx_chip_ddr_flush_ge0, + &ar91xx_chip_ddr_flush_ge1, + &ar91xx_chip_get_eth_pll, + NULL, + &ar91xx_chip_init_usb_peripheral, +}; Index: mips/atheros/ar71xx_chip.h =================================================================== --- mips/atheros/ar71xx_chip.h (revision 0) +++ mips/atheros/ar71xx_chip.h (revision 0) @@ -0,0 +1,6 @@ +#ifndef __AR71XX_CHIP_H__ +#define __AR71XX_CHIP_H__ + +extern struct ar71xx_cpu_def ar71xx_chip_def; + +#endif Index: mips/atheros/ar91xx_chip.h =================================================================== --- mips/atheros/ar91xx_chip.h (revision 0) +++ mips/atheros/ar91xx_chip.h (revision 0) @@ -0,0 +1,6 @@ +#ifndef __AR91XX_CHIP_H__ +#define __AR91XX_CHIP_H__ + +extern struct ar71xx_cpu_def ar91xx_chip_def; + +#endif Index: mips/atheros/ar71xx_setup.c =================================================================== --- mips/atheros/ar71xx_setup.c (revision 0) +++ mips/atheros/ar71xx_setup.c (revision 0) @@ -0,0 +1,134 @@ +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +#include + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include + +#define AR71XX_SYS_TYPE_LEN 128 + +static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; +enum ar71xx_soc_type ar71xx_soc; +struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL; + +void +ar71xx_detect_sys_type(void) +{ + char *chip = "????"; + uint32_t id; + uint32_t major; + uint32_t minor; + uint32_t rev = 0; + + id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + ar71xx_cpu_ops = &ar71xx_chip_def; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + ar71xx_soc = AR71XX_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + ar71xx_soc = AR71XX_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + ar71xx_soc = AR71XX_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + ar71xx_soc = AR71XX_SOC_AR7240; + chip = "7240"; + ar71xx_cpu_ops = &ar724x_chip_def; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7241: + ar71xx_soc = AR71XX_SOC_AR7241; + chip = "7241"; + ar71xx_cpu_ops = &ar724x_chip_def; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7242: + ar71xx_soc = AR71XX_SOC_AR7242; + chip = "7242"; + ar71xx_cpu_ops = &ar724x_chip_def; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR91XX_REV_ID_MINOR_MASK; + rev = id >> AR91XX_REV_ID_REVISION_SHIFT; + rev &= AR91XX_REV_ID_REVISION_MASK; + ar71xx_cpu_ops = &ar91xx_chip_def; + switch (minor) { + case AR91XX_REV_ID_MINOR_AR9130: + ar71xx_soc = AR71XX_SOC_AR9130; + chip = "9130"; + break; + + case AR91XX_REV_ID_MINOR_AR9132: + ar71xx_soc = AR71XX_SOC_AR9132; + chip = "9132"; + break; + } + break; + + default: + panic("ar71xx: unknown chip id:0x%08x\n", id); + } + + sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); +} + +const char * +ar71xx_get_system_type(void) +{ + return ar71xx_sys_type; +} + Index: mips/atheros/ar71xx_wdog.c =================================================================== --- mips/atheros/ar71xx_wdog.c (revision 211426) +++ mips/atheros/ar71xx_wdog.c (working copy) @@ -41,6 +41,7 @@ #include #include +#include struct ar71xx_wdog_softc { device_t dev; Index: mips/atheros/ar71xx_setup.h =================================================================== --- mips/atheros/ar71xx_setup.h (revision 0) +++ mips/atheros/ar71xx_setup.h (revision 0) @@ -0,0 +1,20 @@ +#ifndef __AR71XX_SETUP_H__ +#define __AR71XX_SETUP_H__ + +enum ar71xx_soc_type { + AR71XX_SOC_UNKNOWN, + AR71XX_SOC_AR7130, + AR71XX_SOC_AR7141, + AR71XX_SOC_AR7161, + AR71XX_SOC_AR7240, + AR71XX_SOC_AR7241, + AR71XX_SOC_AR7242, + AR71XX_SOC_AR9130, + AR71XX_SOC_AR9132 +}; +extern enum ar71xx_soc_type ar71xx_soc; + +extern void ar71xx_detect_sys_type(void); +extern const char *ar71xx_get_system_type(void); + +#endif Index: mips/atheros/ar724x_chip.c =================================================================== --- mips/atheros/ar724x_chip.c (revision 0) +++ mips/atheros/ar724x_chip.c (revision 0) @@ -0,0 +1,157 @@ +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +#include + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +static void +ar724x_chip_detect_mem_size(void) +{ +#if 0 + unsigned long size; + + for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; + size <<= 1 ) { + if (!memcmp(ar71xx_detect_mem_size, + ar71xx_detect_mem_size + size, 1024)) + break; + } + add_memory_region(0, size, BOOT_MEM_RAM); +#endif +} + +static void +ar724x_chip_detect_sys_frequency(void) +{ + uint32_t pll; + uint32_t freq; + uint32_t div; + + pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * AR724X_BASE_FREQ; + + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); + freq *= div; + + u_ar71xx_cpu_freq = freq; + + div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + u_ar71xx_ddr_freq = freq / div; + + div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; + u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; +} + +static void +ar724x_chip_device_stop(uint32_t mask) +{ +#if 0 + mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; + local_irq_save(flags); + t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); + t |= mask; + t &= ~mask_inv; + ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); + local_irq_restore(flags); + break; +#endif +} + +static void +ar724x_chip_device_start(uint32_t mask) +{ +#if 0 + mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; + local_irq_save(flags); + t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); + t &= ~mask; + t |= mask_inv; + ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); + local_irq_restore(flags); + break; +#endif +} + +static int +ar724x_chip_device_stopped(uint32_t mask) +{ +#if 0 + local_irq_save(flags); + t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); + local_irq_restore(flags); + break; +#endif + return 0; /* XXX for now */ +} + +static void +ar724x_chip_set_pll_ge0(int speed) +{ +} + +static void +ar724x_chip_set_pll_ge1(int speed) +{ +} + +static void +ar724x_chip_ddr_flush_ge0(int speed) +{ +} + +static void +ar724x_chip_ddr_flush_ge1(int speed) +{ +} + +static uint32_t +ar724x_chip_get_eth_pll(unsigned int mac, int speed) +{ + return 0; +} + +struct ar71xx_cpu_def ar724x_chip_def = { + &ar724x_chip_detect_mem_size, + &ar724x_chip_detect_sys_frequency, + &ar724x_chip_device_stop, + &ar724x_chip_device_start, + &ar724x_chip_device_stopped, + &ar724x_chip_set_pll_ge0, + &ar724x_chip_set_pll_ge1, + &ar724x_chip_ddr_flush_ge0, + &ar724x_chip_ddr_flush_ge1, + &ar724x_chip_get_eth_pll, +}; Index: mips/atheros/ar71xxreg.h =================================================================== --- mips/atheros/ar71xxreg.h (revision 211426) +++ mips/atheros/ar71xxreg.h (working copy) @@ -160,7 +160,11 @@ #define GPIO_FUNC_USB_OC_EN (1 << 4) #define GPIO_FUNC_USB_CLK_EN (0) +#define AR71XX_GPIO_COUNT 16 + #define AR71XX_BASE_FREQ 40000000 + +#define AR71XX_PLL_CPU_BASE 0x18050000 #define AR71XX_PLL_CPU_CONFIG 0x18050000 #define PLL_SW_UPDATE (1 << 31) #define PLL_LOCKED (1 << 30) @@ -183,6 +187,9 @@ #define AR71XX_PLL_SEC_CONFIG 0x18050004 #define AR71XX_PLL_CPU_CLK_CTRL 0x18050008 #define AR71XX_PLL_ETH_INT0_CLK 0x18050010 + +/* XXX these PLL values are wrong for non-AR71XX - it needs to be abstracted out! */ +/* -adrian */ #define AR71XX_PLL_ETH_INT1_CLK 0x18050014 #define XPLL_ETH_INT_CLK_10 0x00991099 #define XPLL_ETH_INT_CLK_100 0x00441011 @@ -194,6 +201,10 @@ #define AR71XX_PLL_ETH_EXT_CLK 0x18050018 #define AR71XX_PLL_PCI_CLK 0x1805001C +/* Reset block */ + +#define AR71XX_RST_BLOCK_BASE 0x18060000 + #define AR71XX_RST_WDOG_CONTROL 0x18060008 #define RST_WDOG_LAST (1 << 31) #define RST_WDOG_ACTION_MASK 3 @@ -221,7 +232,9 @@ #define AR71XX_PCI_INTR_MASK 0x1806001C #define PCI_INTR_CORE (1 << 4) +/* XXX this needs to be removed and moved into per-chip code -adrian */ #define AR71XX_RST_RESET 0x18060024 +#define RST_RESET_MODULE_EXTERNAL (1 << 28) #define RST_RESET_FULL_CHIP (1 << 24) /* Same as pulling the reset pin */ #define RST_RESET_CPU_COLD (1 << 20) /* Cold reset */ @@ -235,6 +248,8 @@ #define RST_RESET_PCI_BUS (1 << 1) #define RST_RESET_PCI_CORE (1 << 0) +#define AR71XX_RST_RESET_REG_REV_ID 0x18060090 + /* * GigE adapters region */ @@ -453,43 +468,52 @@ #define SPI_IO_CTRL_DO 1 #define AR71XX_SPI_RDS 0x0C +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR91XX_REV_ID_MINOR_MASK 0x3 +#define AR91XX_REV_ID_MINOR_AR9130 0x0 +#define AR91XX_REV_ID_MINOR_AR9132 0x1 +#define AR91XX_REV_ID_REVISION_MASK 0x3 +#define AR91XX_REV_ID_REVISION_SHIFT 2 + +#define AR71XX_MEM_SIZE_MIN 0x0200000 +#define AR71XX_MEM_SIZE_MAX 0x10000000 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR71XX_PLL_VAL_1000 0x00110000 +#define AR71XX_PLL_VAL_100 0x00001099 +#define AR71XX_PLL_VAL_10 0x00991099 + + #define ATH_READ_REG(reg) \ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) #define ATH_WRITE_REG(reg, val) \ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val) -static inline uint64_t -ar71xx_cpu_freq(void) +static inline void +ar71xx_ddr_flush(uint32_t reg) { - uint32_t pll_config, div; - uint64_t freq; + ATH_WRITE_REG(reg, 1); + while ((ATH_READ_REG(reg) & 0x1)) + ; - /* PLL freq */ - pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); - div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1; - freq = div * AR71XX_BASE_FREQ; - /* CPU freq */ - div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK) - + 1; - freq = freq / div; - - return (freq); + ATH_WRITE_REG(reg, 1); + while ((ATH_READ_REG(reg) & 0x1)) + ; } -static inline uint64_t -ar71xx_ahb_freq(void) -{ - uint32_t pll_config, div; - uint64_t freq; - - /* PLL freq */ - pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); - /* AHB freq */ - div = (((pll_config >> PLL_AHB_DIV_SHIFT) & PLL_AHB_DIV_MASK) + 1) * 2; - freq = ar71xx_cpu_freq() / div; - return (freq); -} - - #endif /* _AR71XX_REG_H_ */