Index: sys/conf/options.mips
===================================================================
--- sys/conf/options.mips	(revision 255499)
+++ sys/conf/options.mips	(working copy)
@@ -29,6 +29,8 @@
 # $FreeBSD$
 
 CPU_MIPS4KC	opt_global.h
+CPU_MIPS24KC	opt_global.h
+CPU_MIPS74KC	opt_global.h
 CPU_MIPS32	opt_global.h
 CPU_MIPS64	opt_global.h
 CPU_SENTRY5	opt_global.h
Index: sys/mips/conf/AR934X_BASE
===================================================================
--- sys/mips/conf/AR934X_BASE	(revision 255499)
+++ sys/mips/conf/AR934X_BASE	(working copy)
@@ -12,7 +12,7 @@
 
 machine         mips mips
 ident		AR934X_BASE
-cpu		CPU_MIPS4KC
+cpu		CPU_MIPS74KC
 makeoptions	KERNLOADADDR=0x80050000
 options		HZ=1000
 
Index: sys/mips/include/asm.h
===================================================================
--- sys/mips/include/asm.h	(revision 255499)
+++ sys/mips/include/asm.h	(working copy)
@@ -725,6 +725,10 @@
 #elif defined(CPU_RMI)
 #define	HAZARD_DELAY
 #define	ITLBNOPFIX
+#elif defined(CPU_MIPS74KC)
+/* 0xc0 = EHB */
+#define	HAZARD_DELAY	 .word 0xc0
+#define	ITLBNOPFIX	 .word 0xc0
 #else
 #define	ITLBNOPFIX	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
 #define	HAZARD_DELAY	nop;nop;nop;nop;nop;
Index: sys/mips/include/cpuregs.h
===================================================================
--- sys/mips/include/cpuregs.h	(revision 255499)
+++ sys/mips/include/cpuregs.h	(working copy)
@@ -149,6 +149,11 @@
 #define	MIPS_CCA_CC	0x05	/* Cacheable Coherent. */
 #endif
 
+#if defined(CPU_MIPS74KC)
+#define	MIPS_CCA_UNCACHED	0x02	/* Uncached. */
+#define	MIPS_CCA_CACHED		0x00	/* Cacheable, coherency unspecified. */
+#endif
+
 #ifndef	MIPS_CCA_UNCACHED
 #define	MIPS_CCA_UNCACHED	MIPS_CCA_UC
 #endif
@@ -213,6 +218,9 @@
 #endif
 #define	COP0_HAZARD_FPUENABLE	nop; nop; nop; nop;
 
+#undef	COP0_SYNC
+#define	COP0_SYNC	.word 0xc0
+
 /*
  * The bits in the cause register.
  *