Index: if_ath_ahb.c
===================================================================
--- if_ath_ahb.c	(revision 221057)
+++ if_ath_ahb.c	(working copy)
@@ -78,15 +78,15 @@
 };
 
 #define	VENDOR_ATHEROS	0x168c
-#define	AR9100_DEVID	0x000b
+#define	AR9130_DEVID	0x000b
 
 static int
 ath_ahb_probe(device_t dev)
 {
 	const char* devname;
 
-	/* Atheros / ar9100 */
-	devname = ath_hal_probe(VENDOR_ATHEROS, AR9100_DEVID);
+	/* Atheros / ar9130 */
+	devname = ath_hal_probe(VENDOR_ATHEROS, AR9130_DEVID);
 
 	if (devname != NULL) {
 		device_set_desc(dev, devname);
@@ -187,7 +187,7 @@
 
 	ATH_LOCK_INIT(sc);
 
-	error = ath_attach(AR9100_DEVID, sc);
+	error = ath_attach(AR9130_DEVID, sc);
 	if (error == 0)					/* success */
 		return 0;
 
Index: ath_hal/ar5416/ar5416_power.c
===================================================================
--- ath_hal/ar5416/ar5416_power.c	(revision 221057)
+++ ath_hal/ar5416/ar5416_power.c	(working copy)
@@ -52,6 +52,9 @@
 				goto bad;			
 		}
 
+		if (AR_SREV_HOWL(ah))
+			OS_REG_SET_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
+
 		OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
 		OS_DELAY(50);   /* Give chip the chance to awake */
 
@@ -88,7 +91,8 @@
 	if (setChip) {
 		/* Clear the RTC force wake bit to allow the mac to sleep */
 		OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
-		OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
+		if (! AR_SREV_HOWL(ah))
+			OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
 		/* Shutdown chip. Active low */
 		OS_REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
 	}
Index: ath_hal/ar5416/ar2133.c
===================================================================
--- ath_hal/ar5416/ar2133.c	(revision 221057)
+++ ath_hal/ar5416/ar2133.c	(working copy)
@@ -171,7 +171,7 @@
 			aModeRefSel = ath_hal_reverseBits(1, 2);
 	} else if ((freq % 10) == 0) {
 		channelSel = ath_hal_reverseBits(((freq - 4800) / 10 << 1), 8);
-		if (AR_SREV_SOWL_10_OR_LATER(ah))
+		if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah))
 			aModeRefSel = ath_hal_reverseBits(2, 2);
 		else
 			aModeRefSel = ath_hal_reverseBits(1, 2);
Index: ath_hal/ar5416/ar5416_interrupts.c
===================================================================
--- ath_hal/ar5416/ar5416_interrupts.c	(revision 221057)
+++ ath_hal/ar5416/ar5416_interrupts.c	(working copy)
@@ -34,6 +34,10 @@
 ar5416IsInterruptPending(struct ath_hal *ah)
 {
 	uint32_t isr;
+
+	if (AR_SREV_HOWL(ah))
+		return AH_TRUE;
+
 	/* 
 	 * Some platforms trigger our ISR before applying power to
 	 * the card, so make sure the INTPEND is really 1, not 0xffffffff.
@@ -63,22 +67,27 @@
 HAL_BOOL
 ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
 {
-	uint32_t isr, isr0, isr1, sync_cause;
+	uint32_t isr, isr0, isr1, sync_cause = 0;
 
 	/*
 	 * Verify there's a mac interrupt and the RTC is on.
 	 */
-	if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
-	    (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+	if (AR_SREV_HOWL(ah)) {
+		*masked = 0;
 		isr = OS_REG_READ(ah, AR_ISR);
-	else
-		isr = 0;
-	sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
-	sync_cause &= AR_INTR_SYNC_DEFAULT;
-	*masked = 0;
+	} else {
+		if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+		    (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+			isr = OS_REG_READ(ah, AR_ISR);
+		else
+			isr = 0;
+		sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+		sync_cause &= AR_INTR_SYNC_DEFAULT;
+		*masked = 0;
 
-	if (isr == 0 && sync_cause == 0)
-		return AH_FALSE;
+		if (isr == 0 && sync_cause == 0)
+			return AH_FALSE;
+	}
 
 	if (isr != 0) {
 		struct ath_hal_5212 *ahp = AH5212(ah);
@@ -122,7 +131,7 @@
 			ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
 		}
 
-		if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) {
+		if ((! AR_SREV_HOWL(ah)) && (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah))) {
 			uint32_t isr5;
 			isr5 = OS_REG_READ(ah, AR_ISR_S5_S);
 			if (isr5 & AR_ISR_S5_TIM_TIMER)
@@ -138,6 +147,10 @@
 #endif
 		*masked |= mask2;
 	}
+
+	if (AR_SREV_HOWL(ah))
+		return AH_TRUE;
+
 	if (sync_cause != 0) {
 		if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) {
 			*masked |= HAL_INT_FATAL;
@@ -186,11 +199,13 @@
 		OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
 		(void) OS_REG_READ(ah, AR_IER);
 
-		OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
-		(void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+		if (! AR_SREV_HOWL(ah)) {
+			OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+			(void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);
 
-		OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
-		(void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);
+			OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+			(void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);
+		}
 	}
 
 	mask = ints & HAL_INT_COMMON;
@@ -270,19 +285,21 @@
 		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
 		OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
 
-		mask = AR_INTR_MAC_IRQ;
-		if (ints & HAL_INT_GPIO)
-			mask |= SM(AH5416(ah)->ah_gpioMask,
-			    AR_INTR_ASYNC_MASK_GPIO);
-		OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask);
-		OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask);
+		if (! AR_SREV_HOWL(ah)) {
+			mask = AR_INTR_MAC_IRQ;
+			if (ints & HAL_INT_GPIO)
+				mask |= SM(AH5416(ah)->ah_gpioMask,
+				    AR_INTR_ASYNC_MASK_GPIO);
+			OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask);
+			OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask);
 
-		mask = AR_INTR_SYNC_DEFAULT;
-		if (ints & HAL_INT_GPIO)
-			mask |= SM(AH5416(ah)->ah_gpioMask,
-			    AR_INTR_SYNC_MASK_GPIO);
-		OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask);
-		OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask);
+			mask = AR_INTR_SYNC_DEFAULT;
+			if (ints & HAL_INT_GPIO)
+				mask |= SM(AH5416(ah)->ah_gpioMask,
+				    AR_INTR_SYNC_MASK_GPIO);
+			OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask);
+			OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask);
+		}
 	}
 
 	return omask;
Index: ath_hal/ar5416/ar5416_reset.c
===================================================================
--- ath_hal/ar5416/ar5416_reset.c	(revision 221057)
+++ ath_hal/ar5416/ar5416_reset.c	(working copy)
@@ -145,7 +145,8 @@
 		 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW);
 
 	/* For chips on which the RTC reset is done, save TSF before it gets cleared */
-	if (AR_SREV_MERLIN_20_OR_LATER(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
+	if (AR_SREV_HOWL(ah) ||
+	    (AR_SREV_MERLIN_20_OR_LATER(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)))
 		tsf = ar5212GetTsf64(ah);
 
 	/* Mark PHY as inactive; marked active in ar5416InitBB() */
@@ -184,6 +185,17 @@
 
 	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
 
+	/*
+	 * Some AR91xx SoC devices frequently fail to accept TSF writes
+	 * right after the chip reset. When that happens, write a new
+	 * value after the initvals have been applied, with an offset
+	 * based on measured time difference
+	 */
+	if (AR_SREV_HOWL(ah) && (ar5212GetTsf64(ah) < tsf)) {
+		tsf += 1500;
+		ar5212SetTsf64(ah, tsf);
+	}
+
 	HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n",
 		__func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK));
 	HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n",
@@ -548,14 +560,25 @@
                         | AR_IMR_BCNMISC;
 
 #ifdef	AH_AR5416_INTERRUPT_MITIGATION
-       	ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM
+	ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM
 			|  AR_IMR_TXMINTR | AR_IMR_RXMINTR;
 #else
-        ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK;
+	ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK;
 #endif	
+
 	if (opmode == HAL_M_HOSTAP)
 		ahp->ah_maskReg |= AR_IMR_MIB;
 	OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
+
+#ifdef  ADRIAN_NOTYET
+	/* This is straight from ath9k */
+	if (! AR_SREV_HOWL(ah)) {
+		OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
+		OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
+		OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
+	}
+#endif
+
 	/* Enable bus errors that are OR'd to set the HIUERR bit */
 #if 0
 	OS_REG_WRITE(ah, AR_IMR_S2, 
@@ -1136,11 +1159,14 @@
     /*
      * RTC reset and clear
      */
-    OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
+    if (! AR_SREV_HOWL(ah))
+    	OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
     OS_REG_WRITE(ah, AR_RTC_RESET, 0);
     OS_DELAY(20);
-    OS_REG_WRITE(ah, AR_RC, 0);
 
+    if (! AR_SREV_HOWL(ah))
+    	OS_REG_WRITE(ah, AR_RC, 0);
+
     OS_REG_WRITE(ah, AR_RTC_RESET, 1);
 
     /*
@@ -1158,38 +1184,50 @@
 ar5416SetReset(struct ath_hal *ah, int type)
 {
     uint32_t tmpReg, mask;
+    uint32_t rst_flags;
 
+#ifdef	AH_SUPPORT_AR9130	/* Because of the AR9130 specific registers */
+    if (AR_SREV_HOWL(ah)) {
+        HALDEBUG(ah, HAL_DEBUG_ANY, "[ath] HOWL: Fiddling with derived clk!\n");
+        uint32_t val = OS_REG_READ(ah, AR_RTC_DERIVED_CLK);
+        val &= ~AR_RTC_DERIVED_CLK_PERIOD;
+        val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
+        OS_REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
+        (void) OS_REG_READ(ah, AR_RTC_DERIVED_CLK);
+    }
+#endif	/* AH_SUPPORT_AR9130 */
+
     /*
      * Force wake
      */
     OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
 	AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
 
-    /*
-     * Reset AHB
-     */
-    tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
-    if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
-	OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
-	OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
+#ifdef	AH_SUPPORT_AR9130
+    if (AR_SREV_HOWL(ah)) {
+        rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
+          AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
     } else {
-	OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
+#endif	/* AH_SUPPORT_AR9130 */
+        /*
+         * Reset AHB
+         */
+        tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+        if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
+            OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+            OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
+        } else {
+	    OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
+        }
+        rst_flags = AR_RTC_RC_MAC_WARM;
+        if (type == HAL_RESET_COLD)
+            rst_flags |= AR_RTC_RC_MAC_COLD;
+#ifdef	AH_SUPPORT_AR9130
     }
+#endif	/* AH_SUPPORT_AR9130 */
 
-    /*
-     * Set Mac(BB,Phy) Warm Reset
-     */
-    switch (type) {
-    case HAL_RESET_WARM:
-            OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM);
-            break;
-    case HAL_RESET_COLD:
-            OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD);
-            break;
-    default:
-            HALASSERT(AH_FALSE);
-            break;
-    }
+    OS_REG_WRITE(ah, AR_RTC_RC, rst_flags);
+    OS_DELAY(50);
 
     /*
      * Clear resets and force wakeup
@@ -1201,8 +1239,26 @@
     }
 
     /* Clear AHB reset */
-    OS_REG_WRITE(ah, AR_RC, 0);
+    if (! AR_SREV_HOWL(ah))
+        OS_REG_WRITE(ah, AR_RC, 0);
 
+    if (AR_SREV_HOWL(ah))
+        OS_DELAY(50);
+
+    if (AR_SREV_HOWL(ah)) {
+                uint32_t mask;
+                mask = OS_REG_READ(ah, AR_CFG);
+                if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
+                        HALDEBUG(ah, HAL_DEBUG_RESET,
+                                "CFG Byte Swap Set 0x%x\n", mask);
+                } else {
+                        mask =  
+                                INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
+                        OS_REG_WRITE(ah, AR_CFG, mask);
+                        HALDEBUG(ah, HAL_DEBUG_RESET,
+                                "Setting CFG 0x%x\n", OS_REG_READ(ah, AR_CFG));
+                }
+    } else {
 	if (type == HAL_RESET_COLD) {
 		if (isBigEndian()) {
 			/*
@@ -1219,6 +1275,7 @@
 		} else
 			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
 	}
+    }
 
     AH5416(ah)->ah_initPLL(ah, AH_NULL);
 
@@ -1235,6 +1292,11 @@
 	OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
 	OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
 	OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask);
+
+	if (AR_SREV_HOWL(ah)) {
+		OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
+		OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
+	}
 }
 
 void
@@ -2440,12 +2502,12 @@
 
 	/*
 	 * The AR5416 initvals have this already set to 0x11; AR9160 has
-	 * the register set to 0x0. Figure out whether AR9100/AR9160 needs
+	 * the register set to 0x0. Figure out whether AR9130/AR9160 needs
 	 * this before moving forward with it.
 	 */
 #if 0
-	/* Disable BB clock gating for AR5416v2, AR9100, AR9160 */
-        if (AR_SREV_OWL_20_OR_LATER(ah) || AR_SREV_9100(ah) || AR_SREV_SOWL(ah)) {
+	/* Disable BB clock gating for AR5416v2, AR9130, AR9160 */
+        if (AR_SREV_OWL_20_OR_LATER(ah) || AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) {
 		/*
 		 * Disable BB clock gating
 		 * Necessary to avoid issues on AR5416 2.0
@@ -2458,7 +2520,7 @@
 	 * Disable RIFS search on some chips to avoid baseband
 	 * hang issues.
 	 */
-	if (AR_SREV_9100(ah) || AR_SREV_SOWL(ah)) {
+	if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) {
 		val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
 		val &= ~AR_PHY_RIFS_INIT_DELAY;
 		OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
Index: ath_hal/ar5416/ar5416reg.h
===================================================================
--- ath_hal/ar5416/ar5416reg.h	(revision 221057)
+++ ath_hal/ar5416/ar5416reg.h	(working copy)
@@ -19,6 +19,12 @@
 #ifndef _DEV_ATH_AR5416REG_H
 #define	_DEV_ATH_AR5416REG_H
 
+/* AR9130 shifts these registers */
+#ifdef	AH_SUPPORT_AR9130
+#define	AR_SREV		0x0600
+#define	AR_SREV_ID	0x00000FFF
+#endif
+
 #include <dev/ath/ath_hal/ar5212/ar5212reg.h>
 
 /*
@@ -54,15 +60,30 @@
 #define	AR_GPIO_OUTPUT_MUX3	0x4068
 #define	AR_EEPROM_STATUS_DATA	0x407c
 #define	AR_OBS			0x4080
-#define	AR_RTC_RC		0x7000	/* reset control */
-#define	AR_RTC_PLL_CONTROL	0x7014
-#define	AR_RTC_RESET		0x7040	/* RTC reset register */
-#define	AR_RTC_STATUS		0x7044	/* system sleep status */
-#define	AR_RTC_SLEEP_CLK	0x7048
-#define	AR_RTC_FORCE_WAKE	0x704c	/* control MAC force wake */
-#define	AR_RTC_INTR_CAUSE	0x7050	/* RTC interrupt cause/clear */
-#define	AR_RTC_INTR_ENABLE	0x7054	/* RTC interrupt enable */
-#define	AR_RTC_INTR_MASK	0x7058	/* RTC interrupt mask */
+
+#ifdef	AH_SUPPORT_AR9130
+#define	AR_RTC_BASE		0x20000
+#else
+#define	AR_RTC_BASE		0x7000
+#endif	/* AH_SUPPORT_AR9130 */
+
+#define	AR_RTC_RC		AR_RTC_BASE + 0x00	/* reset control */
+#define	AR_RTC_PLL_CONTROL	AR_RTC_BASE + 0x14
+#define	AR_RTC_RESET		AR_RTC_BASE + 0x40	/* RTC reset register */
+#define	AR_RTC_STATUS		AR_RTC_BASE + 0x44	/* system sleep status */
+#define	AR_RTC_SLEEP_CLK	AR_RTC_BASE + 0x48
+#define	AR_RTC_FORCE_WAKE	AR_RTC_BASE + 0x4c	/* control MAC force wake */
+#define	AR_RTC_INTR_CAUSE	AR_RTC_BASE + 0x50	/* RTC interrupt cause/clear */
+#define	AR_RTC_INTR_ENABLE	AR_RTC_BASE + 0x54	/* RTC interrupt enable */
+#define	AR_RTC_INTR_MASK	AR_RTC_BASE + 0x58	/* RTC interrupt mask */
+
+#ifdef	AH_SUPPORT_AR9130
+/* RTC_DERIVED_* - only for AR9130 */
+#define	AR_RTC_DERIVED_CLK		(AR_RTC_BASE + 0x0038)
+#define	AR_RTC_DERIVED_CLK_PERIOD	0x0000fffe
+#define	AR_RTC_DERIVED_CLK_PERIOD_S	1
+#endif	/* AH_SUPPORT_AR9130 */
+
 /* AR9280: rf long shift registers */
 #define	AR_AN_RF2G1_CH0         0x7810
 #define	AR_AN_RF5G1_CH0         0x7818
@@ -313,6 +334,10 @@
 #define	AR_RTC_RC_M		0x00000003
 #define	AR_RTC_RC_MAC_WARM	0x00000001
 #define	AR_RTC_RC_MAC_COLD	0x00000002
+#ifdef	AH_SUPPORT_AR9130
+#define AR_RTC_RC_COLD_RESET    0x00000004
+#define AR_RTC_RC_WARM_RESET    0x00000008
+#endif	/* AH_SUPPORT_AR9130 */
 #define	AR_RTC_PLL_DIV		0x0000001f
 #define	AR_RTC_PLL_DIV_S	0
 #define	AR_RTC_PLL_DIV2		0x00000020
@@ -328,7 +353,11 @@
 #define	AR_RTC_RESET_EN		0x00000001	/* Reset RTC bit */
 
 #define	AR_RTC_PM_STATUS_M	0x0000000f	/* Pwr Mgmt Status */
+#ifdef	AH_SUPPORT_AR9130
+#define	AR_RTC_STATUS_M		0x0000000f	/* RTC Status */
+#else
 #define	AR_RTC_STATUS_M		0x0000003f	/* RTC Status */
+#endif	/* AH_SUPPORT_AR9130 */
 #define	AR_RTC_STATUS_SHUTDOWN	0x00000001
 #define	AR_RTC_STATUS_ON	0x00000002
 #define	AR_RTC_STATUS_SLEEP	0x00000004
@@ -584,7 +613,7 @@
 #define	AR_XSREV_REVISION_OWL_20	1	/* Owl 2.0/2.1 */
 #define	AR_XSREV_REVISION_OWL_22	2	/* Owl 2.2 */
 #define	AR_XSREV_VERSION_HOWL		0x14	/* Howl (AR9130) */
-#define	AR_XSREV_VERSION_SOWL		0x40
+#define	AR_XSREV_VERSION_SOWL		0x40	/* Sowl (AR9160) */
 #define	AR_XSREV_REVISION_SOWL_10	0	/* Sowl 1.0 */
 #define	AR_XSREV_REVISION_SOWL_11	1	/* Sowl 1.1 */
 #define	AR_XSREV_VERSION_MERLIN		0x80	/* Merlin Version */
@@ -607,6 +636,10 @@
 	((AR_SREV_OWL(_ah) && AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22) || \
 	AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL)
 
+#define AR_SREV_HOWL(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL)
+#define	AR_SREV_9100(_ah)	AR_SREV_HOWL(_ah)
+
 #define	AR_SREV_SOWL(_ah) \
 	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL)
 #define	AR_SREV_SOWL_10_OR_LATER(_ah) \
@@ -649,6 +682,5 @@
 /* Not yet implemented chips */
 #define	AR_SREV_9271(_ah)	0
 #define	AR_SREV_9287_11_OR_LATER(_ah)	0
-#define	AR_SREV_9100(_ah)	0
 
 #endif /* _DEV_ATH_AR5416REG_H */
Index: ath_hal/ar5416/ar5416_misc.c
===================================================================
--- ath_hal/ar5416/ar5416_misc.c	(revision 221057)
+++ ath_hal/ar5416/ar5416_misc.c	(working copy)
@@ -77,6 +77,9 @@
 	};
 	uint32_t bits;
 
+	if (AR_SREV_HOWL(ah))
+		return;
+
 	bits = OS_REG_READ(ah, AR_MAC_LED);
 	bits = (bits &~ AR_MAC_LED_MODE)
 	     | SM(AR_MAC_LED_MODE_POWON, AR_MAC_LED_MODE)
Index: ath_hal/ah_devid.h
===================================================================
--- ath_hal/ah_devid.h	(revision 221057)
+++ ath_hal/ah_devid.h	(working copy)
@@ -74,6 +74,7 @@
 /* AR5416 compatible devid's  */
 #define AR5416_DEVID_PCI	0x0023          /* AR5416 PCI (MB/CB) Owl */
 #define AR5416_DEVID_PCIE	0x0024          /* AR5416 PCI-E (XB) Owl */
+#define	AR5416_AR9130_DEVID     0x000b          /* AR9130 SoC WiMAC */
 #define AR9160_DEVID_PCI	0x0027          /* AR9160 PCI Sowl */
 #define AR9280_DEVID_PCI	0x0029          /* AR9280 PCI Merlin */
 #define AR9280_DEVID_PCIE	0x002a          /* AR9280 PCI-E Merlin */
Index: ath_hal/ah.c
===================================================================
--- ath_hal/ah.c	(revision 221057)
+++ ath_hal/ah.c	(working copy)
@@ -109,6 +109,8 @@
 		return "5416";
 	case AR_XSREV_VERSION_OWL_PCIE:
 		return "5418";
+	case AR_XSREV_VERSION_HOWL:
+		return "9130";
 	case AR_XSREV_VERSION_SOWL:
 		return "9160";
 	case AR_XSREV_VERSION_MERLIN:
Index: ath_hal/ah_eeprom_v14.c
===================================================================
--- ath_hal/ah_eeprom_v14.c	(revision 221057)
+++ ath_hal/ah_eeprom_v14.c	(working copy)
@@ -321,24 +321,36 @@
 {
 #define	NW(a)	(sizeof(a) / sizeof(uint16_t))
 	HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
-	uint16_t *eep_data, magic;
-	HAL_BOOL need_swap;
+	uint16_t *eep_data, magic, magic2 = 0;
+	HAL_BOOL need_swap = 0;
 	u_int w, off, len;
 	uint32_t sum;
 
 	HALASSERT(ee == AH_NULL);
- 
-	if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
-		HALDEBUG(ah, HAL_DEBUG_ANY,
-		    "%s Error reading Eeprom MAGIC\n", __func__);
-		return HAL_EEREAD;
+
+	/* Do we have a private copy of the EEPROM data? Then don't check magic -adrian */
+	if (ah->ah_eepromdata == AH_NULL) {
+		if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s Error reading Eeprom MAGIC\n", __func__);
+			return HAL_EEREAD;
+		}
+		magic2 = __bswap16(magic);
+		HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x; Swapped Magic = 0x%x\n",
+		    __func__, magic, magic2);
+		if (magic != AR5416_EEPROM_MAGIC && magic2 != AR5416_EEPROM_MAGIC) {
+			HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");
+			return HAL_EEMAGIC;
+		}
+
+		/* Do we need to swap the contents? */
+		if (magic2 == AR5416_EEPROM_MAGIC)
+			need_swap = AH_TRUE;
+
+		/* The "old style" swap logic from the HAL - swap if we're on bigendian */
+		if (isBigEndian())
+			need_swap = AH_TRUE;
 	}
-	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",
-	    __func__, magic);
-	if (magic != AR5416_EEPROM_MAGIC) {
-		HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");
-		return HAL_EEMAGIC;
-	}
 
 	ee = ath_hal_malloc(sizeof(HAL_EEPROM_v14));
 	if (ee == AH_NULL) {
@@ -357,19 +369,27 @@
 		}
 	}
 	/* Convert to eeprom native eeprom endian format */
-	if (isBigEndian()) {
+
+        /*
+         * Assume EEPROM "copy" data from a flash device (eg via if_ath_ahb.c) is
+         * already in native byte order and doesn't need to be swapped.
+	 * In this instance, magic2 is 0 and won't trigger the magic check here.
+         */
+	if (need_swap == AH_TRUE) {
+		HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM, "%s: eeprom: swapping eeprom contents for you\n", __func__);
 		for (w = 0; w < NW(struct ar5416eeprom); w++)
 			eep_data[w] = __bswap16(eep_data[w]);
 	}
 
 	/*
 	 * At this point, we're in the native eeprom endian format
-	 * Now, determine the eeprom endian by looking at byte 26??
+	 * Swap length if needed
 	 */
-	need_swap = ((ee->ee_base.baseEepHeader.eepMisc & AR5416_EEPMISC_BIG_ENDIAN) != 0) ^ isBigEndian();
+	printf("need_swap: %d\n", need_swap);
+	HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM, "%s: eeprom: swapsies: %d\n", __func__, need_swap);
 	if (need_swap) {
 		HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
-		    "Byte swap EEPROM contents.\n");
+		    "%s: Byte swap EEPROM contents.\n", __func__);
 		len = __bswap16(ee->ee_base.baseEepHeader.length);
 	} else {
 		len = ee->ee_base.baseEepHeader.length;
Index: ath_hal/ar5212/ar5212reg.h
===================================================================
--- ath_hal/ar5212/ar5212reg.h	(revision 221057)
+++ ath_hal/ar5212/ar5212reg.h	(working copy)
@@ -234,7 +234,9 @@
 #define	AR_GPIOCR	0x4014	/* GPIO control register */
 #define	AR_GPIODO	0x4018	/* GPIO data output access register */
 #define	AR_GPIODI	0x401C	/* GPIO data input access register */
+#if !defined(AR_SREV)
 #define	AR_SREV		0x4020	/* Silicon Revision register */
+#endif
 #define	AR_TXEPOST	0x4028	/* TXE write posting resgister */
 #define	AR_QSM		0x402C	/* QCU sleep mask */
 
@@ -758,7 +760,9 @@
 #define	AR_GPIOCR_INT_SELH	0x00010000 /* Generate int if pin is high */
 #define	AR_GPIOCR_INT_SEL	AR_GPIOCR_INT_SELH
 
+#if !defined(AR_SREV_ID)
 #define	AR_SREV_ID		0x000000FF /* Mask to read SREV info */
+#endif
 #define	AR_SREV_ID_S		4	   /* Mask to shift Major Rev Info */
 #define	AR_SREV_REVISION	0x0000000F /* Mask for Chip revision level */
 #define	AR_SREV_REVISION_MIN	0	   /* lowest revision level */
Index: ath_hal/ar9001/ar9130_phy.c
===================================================================
--- ath_hal/ar9001/ar9130_phy.c	(revision 0)
+++ ath_hal/ar9001/ar9130_phy.c	(revision 0)
@@ -0,0 +1,26 @@
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+#include "ar9001/ar9130_phy.h"
+
+void
+ar9130InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+
+	uint32_t pll;
+
+	if (chan && IEEE80211_IS_CHAN_5GHZ(chan))
+		pll = 0x1450;
+	else
+		pll = 0x1458;
+
+	OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+	OS_DELAY(RTC_PLL_SETTLE_DELAY);
+	OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
+}
Index: ath_hal/ar9001/ar9130_attach.c
===================================================================
--- ath_hal/ar9001/ar9130_attach.c	(revision 0)
+++ ath_hal/ar9001/ar9130_attach.c	(revision 0)
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2010 Adrian Chadd, Xenion Pty Ltd
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+#include "ar9001/ar9130_phy.h"
+#include "ar9001/ar9130_eeprom.h"
+
+#include "ar9001/ar9130.ini"
+
+static const HAL_PERCAL_DATA ar9130_iq_cal = {		/* multi sample */
+	.calName = "IQ", .calType = IQ_MISMATCH_CAL,
+	.calNumSamples	= MAX_CAL_SAMPLES,
+	.calCountMax	= PER_MIN_LOG_COUNT,
+	.calCollect	= ar5416IQCalCollect,
+	.calPostProc	= ar5416IQCalibration
+};
+static const HAL_PERCAL_DATA ar9130_adc_gain_cal = {	/* multi sample */
+	.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
+	.calNumSamples	= MAX_CAL_SAMPLES,
+	.calCountMax	= PER_MIN_LOG_COUNT,
+	.calCollect	= ar5416AdcGainCalCollect,
+	.calPostProc	= ar5416AdcGainCalibration
+};
+static const HAL_PERCAL_DATA ar9130_adc_dc_cal = {	/* multi sample */
+	.calName = "ADC DC", .calType = ADC_DC_CAL,
+	.calNumSamples	= MAX_CAL_SAMPLES,
+	.calCountMax	= PER_MIN_LOG_COUNT,
+	.calCollect	= ar5416AdcDcCalCollect,
+	.calPostProc	= ar5416AdcDcCalibration
+};
+static const HAL_PERCAL_DATA ar9130_adc_init_dc_cal = {
+	.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
+	.calNumSamples	= MIN_CAL_SAMPLES,
+	.calCountMax	= INIT_LOG_COUNT,
+	.calCollect	= ar5416AdcDcCalCollect,
+	.calPostProc	= ar5416AdcDcCalibration
+};
+
+static HAL_BOOL ar9130FillCapabilityInfo(struct ath_hal *ah);
+
+/*
+ * Attach for an AR9130 part.
+ */
+static struct ath_hal *
+ar9130Attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *status)
+{
+	struct ath_hal_5416 *ahp5416;
+	struct ath_hal_5212 *ahp;
+	struct ath_hal *ah;
+	uint32_t val;
+	HAL_STATUS ecode;
+	HAL_BOOL rfStatus;
+
+	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+	    __func__, sc, (void*) st, (void*) sh);
+
+	/* NB: memory is returned zero'd */
+	ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416));
+	if (ahp5416 == AH_NULL) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		    "%s: cannot allocate memory for state block\n", __func__);
+		*status = HAL_ENOMEM;
+		return AH_NULL;
+	}
+	ar5416InitState(ahp5416, devid, sc, st, sh, status);
+	ahp = &ahp5416->ah_5212;
+	ah = &ahp->ah_priv.h;
+
+	/* XXX override with 9100 specific state */
+	AH5416(ah)->ah_initPLL = ar9130InitPLL;
+	/* XXX should force chainmasks to 0x7, as per ath9k calibration bugs */
+
+	/* override 5416 methods for our needs */
+
+	AH5416(ah)->ah_cal.iqCalData.calData = &ar9130_iq_cal;
+	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9130_adc_gain_cal;
+	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9130_adc_dc_cal;
+	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9130_adc_init_dc_cal;
+	AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
+
+	/*
+	 * Hard-set the MAC version here so reset, EEPROM, etc uses the right
+	 * register values where appropriate for the AR9130. Some of them
+	 * have moved. -adrian
+	 */
+	AH_PRIVATE((ah))->ah_macVersion = AR_XSREV_VERSION_HOWL;
+
+	/*
+	 * Use the "local" EEPROM data given to us by the higher layers.
+	 * This is a private copy out of system flash. The Linux ath9k
+	 * commit for the initial AR9100 support mentions MMIO flash
+	 * access is "unreliable." -adrian
+	 */
+	AH_PRIVATE((ah))->ah_eepromRead = ar9130EepromRead;
+	AH_PRIVATE((ah))->ah_eepromWrite = NULL;
+	ah->ah_eepromdata = eepromdata;
+
+	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
+		/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
+		    __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
+		    __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+	/* Read Revisions from Chips before taking out of reset */
+	val = OS_REG_READ(ah, AR_SREV);
+	/* XXX are these values even valid for the mac/radio revision? -adrian */
+	HALDEBUG(ah, HAL_DEBUG_ATTACH,
+	    "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
+	    __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
+	    MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
+	AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
+	AH_PRIVATE(ah)->ah_ispcie = 0;
+
+	/* setup common ini data; rf backends handle remainder */
+	HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes_9100, 6);
+	HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common_9100, 2);
+
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain_9100, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0_9100, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1_9100, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2_9100, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3_9100, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6TPC_9100, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7_9100, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac_9100, 2);
+
+	ecode = ath_hal_v14EepromAttach(ah);
+	if (ecode != HAL_OK)
+		goto bad;
+
+	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+
+	if (!ar5212ChipTest(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+		    __func__);
+		ecode = HAL_ESELFTEST;
+		goto bad;
+	}
+
+	/*
+	 * Set correct Baseband to analog shift
+	 * setting to access analog chips.
+	 */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+	/* Read Radio Chip Rev Extract */
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
+	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
+        case AR_RAD2133_SREV_MAJOR:	/* Sowl: 2G/3x3 */
+	case AR_RAD5133_SREV_MAJOR:	/* Sowl: 2+5G/3x3 */
+		break;
+	default:
+		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
+			AH_PRIVATE(ah)->ah_analog5GhzRev =
+				AR_RAD5133_SREV_MAJOR;
+			break;
+		}
+#ifdef AH_DEBUG
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
+		    "this driver\n", __func__,
+		    AH_PRIVATE(ah)->ah_analog5GhzRev);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+#endif
+	}
+	rfStatus = ar2133RfAttach(ah, &ecode);
+	if (!rfStatus) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
+		    __func__, ecode);
+		goto bad;
+	}
+
+	/*
+	 * Got everything we need now to setup the capabilities.
+	 */
+	if (!ar9130FillCapabilityInfo(ah)) {
+		ecode = HAL_EEREAD;
+		goto bad;
+	}
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error getting mac address from EEPROM\n", __func__);
+		goto bad;
+        }
+	/* XXX How about the serial number ? */
+	/* Read Reg Domain */
+	AH_PRIVATE(ah)->ah_currentRD =
+	    ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
+
+	/*
+	 * ah_miscMode is populated by ar5416FillCapabilityInfo()
+	 * starting from griffin. Set here to make sure that
+	 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
+	 * placed into hardware.
+	 */
+	if (ahp->ah_miscMode != 0)
+		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+
+	/* XXX no ANI for AR9130 */
+	AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
+	AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
+	AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
+	AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
+	AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
+	AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
+
+	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+	return ah;
+bad:
+	if (ahp)
+		ar5416Detach((struct ath_hal *) ahp);
+	if (status)
+		*status = ecode;
+	return AH_NULL;
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ * Return failure if capabilities are to come from EEPROM and
+ * cannot be read.
+ */
+static HAL_BOOL
+ar9130FillCapabilityInfo(struct ath_hal *ah)
+{
+	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: begin\n", __func__);
+	if (!ar5416FillCapabilityInfo(ah))
+		return AH_FALSE;
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: fill'ed; now setting\n", __func__);
+	pCap->halCSTSupport = AH_TRUE;
+	pCap->halRifsRxSupport = AH_TRUE;
+	pCap->halRifsTxSupport = AH_TRUE;
+	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
+	pCap->halExtChanDfsSupport = AH_TRUE;
+	pCap->halAutoSleepSupport = AH_FALSE;	/* XXX? */
+	return AH_TRUE;
+}
+
+static const char*
+ar9130Probe(uint16_t vendorid, uint16_t devid)
+{
+        if (vendorid == ATHEROS_VENDOR_ID && devid == AR5416_AR9130_DEVID)
+                return "Atheros 9130";
+	return AH_NULL;
+}
+AH_CHIP(AR9130, ar9130Probe, ar9130Attach);
Index: ath_hal/ar9001/ar9130_phy.h
===================================================================
--- ath_hal/ar9001/ar9130_phy.h	(revision 0)
+++ ath_hal/ar9001/ar9130_phy.h	(revision 0)
@@ -0,0 +1,6 @@
+#ifndef	__AR9130_PHY_H__
+#define	__AR9130_PHY_H__
+
+extern	void ar9130InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
+
+#endif
Index: ath_hal/ar9001/ar9130_eeprom.c
===================================================================
--- ath_hal/ar9001/ar9130_eeprom.c	(revision 0)
+++ ath_hal/ar9001/ar9130_eeprom.c	(revision 0)
@@ -0,0 +1,25 @@
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar9001/ar9130_eeprom.h"
+
+/* XXX this shouldn't be done here */
+/* This is in 16 bit words; not bytes -adrian */
+#define ATH_DATA_EEPROM_SIZE    2048
+
+HAL_BOOL
+ar9130EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
+{
+	if (ah->ah_eepromdata == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: no eeprom data!\n", __func__);
+		return AH_FALSE;
+	}
+	if (off > ATH_DATA_EEPROM_SIZE) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "ar9130EepromRead: offset %x > %x\n", off, ATH_DATA_EEPROM_SIZE);
+		return AH_FALSE;
+	}
+	(*data) = ah->ah_eepromdata[off];
+	return AH_TRUE;
+}
Index: ath_hal/ar9001/ar9130_eeprom.h
===================================================================
--- ath_hal/ar9001/ar9130_eeprom.h	(revision 0)
+++ ath_hal/ar9001/ar9130_eeprom.h	(revision 0)
@@ -0,0 +1,6 @@
+#ifndef	__AR9130_EEPROM_H__
+#define	__AR9130_EEPROM_H__
+
+extern	HAL_BOOL ar9130EepromRead(struct ath_hal *ah, u_int off, uint16_t *data);
+
+#endif
Index: ath_hal/ar9001/ar9130.ini
===================================================================
--- ath_hal/ar9001/ar9130.ini	(revision 0)
+++ ath_hal/ar9001/ar9130.ini	(revision 0)
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+static const uint32_t ar5416Modes_9100[][6] = {
+    { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
+    { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
+    { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
+    { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
+    { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
+    { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
+    { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
+    { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
+    { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
+    { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
+    { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
+    { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
+    { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x00009850, 0x6c48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
+    { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
+    { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
+    { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
+    { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+    { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
+    { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
+    { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
+    { 0x00009940, 0x00750604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
+    { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
+    { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
+    { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
+    { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
+    { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
+    { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
+    { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
+    { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
+    { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
+    { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
+    { 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 },
+    { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
+    { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
+    { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
+    { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
+    { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
+    { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
+    { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
+    { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
+    { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
+    { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
+    { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
+    { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
+    { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
+    { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
+    { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
+    { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
+    { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
+    { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
+static const uint32_t ar5416Common_9100[][2] = {
+    /* Addr      allmodes  */
+    { 0x0000000c, 0x00000000 },
+    { 0x00000030, 0x00020015 },
+    { 0x00000034, 0x00000005 },
+    { 0x00000040, 0x00000000 },
+    { 0x00000044, 0x00000008 },
+    { 0x00000048, 0x00000008 },
+    { 0x0000004c, 0x00000010 },
+    { 0x00000050, 0x00000000 },
+    { 0x00000054, 0x0000001f },
+    { 0x00000800, 0x00000000 },
+    { 0x00000804, 0x00000000 },
+    { 0x00000808, 0x00000000 },
+    { 0x0000080c, 0x00000000 },
+    { 0x00000810, 0x00000000 },
+    { 0x00000814, 0x00000000 },
+    { 0x00000818, 0x00000000 },
+    { 0x0000081c, 0x00000000 },
+    { 0x00000820, 0x00000000 },
+    { 0x00000824, 0x00000000 },
+    { 0x00001040, 0x002ffc0f },
+    { 0x00001044, 0x002ffc0f },
+    { 0x00001048, 0x002ffc0f },
+    { 0x0000104c, 0x002ffc0f },
+    { 0x00001050, 0x002ffc0f },
+    { 0x00001054, 0x002ffc0f },
+    { 0x00001058, 0x002ffc0f },
+    { 0x0000105c, 0x002ffc0f },
+    { 0x00001060, 0x002ffc0f },
+    { 0x00001064, 0x002ffc0f },
+    { 0x00001230, 0x00000000 },
+    { 0x00001270, 0x00000000 },
+    { 0x00001038, 0x00000000 },
+    { 0x00001078, 0x00000000 },
+    { 0x000010b8, 0x00000000 },
+    { 0x000010f8, 0x00000000 },
+    { 0x00001138, 0x00000000 },
+    { 0x00001178, 0x00000000 },
+    { 0x000011b8, 0x00000000 },
+    { 0x000011f8, 0x00000000 },
+    { 0x00001238, 0x00000000 },
+    { 0x00001278, 0x00000000 },
+    { 0x000012b8, 0x00000000 },
+    { 0x000012f8, 0x00000000 },
+    { 0x00001338, 0x00000000 },
+    { 0x00001378, 0x00000000 },
+    { 0x000013b8, 0x00000000 },
+    { 0x000013f8, 0x00000000 },
+    { 0x00001438, 0x00000000 },
+    { 0x00001478, 0x00000000 },
+    { 0x000014b8, 0x00000000 },
+    { 0x000014f8, 0x00000000 },
+    { 0x00001538, 0x00000000 },
+    { 0x00001578, 0x00000000 },
+    { 0x000015b8, 0x00000000 },
+    { 0x000015f8, 0x00000000 },
+    { 0x00001638, 0x00000000 },
+    { 0x00001678, 0x00000000 },
+    { 0x000016b8, 0x00000000 },
+    { 0x000016f8, 0x00000000 },
+    { 0x00001738, 0x00000000 },
+    { 0x00001778, 0x00000000 },
+    { 0x000017b8, 0x00000000 },
+    { 0x000017f8, 0x00000000 },
+    { 0x0000103c, 0x00000000 },
+    { 0x0000107c, 0x00000000 },
+    { 0x000010bc, 0x00000000 },
+    { 0x000010fc, 0x00000000 },
+    { 0x0000113c, 0x00000000 },
+    { 0x0000117c, 0x00000000 },
+    { 0x000011bc, 0x00000000 },
+    { 0x000011fc, 0x00000000 },
+    { 0x0000123c, 0x00000000 },
+    { 0x0000127c, 0x00000000 },
+    { 0x000012bc, 0x00000000 },
+    { 0x000012fc, 0x00000000 },
+    { 0x0000133c, 0x00000000 },
+    { 0x0000137c, 0x00000000 },
+    { 0x000013bc, 0x00000000 },
+    { 0x000013fc, 0x00000000 },
+    { 0x0000143c, 0x00000000 },
+    { 0x0000147c, 0x00000000 },
+    { 0x00020010, 0x00000003 },
+    { 0x00020038, 0x000004c2 },
+    { 0x00008004, 0x00000000 },
+    { 0x00008008, 0x00000000 },
+    { 0x0000800c, 0x00000000 },
+    { 0x00008018, 0x00000700 },
+    { 0x00008020, 0x00000000 },
+    { 0x00008038, 0x00000000 },
+    { 0x0000803c, 0x00000000 },
+    { 0x00008048, 0x40000000 },
+    { 0x00008054, 0x00004000 },
+    { 0x00008058, 0x00000000 },
+    { 0x0000805c, 0x000fc78f },
+    { 0x00008060, 0x0000000f },
+    { 0x00008064, 0x00000000 },
+    { 0x000080c0, 0x2a82301a },
+    { 0x000080c4, 0x05dc01e0 },
+    { 0x000080c8, 0x1f402710 },
+    { 0x000080cc, 0x01f40000 },
+    { 0x000080d0, 0x00001e00 },
+    { 0x000080d4, 0x00000000 },
+    { 0x000080d8, 0x00400000 },
+    { 0x000080e0, 0xffffffff },
+    { 0x000080e4, 0x0000ffff },
+    { 0x000080e8, 0x003f3f3f },
+    { 0x000080ec, 0x00000000 },
+    { 0x000080f0, 0x00000000 },
+    { 0x000080f4, 0x00000000 },
+    { 0x000080f8, 0x00000000 },
+    { 0x000080fc, 0x00020000 },
+    { 0x00008100, 0x00020000 },
+    { 0x00008104, 0x00000001 },
+    { 0x00008108, 0x00000052 },
+    { 0x0000810c, 0x00000000 },
+    { 0x00008110, 0x00000168 },
+    { 0x00008118, 0x000100aa },
+    { 0x0000811c, 0x00003210 },
+    { 0x00008120, 0x08f04800 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008144, 0x00000000 },
+    { 0x00008168, 0x00000000 },
+    { 0x0000816c, 0x00000000 },
+    { 0x00008170, 0x32143320 },
+    { 0x00008174, 0xfaa4fa50 },
+    { 0x00008178, 0x00000100 },
+    { 0x0000817c, 0x00000000 },
+    { 0x000081c4, 0x00000000 },
+    { 0x000081d0, 0x00003210 },
+    { 0x000081ec, 0x00000000 },
+    { 0x000081f0, 0x00000000 },
+    { 0x000081f4, 0x00000000 },
+    { 0x000081f8, 0x00000000 },
+    { 0x000081fc, 0x00000000 },
+    { 0x00008200, 0x00000000 },
+    { 0x00008204, 0x00000000 },
+    { 0x00008208, 0x00000000 },
+    { 0x0000820c, 0x00000000 },
+    { 0x00008210, 0x00000000 },
+    { 0x00008214, 0x00000000 },
+    { 0x00008218, 0x00000000 },
+    { 0x0000821c, 0x00000000 },
+    { 0x00008220, 0x00000000 },
+    { 0x00008224, 0x00000000 },
+    { 0x00008228, 0x00000000 },
+    { 0x0000822c, 0x00000000 },
+    { 0x00008230, 0x00000000 },
+    { 0x00008234, 0x00000000 },
+    { 0x00008238, 0x00000000 },
+    { 0x0000823c, 0x00000000 },
+    { 0x00008240, 0x00100000 },
+    { 0x00008244, 0x0010f400 },
+    { 0x00008248, 0x00000100 },
+    { 0x0000824c, 0x0001e800 },
+    { 0x00008250, 0x00000000 },
+    { 0x00008254, 0x00000000 },
+    { 0x00008258, 0x00000000 },
+    { 0x0000825c, 0x400000ff },
+    { 0x00008260, 0x00080922 },
+    { 0x00008270, 0x00000000 },
+    { 0x00008274, 0x40000000 },
+    { 0x00008278, 0x003e4180 },
+    { 0x0000827c, 0x00000000 },
+    { 0x00008284, 0x0000002c },
+    { 0x00008288, 0x0000002c },
+    { 0x0000828c, 0x00000000 },
+    { 0x00008294, 0x00000000 },
+    { 0x00008298, 0x00000000 },
+    { 0x00008300, 0x00000000 },
+    { 0x00008304, 0x00000000 },
+    { 0x00008308, 0x00000000 },
+    { 0x0000830c, 0x00000000 },
+    { 0x00008310, 0x00000000 },
+    { 0x00008314, 0x00000000 },
+    { 0x00008318, 0x00000000 },
+    { 0x00008328, 0x00000000 },
+    { 0x0000832c, 0x00000007 },
+    { 0x00008330, 0x00000302 },
+    { 0x00008334, 0x00000e00 },
+    { 0x00008338, 0x00000000 },
+    { 0x0000833c, 0x00000000 },
+    { 0x00008340, 0x000107ff },
+    { 0x00009808, 0x00000000 },
+    { 0x0000980c, 0xad848e19 },
+    { 0x00009810, 0x7d14e000 },
+    { 0x00009814, 0x9c0a9f6b },
+    { 0x0000981c, 0x00000000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x00009830, 0x00000000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x00009840, 0x206a01ae },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009854, 0x00000859 },
+    { 0x00009900, 0x00000000 },
+    { 0x00009904, 0x00000000 },
+    { 0x00009908, 0x00000000 },
+    { 0x0000990c, 0x00000000 },
+    { 0x0000991c, 0x10000fff },
+    { 0x00009920, 0x05100000 },
+    { 0x0000a920, 0x05100000 },
+    { 0x0000b920, 0x05100000 },
+    { 0x00009928, 0x00000001 },
+    { 0x0000992c, 0x00000004 },
+    { 0x00009934, 0x1e1f2022 },
+    { 0x00009938, 0x0a0b0c0d },
+    { 0x0000993c, 0x00000000 },
+    { 0x00009948, 0x9280b212 },
+    { 0x0000994c, 0x00020028 },
+    { 0x0000c95c, 0x004b6a8e },
+    { 0x0000c968, 0x000003ce },
+    { 0x00009970, 0x190fb515 },
+    { 0x00009974, 0x00000000 },
+    { 0x00009978, 0x00000001 },
+    { 0x0000997c, 0x00000000 },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x00000000 },
+    { 0x00009988, 0x00000000 },
+    { 0x0000998c, 0x00000000 },
+    { 0x00009990, 0x00000000 },
+    { 0x00009994, 0x00000000 },
+    { 0x00009998, 0x00000000 },
+    { 0x0000999c, 0x00000000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099a4, 0x00000001 },
+    { 0x000099a8, 0x201fff00 },
+    { 0x000099ac, 0x006f0000 },
+    { 0x000099b0, 0x03051000 },
+    { 0x000099dc, 0x00000000 },
+    { 0x000099e0, 0x00000200 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x0cc80caa },
+    { 0x000099fc, 0x00001042 },
+    { 0x00009b00, 0x00000000 },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b28, 0x0000000c },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b38, 0x00000012 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b64, 0x00000021 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b8c, 0x0000002d },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009b9c, 0x00000033 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+    { 0x0000a210, 0x40806333 },
+    { 0x0000a214, 0x00106c10 },
+    { 0x0000a218, 0x009c4060 },
+    { 0x0000a220, 0x018830c6 },
+    { 0x0000a224, 0x00000400 },
+    { 0x0000a228, 0x001a0bb5 },
+    { 0x0000a22c, 0x00000000 },
+    { 0x0000a234, 0x20202020 },
+    { 0x0000a238, 0x20202020 },
+    { 0x0000a23c, 0x13c889af },
+    { 0x0000a240, 0x38490a20 },
+    { 0x0000a244, 0x00007bb6 },
+    { 0x0000a248, 0x0fff3ffc },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000e000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0xdfa91f01 },
+    { 0x0000a268, 0x00000001 },
+    { 0x0000a26c, 0x0ebae9c6 },
+    { 0x0000b26c, 0x0ebae9c6 },
+    { 0x0000c26c, 0x0ebae9c6 },
+    { 0x0000d270, 0x00820820 },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x050701ce },
+    { 0x0000a338, 0x00000000 },
+    { 0x0000a33c, 0x00000000 },
+    { 0x0000a340, 0x00000000 },
+    { 0x0000a344, 0x00000000 },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa33 },
+    { 0x0000d35c, 0x07ffffef },
+    { 0x0000d360, 0x0fffffe7 },
+    { 0x0000d364, 0x17ffffe5 },
+    { 0x0000d368, 0x1fffffe4 },
+    { 0x0000d36c, 0x37ffffe3 },
+    { 0x0000d370, 0x3fffffe3 },
+    { 0x0000d374, 0x57ffffe3 },
+    { 0x0000d378, 0x5fffffe2 },
+    { 0x0000d37c, 0x7fffffe2 },
+    { 0x0000d380, 0x7f3c7bba },
+    { 0x0000d384, 0xf3307ff0 },
+    { 0x0000a388, 0x0c000000 },
+    { 0x0000a38c, 0x20202020 },
+    { 0x0000a390, 0x20202020 },
+    { 0x0000a394, 0x1ce739ce },
+    { 0x0000a398, 0x000001ce },
+    { 0x0000a39c, 0x00000001 },
+    { 0x0000a3a0, 0x00000000 },
+    { 0x0000a3a4, 0x00000000 },
+    { 0x0000a3a8, 0x00000000 },
+    { 0x0000a3ac, 0x00000000 },
+    { 0x0000a3b0, 0x00000000 },
+    { 0x0000a3b4, 0x00000000 },
+    { 0x0000a3b8, 0x00000000 },
+    { 0x0000a3bc, 0x00000000 },
+    { 0x0000a3c0, 0x00000000 },
+    { 0x0000a3c4, 0x00000000 },
+    { 0x0000a3c8, 0x00000246 },
+    { 0x0000a3cc, 0x20202020 },
+    { 0x0000a3d0, 0x20202020 },
+    { 0x0000a3d4, 0x20202020 },
+    { 0x0000a3dc, 0x1ce739ce },
+    { 0x0000a3e0, 0x000001ce },
+};
+
+static const uint32_t ar5416Bank0_9100[][2] = {
+    /* Addr      allmodes  */
+    { 0x000098b0, 0x1e5795e5 },
+    { 0x000098e0, 0x02008020 },
+};
+
+static const uint32_t ar5416BB_RfGain_9100[][3] = {
+    /* Addr      5G_HT20     5G_HT40   */
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000040, 0x00000040 },
+    { 0x00009a08, 0x00000080, 0x00000080 },
+    { 0x00009a0c, 0x000001a1, 0x00000141 },
+    { 0x00009a10, 0x000001e1, 0x00000181 },
+    { 0x00009a14, 0x00000021, 0x000001c1 },
+    { 0x00009a18, 0x00000061, 0x00000001 },
+    { 0x00009a1c, 0x00000168, 0x00000041 },
+    { 0x00009a20, 0x000001a8, 0x000001a8 },
+    { 0x00009a24, 0x000001e8, 0x000001e8 },
+    { 0x00009a28, 0x00000028, 0x00000028 },
+    { 0x00009a2c, 0x00000068, 0x00000068 },
+    { 0x00009a30, 0x00000189, 0x000000a8 },
+    { 0x00009a34, 0x000001c9, 0x00000169 },
+    { 0x00009a38, 0x00000009, 0x000001a9 },
+    { 0x00009a3c, 0x00000049, 0x000001e9 },
+    { 0x00009a40, 0x00000089, 0x00000029 },
+    { 0x00009a44, 0x00000170, 0x00000069 },
+    { 0x00009a48, 0x000001b0, 0x00000190 },
+    { 0x00009a4c, 0x000001f0, 0x000001d0 },
+    { 0x00009a50, 0x00000030, 0x00000010 },
+    { 0x00009a54, 0x00000070, 0x00000050 },
+    { 0x00009a58, 0x00000191, 0x00000090 },
+    { 0x00009a5c, 0x000001d1, 0x00000151 },
+    { 0x00009a60, 0x00000011, 0x00000191 },
+    { 0x00009a64, 0x00000051, 0x000001d1 },
+    { 0x00009a68, 0x00000091, 0x00000011 },
+    { 0x00009a6c, 0x000001b8, 0x00000051 },
+    { 0x00009a70, 0x000001f8, 0x00000198 },
+    { 0x00009a74, 0x00000038, 0x000001d8 },
+    { 0x00009a78, 0x00000078, 0x00000018 },
+    { 0x00009a7c, 0x00000199, 0x00000058 },
+    { 0x00009a80, 0x000001d9, 0x00000098 },
+    { 0x00009a84, 0x00000019, 0x00000159 },
+    { 0x00009a88, 0x00000059, 0x00000199 },
+    { 0x00009a8c, 0x00000099, 0x000001d9 },
+    { 0x00009a90, 0x000000d9, 0x00000019 },
+    { 0x00009a94, 0x000000f9, 0x00000059 },
+    { 0x00009a98, 0x000000f9, 0x00000099 },
+    { 0x00009a9c, 0x000000f9, 0x000000d9 },
+    { 0x00009aa0, 0x000000f9, 0x000000f9 },
+    { 0x00009aa4, 0x000000f9, 0x000000f9 },
+    { 0x00009aa8, 0x000000f9, 0x000000f9 },
+    { 0x00009aac, 0x000000f9, 0x000000f9 },
+    { 0x00009ab0, 0x000000f9, 0x000000f9 },
+    { 0x00009ab4, 0x000000f9, 0x000000f9 },
+    { 0x00009ab8, 0x000000f9, 0x000000f9 },
+    { 0x00009abc, 0x000000f9, 0x000000f9 },
+    { 0x00009ac0, 0x000000f9, 0x000000f9 },
+    { 0x00009ac4, 0x000000f9, 0x000000f9 },
+    { 0x00009ac8, 0x000000f9, 0x000000f9 },
+    { 0x00009acc, 0x000000f9, 0x000000f9 },
+    { 0x00009ad0, 0x000000f9, 0x000000f9 },
+    { 0x00009ad4, 0x000000f9, 0x000000f9 },
+    { 0x00009ad8, 0x000000f9, 0x000000f9 },
+    { 0x00009adc, 0x000000f9, 0x000000f9 },
+    { 0x00009ae0, 0x000000f9, 0x000000f9 },
+    { 0x00009ae4, 0x000000f9, 0x000000f9 },
+    { 0x00009ae8, 0x000000f9, 0x000000f9 },
+    { 0x00009aec, 0x000000f9, 0x000000f9 },
+    { 0x00009af0, 0x000000f9, 0x000000f9 },
+    { 0x00009af4, 0x000000f9, 0x000000f9 },
+    { 0x00009af8, 0x000000f9, 0x000000f9 },
+    { 0x00009afc, 0x000000f9, 0x000000f9 },
+};
+
+static const uint32_t ar5416Bank1_9100[][2] = {
+    /* Addr      allmodes  */
+    { 0x000098b0, 0x02108421 },
+    { 0x000098ec, 0x00000008 },
+};
+
+static const uint32_t ar5416Bank2_9100[][2] = {
+    /* Addr      allmodes  */
+    { 0x000098b0, 0x0e73ff17 },
+    { 0x000098e0, 0x00000420 },
+};
+
+static const uint32_t ar5416Bank3_9100[][3] = {
+    /* Addr      5G_HT20     5G_HT40   */
+    { 0x000098f0, 0x01400018, 0x01c00018 },
+};
+
+static const uint32_t ar5416Bank6_9100[][3] = {
+    /* Addr      5G_HT20     5G_HT40   */
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00e00000, 0x00e00000 },
+    { 0x0000989c, 0x005e0000, 0x005e0000 },
+    { 0x0000989c, 0x00120000, 0x00120000 },
+    { 0x0000989c, 0x00620000, 0x00620000 },
+    { 0x0000989c, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x005f0000, 0x005f0000 },
+    { 0x0000989c, 0x00870000, 0x00870000 },
+    { 0x0000989c, 0x00f90000, 0x00f90000 },
+    { 0x0000989c, 0x007b0000, 0x007b0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00f50000, 0x00f50000 },
+    { 0x0000989c, 0x00dc0000, 0x00dc0000 },
+    { 0x0000989c, 0x00110000, 0x00110000 },
+    { 0x0000989c, 0x006100a8, 0x006100a8 },
+    { 0x0000989c, 0x004210a2, 0x004210a2 },
+    { 0x0000989c, 0x0014000f, 0x0014000f },
+    { 0x0000989c, 0x00c40002, 0x00c40002 },
+    { 0x0000989c, 0x003000f2, 0x003000f2 },
+    { 0x0000989c, 0x00440016, 0x00440016 },
+    { 0x0000989c, 0x00410040, 0x00410040 },
+    { 0x0000989c, 0x000180d6, 0x000180d6 },
+    { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
+    { 0x0000989c, 0x000000b1, 0x000000b1 },
+    { 0x0000989c, 0x00002000, 0x00002000 },
+    { 0x0000989c, 0x000000d4, 0x000000d4 },
+    { 0x000098d0, 0x0000000f, 0x0010000f },
+};
+
+static const uint32_t ar5416Bank6TPC_9100[][3] = {
+    /* Addr      5G_HT20     5G_HT40   */
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00e00000, 0x00e00000 },
+    { 0x0000989c, 0x005e0000, 0x005e0000 },
+    { 0x0000989c, 0x00120000, 0x00120000 },
+    { 0x0000989c, 0x00620000, 0x00620000 },
+    { 0x0000989c, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x40ff0000, 0x40ff0000 },
+    { 0x0000989c, 0x005f0000, 0x005f0000 },
+    { 0x0000989c, 0x00870000, 0x00870000 },
+    { 0x0000989c, 0x00f90000, 0x00f90000 },
+    { 0x0000989c, 0x007b0000, 0x007b0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00f50000, 0x00f50000 },
+    { 0x0000989c, 0x00dc0000, 0x00dc0000 },
+    { 0x0000989c, 0x00110000, 0x00110000 },
+    { 0x0000989c, 0x006100a8, 0x006100a8 },
+    { 0x0000989c, 0x00423022, 0x00423022 },
+    { 0x0000989c, 0x2014008f, 0x2014008f },
+    { 0x0000989c, 0x00c40002, 0x00c40002 },
+    { 0x0000989c, 0x003000f2, 0x003000f2 },
+    { 0x0000989c, 0x00440016, 0x00440016 },
+    { 0x0000989c, 0x00410040, 0x00410040 },
+    { 0x0000989c, 0x0001805e, 0x0001805e },
+    { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
+    { 0x0000989c, 0x000000e1, 0x000000e1 },
+    { 0x0000989c, 0x00007080, 0x00007080 },
+    { 0x0000989c, 0x000000d4, 0x000000d4 },
+    { 0x000098d0, 0x0000000f, 0x0010000f },
+};
+
+static const uint32_t ar5416Bank7_9100[][2] = {
+    /* Addr      allmodes  */
+    { 0x0000989c, 0x00000500 },
+    { 0x0000989c, 0x00000800 },
+    { 0x000098cc, 0x0000000e },
+};
+
+static const uint32_t ar5416Addac_9100[][2] = {
+    /* Addr      allmodes  */
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000010 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x000000c0 },
+    { 0x0000989c, 0x00000015 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x0000989c, 0x00000000 },
+    { 0x000098cc, 0x00000000 },
+};