Index: sys/mips/conf/AR934X_BASE =================================================================== --- sys/mips/conf/AR934X_BASE (revision 0) +++ sys/mips/conf/AR934X_BASE (working copy) @@ -0,0 +1,124 @@ +# +# AR91XX -- Kernel configuration base file for the Atheros AR913x SoC. +# +# This file (and the hints file accompanying it) are not designed to be +# used by themselves. Instead, users of this file should create a kernel +# config file which includes this file (which gets the basic hints), then +# override the default options (adding devices as needed) and adding +# hints as needed (for example, the GPIO and LAN PHY.) +# +# $FreeBSD$ +# + +machine mips mips +ident AR934X_BASE +cpu CPU_MIPS4KC +makeoptions KERNLOADADDR=0x80050000 +options HZ=1000 + +files "../atheros/files.ar71xx" +hints "AR934X_BASE.hints" + +makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols +# makeoptions MODULES_OVERRIDE="random gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc" +makeoptions MODULES_OVERRIDE="" + +options DDB +options KDB +options ALQ + +options SCHED_4BSD #4BSD scheduler +options INET #InterNETworking +#options INET6 #InterNETworking +#options NFSCL #Network Filesystem Client +options PSEUDOFS #Pseudo-filesystem framework +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions + +# Don't include the SCSI/CAM strings in the default build +options SCSI_NO_SENSE_STRINGS +options SCSI_NO_OP_STRINGS + +# .. And no sysctl strings +options NO_SYSCTL_DESCR + +# Limit IO size +options NBUF=128 + +# Limit UMTX hash size +# options UMTX_NUM_CHAINS=64 + +# PMC +#options HWPMC_HOOKS +#device hwpmc +#device hwpmc_mips24k + +# options NFS_LEGACYRPC +# Debugging for use in -current +#options INVARIANTS +#options INVARIANT_SUPPORT +#options WITNESS +#options WITNESS_SKIPSPIN +options FFS #Berkeley Fast Filesystem +#options SOFTUPDATES #Enable FFS soft updates support +#options UFS_ACL #Support for access control lists +#options UFS_DIRHASH #Improve performance on big directories +options NO_FFS_SNAPSHOT # We don't require snapshot support + +# Wireless NIC cards +options IEEE80211_DEBUG +options IEEE80211_SUPPORT_MESH +options IEEE80211_SUPPORT_TDMA +options IEEE80211_SUPPORT_SUPERG +options IEEE80211_ALQ # 802.11 ALQ logging support +device wlan # 802.11 support +device wlan_wep # 802.11 WEP support +device wlan_ccmp # 802.11 CCMP support +device wlan_tkip # 802.11 TKIP support +device wlan_xauth # 802.11 hostap support + +# ath(4) +device ath # Atheros network device +device ath_rate_sample +device ath_ahb # Atheros host bus glue +options ATH_DEBUG +options ATH_DIAGAPI +option ATH_ENABLE_11N +option AH_DEBUG_ALQ + +#device ath_hal +device ath_ar9300 # AR9330 HAL; no need for the others +option AH_DEBUG +option AH_SUPPORT_AR5416 # 11n HAL support +option AH_SUPPORT_AR9340 # Chipset support +option AH_DEBUG_ALQ +option AH_AR5416_INTERRUPT_MITIGATION + +device mii +device arge + +device usb +options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order +options USB_DEBUG +options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this +device ehci + +device scbus +device umass +device da + +device spibus +device ar71xx_spi +device mx25l +device ar71xx_wdog + +device uart +device uart_ar71xx + +device loop +device ether +device md +device bpf +device random +device if_bridge +device gpio +device gpioled Property changes on: sys/mips/conf/AR934X_BASE ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Index: sys/mips/conf/AR934X_BASE.hints =================================================================== --- sys/mips/conf/AR934X_BASE.hints (revision 0) +++ sys/mips/conf/AR934X_BASE.hints (working copy) @@ -0,0 +1,61 @@ +# This file (and the kernel config file accompanying it) are not designed +# to be used by themselves. Instead, users of this file should create a +# kernel # config file which includes this file (which gets the basic hints), +# then override the default options (adding devices as needed) and adding +# hints as needed (for example, the GPIO and LAN PHY.) + +# $FreeBSD$ + +hint.apb.0.at="nexus0" +hint.apb.0.irq=4 + +# uart0 +hint.uart.0.at="apb0" +# NB: This isn't an ns8250 UART +hint.uart.0.maddr=0x18020003 +hint.uart.0.msize=0x18 +hint.uart.0.irq=3 + +#ehci - note the 0x100 offset for the AR913x/AR724x +hint.ehci.0.at="nexus0" +hint.ehci.0.maddr=0x1b000100 +hint.ehci.0.msize=0x00001000 +hint.ehci.0.irq=1 + +hint.arge.0.at="nexus0" +hint.arge.0.maddr=0x19000000 +hint.arge.0.msize=0x1000 +hint.arge.0.irq=2 + +hint.arge.1.at="nexus0" +hint.arge.1.maddr=0x1a000000 +hint.arge.1.msize=0x1000 +hint.arge.1.irq=3 + +# XXX The ath device hangs off of the AHB, rather than the Nexus. +hint.ath.0.at="nexus0" +hint.ath.0.maddr=0x18100000 +hint.ath.0.msize=0x20000 +hint.ath.0.irq=0 +hint.ath.0.vendor_id=0x168c +hint.ath.0.device_id=0x0031 +# Set this to define where the ath calibration data +# should be fetched from in physical memory. +# hint.ath.0.eepromaddr=0x1fff1000 + +# SPI flash +hint.spi.0.at="nexus0" +hint.spi.0.maddr=0x1f000000 +hint.spi.0.msize=0x10 + +hint.mx25l.0.at="spibus0" +hint.mx25l.0.cs=0 + +# Watchdog +hint.ar71xx_wdog.0.at="nexus0" + +# The GPIO function and pin mask is configured per-board +hint.gpio.0.at="apb0" +hint.gpio.0.maddr=0x18040000 +hint.gpio.0.msize=0x1000 +hint.gpio.0.irq=2 Property changes on: sys/mips/conf/AR934X_BASE.hints ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Index: sys/mips/conf/DB120 =================================================================== --- sys/mips/conf/DB120 (revision 0) +++ sys/mips/conf/DB120 (working copy) @@ -0,0 +1,46 @@ +# +# DB120 - the AR9344 SoC reference design +# +# $FreeBSD$ +# + +# Include the default AR934x parameters +include "AR934X_BASE" + +ident DB120 + +# Override hints with board values +hints "DB120.hints" + +# Force the board memory - the base DB120 has 128MB RAM +options AR71XX_REALMEM=(32*1024*1024) + +# i2c GPIO bus +#device gpioiic +#device iicbb +#device iicbus +#device iic + +# Options required for miiproxy and mdiobus +options ARGE_MDIO # Export an MDIO bus separate from arge +device miiproxy # MDIO bus <-> MII PHY rendezvous + +device etherswitch +device arswitch + +# read MSDOS formatted disks - USB +#options MSDOSFS + +# Enable the uboot environment stuff rather then the +# redboot stuff. +options AR71XX_ENV_UBOOT + +# uzip - to boot natively from flash +device geom_uncompress +options GEOM_UNCOMPRESS + +# Used for the static uboot partition map +device geom_map + +# Boot off of the rootfs, as defined in the geom_map setup. +options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\" Property changes on: sys/mips/conf/DB120 ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Index: sys/mips/conf/DB120.hints =================================================================== Property changes on: sys/mips/conf/DB120.hints ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Index: sys/mips/atheros/files.ar71xx =================================================================== --- sys/mips/atheros/files.ar71xx (revision 253313) +++ sys/mips/atheros/files.ar71xx (working copy) @@ -25,6 +25,7 @@ mips/atheros/ar724x_chip.c standard mips/atheros/ar91xx_chip.c standard mips/atheros/ar933x_chip.c standard +mips/atheros/ar934x_chip.c standard mips/atheros/ar71xx_fixup.c optional ar71xx_ath_eeprom dev/hwpmc/hwpmc_mips24k.c optional hwpmc_mips24k Index: sys/mips/atheros/uart_cpu_ar71xx.c =================================================================== --- sys/mips/atheros/uart_cpu_ar71xx.c (revision 253313) +++ sys/mips/atheros/uart_cpu_ar71xx.c (working copy) @@ -56,7 +56,7 @@ { uint64_t freq; - freq = ar71xx_ahb_freq(); + freq = ar71xx_uart_freq(); di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; Index: sys/mips/atheros/ar933x_chip.c =================================================================== --- sys/mips/atheros/ar933x_chip.c (revision 253313) +++ sys/mips/atheros/ar933x_chip.c (working copy) @@ -114,6 +114,10 @@ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; u_ar71xx_ahb_freq = freq / t; } + + /* XXX uart should be the refclk, no? */ + u_ar71xx_uart_freq = u_ar71xx_ahb_freq; + u_ar71xx_wdt_freq = u_ar71xx_ahb_freq; } static void Index: sys/mips/atheros/ar934x_chip.c =================================================================== --- sys/mips/atheros/ar934x_chip.c (revision 0) +++ sys/mips/atheros/ar934x_chip.c (working copy) @@ -0,0 +1,333 @@ +/*- + * Copyright (c) 2013 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +static void +ar934x_chip_detect_mem_size(void) +{ +} + +static uint32_t +ar934x_get_pll_freq(uint32_t ref, uint32_t ref_div, uint32_t nint, + uint32_t nfrac, uint32_t frac, uint32_t out_div) +{ + uint64_t t; + uint32_t ret; + + t = u_ar71xx_refclk; + t *= nint; + t = t / ref_div; + ret = t; + + t = u_ar71xx_refclk; + t *= nfrac; + t = t / (ref_div * frac); + ret += t; + + ret /= (1 << out_div); + return (ret); +} + +static void +ar934x_chip_detect_sys_frequency(void) +{ + uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; + uint32_t cpu_pll, ddr_pll; + uint32_t bootstrap; + + bootstrap = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) + u_ar71xx_refclk = 40 * 1000 * 1000; + else + u_ar71xx_refclk = 25 * 1000 * 1000; + + pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG); + if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { + out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & + AR934X_SRIF_DPLL2_OUTDIV_MASK; + pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG); + nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & + AR934X_SRIF_DPLL1_NINT_MASK; + nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; + ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & + AR934X_SRIF_DPLL1_REFDIV_MASK; + frac = 1 << 18; + } else { + pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG); + out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR934X_PLL_CPU_CONFIG_NINT_MASK; + nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_CPU_CONFIG_NFRAC_MASK; + frac = 1 << 6; + } + + cpu_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint, + nfrac, frac, out_div); + + pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG); + if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { + out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & + AR934X_SRIF_DPLL2_OUTDIV_MASK; + pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG); + nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & + AR934X_SRIF_DPLL1_NINT_MASK; + nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; + ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & + AR934X_SRIF_DPLL1_REFDIV_MASK; + frac = 1 << 18; + } else { + pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG); + out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & + AR934X_PLL_DDR_CONFIG_NINT_MASK; + nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_DDR_CONFIG_NFRAC_MASK; + frac = 1 << 10; + } + + ddr_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint, + nfrac, frac, out_div); + + clk_ctrl = ATH_READ_REG(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + + postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & + AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; + + if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) + u_ar71xx_cpu_freq = u_ar71xx_refclk; + else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) + u_ar71xx_cpu_freq = cpu_pll / (postdiv + 1); + else + u_ar71xx_cpu_freq = ddr_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & + AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; + + if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) + u_ar71xx_ddr_freq = u_ar71xx_refclk; + else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) + u_ar71xx_ddr_freq = ddr_pll / (postdiv + 1); + else + u_ar71xx_ddr_freq = cpu_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & + AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; + + if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) + u_ar71xx_ahb_freq = u_ar71xx_refclk; + else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) + u_ar71xx_ahb_freq = ddr_pll / (postdiv + 1); + else + u_ar71xx_ahb_freq = cpu_pll / (postdiv + 1); + + u_ar71xx_wdt_freq = u_ar71xx_refclk; + u_ar71xx_uart_freq = u_ar71xx_refclk; +} + +static void +ar934x_chip_device_stop(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE); + ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg | mask); +} + +static void +ar934x_chip_device_start(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE); + ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg & ~mask); +} + +static int +ar934x_chip_device_stopped(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE); + return ((reg & mask) == mask); +} + +static void +ar934x_chip_set_mii_speed(uint32_t unit, uint32_t speed) +{ + + /* XXX TODO */ + return; +} + +/* + * XXX TODO !! + */ +static void +ar934x_chip_set_pll_ge(int unit, int speed, uint32_t pll) +{ + + switch (unit) { + case 0: + /* XXX TODO */ + break; + case 1: + /* XXX TODO */ + break; + default: + printf("%s: invalid PLL set for arge unit: %d\n", + __func__, unit); + return; + } +} + +static void +ar934x_chip_ddr_flush_ge(int unit) +{ + + switch (unit) { + case 0: + ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0); + break; + case 1: + ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1); + break; + default: + printf("%s: invalid DDR flush for arge unit: %d\n", + __func__, unit); + return; + } +} + +static void +ar934x_chip_ddr_flush_ip2(void) +{ + + ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC); +} + +static uint32_t +ar934x_chip_get_eth_pll(unsigned int mac, int speed) +{ +#if 0 + uint32_t pll; + + switch (speed) { + case 10: + pll = AR933X_PLL_VAL_10; + break; + case 100: + pll = AR933X_PLL_VAL_100; + break; + case 1000: + pll = AR933X_PLL_VAL_1000; + break; + default: + printf("%s%d: invalid speed %d\n", __func__, mac, speed); + pll = 0; + } + return (pll); +#endif + return (0); +} + +static void +ar934x_chip_init_usb_peripheral(void) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP); + if (reg & AR934X_BOOTSTRAP_USB_MODE_DEVICE) + return; + + ar71xx_device_stop(AR934X_RESET_USBSUS_OVERRIDE); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_USB_PHY); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_USB_PHY_ANALOG); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_USB_HOST); + DELAY(100); +} + +struct ar71xx_cpu_def ar934x_chip_def = { + &ar934x_chip_detect_mem_size, + &ar934x_chip_detect_sys_frequency, + &ar934x_chip_device_stop, + &ar934x_chip_device_start, + &ar934x_chip_device_stopped, + &ar934x_chip_set_pll_ge, + &ar934x_chip_set_mii_speed, + &ar71xx_chip_set_mii_if, + &ar934x_chip_ddr_flush_ge, + &ar934x_chip_get_eth_pll, + &ar934x_chip_ddr_flush_ip2, + &ar934x_chip_init_usb_peripheral +}; Property changes on: sys/mips/atheros/ar934x_chip.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Index: sys/mips/atheros/ar71xx_chip.c =================================================================== --- sys/mips/atheros/ar71xx_chip.c (revision 253313) +++ sys/mips/atheros/ar71xx_chip.c (working copy) @@ -78,6 +78,8 @@ uint32_t u_ar71xx_cpu_freq; uint32_t u_ar71xx_ahb_freq; uint32_t u_ar71xx_ddr_freq; +uint32_t u_ar71xx_uart_freq; +uint32_t u_ar71xx_wdt_freq; uint32_t u_ar71xx_refclk; static void @@ -107,6 +109,8 @@ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; + u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; + u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; } /* Index: sys/mips/atheros/ar91xx_chip.c =================================================================== --- sys/mips/atheros/ar91xx_chip.c (revision 253313) +++ sys/mips/atheros/ar91xx_chip.c (working copy) @@ -84,6 +84,8 @@ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; + u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; + u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; } static void Index: sys/mips/atheros/ar934x_chip.h =================================================================== --- sys/mips/atheros/ar934x_chip.h (revision 0) +++ sys/mips/atheros/ar934x_chip.h (working copy) @@ -0,0 +1,34 @@ +/*- + * Copyright (c) 2013 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +#ifndef __AR934X_CHIP_H__ +#define __AR934X_CHIP_H__ + +extern struct ar71xx_cpu_def ar934x_chip_def; + +#endif Property changes on: sys/mips/atheros/ar934x_chip.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H Index: sys/mips/atheros/uart_cpu_ar933x.c =================================================================== --- sys/mips/atheros/uart_cpu_ar933x.c (revision 253313) +++ sys/mips/atheros/uart_cpu_ar933x.c (working copy) @@ -58,7 +58,7 @@ { uint64_t freq; - freq = ar71xx_refclk(); + freq = ar71xx_uart_freq(); di->ops = uart_getops(&uart_ar933x_class); di->bas.chan = 0; Index: sys/mips/atheros/uart_bus_ar71xx.c =================================================================== --- sys/mips/atheros/uart_bus_ar71xx.c (revision 253313) +++ sys/mips/atheros/uart_bus_ar71xx.c (working copy) @@ -70,7 +70,7 @@ struct uart_softc *sc; uint64_t freq; - freq = ar71xx_ahb_freq(); + freq = ar71xx_uart_freq(); sc = device_get_softc(dev); sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); Index: sys/mips/atheros/ar71xx_cpudef.h =================================================================== --- sys/mips/atheros/ar71xx_cpudef.h (revision 253313) +++ sys/mips/atheros/ar71xx_cpudef.h (working copy) @@ -121,10 +121,14 @@ extern uint32_t u_ar71xx_cpu_freq; extern uint32_t u_ar71xx_ahb_freq; extern uint32_t u_ar71xx_ddr_freq; +extern uint32_t u_ar71xx_uart_freq; +extern uint32_t u_ar71xx_wdt_freq; static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; } static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; } static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; } static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; } - +static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; } +static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; } + #endif Index: sys/mips/atheros/uart_bus_ar933x.c =================================================================== --- sys/mips/atheros/uart_bus_ar933x.c (revision 253313) +++ sys/mips/atheros/uart_bus_ar933x.c (working copy) @@ -72,7 +72,7 @@ struct uart_softc *sc; uint64_t freq; - freq = ar71xx_refclk(); + freq = ar71xx_uart_freq(); sc = device_get_softc(dev); sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); Index: sys/mips/atheros/ar71xx_gpio.c =================================================================== --- sys/mips/atheros/ar71xx_gpio.c (revision 253313) +++ sys/mips/atheros/ar71xx_gpio.c (working copy) @@ -50,6 +50,7 @@ #include #include #include +#include #include "gpio_if.h" @@ -90,13 +91,23 @@ static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask) { - GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask); + if (ar71xx_soc == AR71XX_SOC_AR9341 || + ar71xx_soc == AR71XX_SOC_AR9342 || + ar71xx_soc == AR71XX_SOC_AR9344) + GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask); + else + GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask); } static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask) { - GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask); + if (ar71xx_soc == AR71XX_SOC_AR9341 || + ar71xx_soc == AR71XX_SOC_AR9342 || + ar71xx_soc == AR71XX_SOC_AR9344) + GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask); + else + GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask); } static void @@ -141,6 +152,10 @@ case AR71XX_SOC_AR9331: *maxpin = AR933X_GPIO_COUNT - 1; break; + case AR71XX_SOC_AR9341: + case AR71XX_SOC_AR9342: + case AR71XX_SOC_AR9344: + *maxpin = AR934X_GPIO_COUNT - 1; default: *maxpin = AR71XX_GPIO_PINS - 1; } Index: sys/mips/atheros/ar71xx_setup.c =================================================================== --- sys/mips/atheros/ar71xx_setup.c (revision 253313) +++ sys/mips/atheros/ar71xx_setup.c (working copy) @@ -53,6 +53,7 @@ #include #include +#include #include @@ -62,6 +63,7 @@ #include #include #include +#include #define AR71XX_SYS_TYPE_LEN 128 @@ -158,6 +160,30 @@ ar71xx_cpu_ops = &ar933x_chip_def; break; + case REV_ID_MAJOR_AR9341: + minor = 0; + rev = (id & AR934X_REV_ID_REVISION_MASK); + chip = "9341"; + ar71xx_soc = AR71XX_SOC_AR9341; + ar71xx_cpu_ops = &ar934x_chip_def; + break; + + case REV_ID_MAJOR_AR9342: + minor = 0; + rev = (id & AR934X_REV_ID_REVISION_MASK); + chip = "9342"; + ar71xx_soc = AR71XX_SOC_AR9342; + ar71xx_cpu_ops = &ar934x_chip_def; + break; + + case REV_ID_MAJOR_AR9344: + minor = 0; + rev = (id & AR934X_REV_ID_REVISION_MASK); + chip = "9344"; + ar71xx_soc = AR71XX_SOC_AR9344; + ar71xx_cpu_ops = &ar934x_chip_def; + break; + default: panic("ar71xx: unknown chip id:0x%08x\n", id); } Index: sys/mips/atheros/ar724x_chip.c =================================================================== --- sys/mips/atheros/ar724x_chip.c (revision 253313) +++ sys/mips/atheros/ar724x_chip.c (working copy) @@ -90,6 +90,8 @@ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; + u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; + u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; } static void