Index: contrib/binutils/ld/emulparams/armelf_fbsd.sh =================================================================== RCS file: /cognet/ncvs/src/contrib/binutils/ld/emulparams/armelf_fbsd.sh,v retrieving revision 1.1.1.1 diff -u -p -r1.1.1.1 armelf_fbsd.sh --- contrib/binutils/ld/emulparams/armelf_fbsd.sh 22 Feb 2002 04:18:15 -0000 1.1.1.1 +++ contrib/binutils/ld/emulparams/armelf_fbsd.sh 21 Jul 2006 12:51:15 -0000 @@ -1,2 +1,7 @@ . ${srcdir}/emulparams/armelf.sh . ${srcdir}/emulparams/elf_fbsd.sh +MAXPAGESIZE=0x8000 +GENERATE_PIE_SCRIPT=yes + +unset STACK_ADDR +unset EMBEDDED Index: contrib/binutils/ld/emulparams/armelfb_fbsd.sh =================================================================== RCS file: contrib/binutils/ld/emulparams/armelfb_fbsd.sh diff -N contrib/binutils/ld/emulparams/armelfb_fbsd.sh --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/binutils/ld/emulparams/armelfb_fbsd.sh 21 Jul 2006 12:52:38 -0000 @@ -0,0 +1,3 @@ +. ${srcdir}/emulparams/armelf_fbsd.sh + +OUTPUT_FORMAT="elf32-bigarm" Index: contrib/gcc/config/arm/arm.md =================================================================== RCS file: /cognet/ncvs/src/contrib/gcc/config/arm/arm.md,v retrieving revision 1.1.1.7 diff -u -p -r1.1.1.7 arm.md --- contrib/gcc/config/arm/arm.md 3 Jun 2005 03:28:42 -0000 1.1.1.7 +++ contrib/gcc/config/arm/arm.md 29 Aug 2005 12:39:39 -0000 @@ -8836,12 +8836,12 @@ ldm[2] = operands[4]; } if (GET_CODE (XEXP (operands[2], 0)) != REG) - val1 = INTVAL (XEXP (XEXP (operands[2], 0), 1)); + val1 = INTVAL (XEXP (XEXP (operands[2], 0), 1)); if (GET_CODE (XEXP (operands[3], 0)) != REG) - val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); + val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); arith[0] = operands[0]; arith[3] = operands[1]; - if (val1 < val2) + if (val1 <= val2) { arith[1] = ldm[1]; arith[2] = ldm[2]; @@ -8871,7 +8871,7 @@ else output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); } - else + else if (val2) { ldm[0] = XEXP (operands[2], 0); if (val1 < val2) @@ -8879,6 +8879,14 @@ else output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); } + else { + ldm[0] = operands[0]; + ldm[1] = XEXP(operands[2], 0); + output_asm_insn(\"ldr\\t%0, [%1]\", ldm); + ldm[0] = operands[4]; + ldm[1] = XEXP(operands[3], 0); + output_asm_insn(\"ldr\\t%0, [%1]\", ldm); + } output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith); return \"\"; }" Index: contrib/gcc/config/arm/freebsd.h =================================================================== RCS file: /cognet/ncvs/src/contrib/gcc/config/arm/freebsd.h,v retrieving revision 1.1.1.3 diff -u -p -r1.1.1.3 freebsd.h --- contrib/gcc/config/arm/freebsd.h 28 Jul 2004 03:11:35 -0000 1.1.1.3 +++ contrib/gcc/config/arm/freebsd.h 21 Jul 2006 00:50:25 -0000 @@ -22,7 +22,10 @@ #undef SUBTARGET_EXTRA_SPECS #define SUBTARGET_EXTRA_SPECS \ - { "fbsd_dynamic_linker", FBSD_DYNAMIC_LINKER } + { "fbsd_dynamic_linker", FBSD_DYNAMIC_LINKER }, \ + { "subtarget_extra_asm_spec", SUBTARGET_EXTRA_ASM_SPEC }, \ + { "subtarget_asm_float_spec", SUBTARGET_ASM_FLOAT_SPEC } + #undef SUBTARGET_CPP_SPEC #define SUBTARGET_CPP_SPEC FBSD_CPP_SPEC @@ -39,7 +42,8 @@ %{rdynamic:-export-dynamic} \ %{!dynamic-linker:-dynamic-linker %(fbsd_dynamic_linker) }} \ %{static:-Bstatic}} \ - %{symbolic:-Bsymbolic}" + %{symbolic:-Bsymbolic} \ + %{mbig-endian:-EB} %{mlittle-endian:-EL}" /************************[ Target stuff ]***********************************/ @@ -67,3 +71,80 @@ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (FreeBSD/StrongARM ELF)"); + +#ifndef TARGET_ENDIAN_DEFAULT +#define TARGET_ENDIAN_DEFAULT 0 +#endif + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT \ + (ARM_FLAG_APCS_32 \ + | ARM_FLAG_SOFT_FLOAT \ + | ARM_FLAG_APCS_FRAME \ + | ARM_FLAG_ATPCS \ + | ARM_FLAG_VFP \ + | ARM_FLAG_MMU_TRAPS \ + | TARGET_ENDIAN_DEFAULT) + +#undef TYPE_OPERAND_FMT +#define TYPE_OPERAND_FMT "%%%s" + +#undef SUBTARGET_EXTRA_ASM_SPEC +#define SUBTARGET_EXTRA_ASM_SPEC \ + "-matpcs %{fpic|fpie:-k} %{fPIC|fPIE:-k}" + + /* Default floating point model is soft-VFP. + * FIXME: -mhard-float currently implies FPA. */ +#undef SUBTARGET_ASM_FLOAT_SPEC +#define SUBTARGET_ASM_FLOAT_SPEC \ + "%{mhard-float:-mfpu=fpa} \ + %{msoft-float:-mfpu=softvfp} \ + %{!mhard-float: \ + %{!msoft-float:-mfpu=softvfp}}" + + +/* FreeBSD does its profiling differently to the Acorn compiler. We + don't need a word following the mcount call; and to skip it + requires either an assembly stub or use of fomit-frame-pointer when + compiling the profiling functions. Since we break Acorn CC + compatibility below a little more won't hurt. */ + +#undef ARM_FUNCTION_PROFILER +#define ARM_FUNCTION_PROFILER(STREAM,LABELNO) \ +{ \ + asm_fprintf (STREAM, "\tmov\t%Rip, %Rlr\n"); \ + asm_fprintf (STREAM, "\tbl\t_mcount%s\n", \ + NEED_PLT_RELOC ? "(PLT)" : ""); \ +} + +/* Emit code to set up a trampoline and synchronize the caches. */ +#undef INITIALIZE_TRAMPOLINE +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +do \ + { \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ + (CXT)); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ + (FNADDR)); \ + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \ + 0, VOIDmode, 2, TRAMP, Pmode, \ + plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \ + } \ +while (0) + +/* Clear the instruction cache from `BEG' to `END'. This makes a + call to the ARM_SYNC_ICACHE architecture specific syscall. */ +#define CLEAR_INSN_CACHE(BEG, END) \ +do \ + { \ + extern int sysarch(int number, void *args); \ + struct \ + { \ + unsigned int addr; \ + int len; \ + } s; \ + s.addr = (unsigned int)(BEG); \ + s.len = (END) - (BEG); \ + (void) sysarch (0, &s); \ + } \ +while (0) Index: contrib/gdb/gdb/armfbsd-nat.c =================================================================== RCS file: contrib/gdb/gdb/armfbsd-nat.c diff -N contrib/gdb/gdb/armfbsd-nat.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/gdb/gdb/armfbsd-nat.c 19 Jul 2006 10:24:46 -0000 @@ -0,0 +1,516 @@ + /* Native-dependent code for BSD Unix running on ARM's, for GDB. + Copyright 1988, 1989, 1991, 1992, 1994, 1996, 1999, 2002 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" + +#ifndef FETCH_INFERIOR_REGISTERS +#ifndef CROSS_DEBUGGER +#error Not FETCH_INFERIOR_REGISTERS +#endif +#endif /* !FETCH_INFERIOR_REGISTERS */ + +#include "arm-tdep.h" + +#include +#include +#ifndef CROSS_DEBUGGER +#include +#include +#endif +#include "inferior.h" +#include "regcache.h" +#include "gdbcore.h" + +extern int arm_apcs_32; + +#ifdef CROSS_DEBUGGER +struct reg { + unsigned int r[13]; + unsigned int r_sp; + unsigned int r_lr; + unsigned int r_pc; + unsigned int r_cpsr; +}; + +typedef struct fp_extended_precision { + u_int32_t fp_exponent; + u_int32_t fp_mantissa_hi; + u_int32_t fp_mantissa_lo; +} fp_extended_precision_t; + +typedef struct fp_extended_precision fp_reg_t; + +struct fpreg { + unsigned int fpr_fpsr; + fp_reg_t fpr[8]; +}; +#endif + +void +supply_gregset (struct reg *gregset) +{ + int regno; + CORE_ADDR r_pc; + + /* Integer registers. */ + for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++) + supply_register (regno, (char *) &gregset->r[regno]); + + supply_register (ARM_SP_REGNUM, (char *) &gregset->r_sp); + supply_register (ARM_LR_REGNUM, (char *) &gregset->r_lr); + /* This is ok: we're running native... */ + r_pc = ADDR_BITS_REMOVE (gregset->r_pc); + supply_register (ARM_PC_REGNUM, (char *) &r_pc); + + if (arm_apcs_32) + supply_register (ARM_PS_REGNUM, (char *) &gregset->r_cpsr); + else + supply_register (ARM_PS_REGNUM, (char *) &gregset->r_pc); +} + +void +supply_fpregset (struct fpreg *fparegset) +{ + int regno; + + for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) + supply_register + (regno, (char *) &fparegset->fpr[regno - ARM_F0_REGNUM]); + + supply_register (ARM_FPS_REGNUM, (char *) &fparegset->fpr_fpsr); +} + +static void +fetch_register (int regno) +{ + struct reg inferior_registers; +#ifndef CROSS_DEBUGGER + int ret; + + ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_registers, 0); + + if (ret < 0) + { + warning ("unable to fetch general register"); + return; + } +#endif + + switch (regno) + { + case ARM_SP_REGNUM: + supply_register (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp); + break; + + case ARM_LR_REGNUM: + supply_register (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr); + break; + + case ARM_PC_REGNUM: + /* This is ok: we're running native... */ + inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc); + supply_register (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc); + break; + + case ARM_PS_REGNUM: + if (arm_apcs_32) + supply_register (ARM_PS_REGNUM, (char *) &inferior_registers.r_cpsr); + else + supply_register (ARM_PS_REGNUM, (char *) &inferior_registers.r_pc); + break; + + default: + supply_register (regno, (char *) &inferior_registers.r[regno]); + break; + } +} + +static void +fetch_regs (void) +{ + struct reg inferior_registers; +#ifndef CROSS_DEBUGGER + int ret; +#endif + int regno; + +#ifndef CROSS_DEBUGGER + ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_registers, 0); + + if (ret < 0) + { + warning ("unable to fetch general registers"); + return; + } +#endif + + supply_gregset (&inferior_registers); +} + +static void +fetch_fp_register (int regno) +{ + struct fpreg inferior_fp_registers; +#ifndef CROSS_DEBUGGER + int ret; + + ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); + + if (ret < 0) + { + warning ("unable to fetch floating-point register"); + return; + } +#endif + + switch (regno) + { + case ARM_FPS_REGNUM: + supply_register (ARM_FPS_REGNUM, + (char *) &inferior_fp_registers.fpr_fpsr); + break; + + default: + supply_register + (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); + break; + } +} + +static void +fetch_fp_regs (void) +{ + struct fpreg inferior_fp_registers; +#ifndef CROSS_DEBUGGER + int ret; +#endif + int regno; + +#ifndef CROSS_DEBUGGER + ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); + + if (ret < 0) + { + warning ("unable to fetch general registers"); + return; + } +#endif + + supply_fpregset (&inferior_fp_registers); +} + +void +fetch_inferior_registers (int regno) +{ + if (regno >= 0) + { + if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM) + fetch_register (regno); + else + fetch_fp_register (regno); + } + else + { + fetch_regs (); + fetch_fp_regs (); + } +} + + +static void +store_register (int regno) +{ + struct reg inferior_registers; +#ifndef CROSS_DEBUGGER + int ret; + + ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_registers, 0); + + if (ret < 0) + { + warning ("unable to fetch general registers"); + return; + } +#endif + + switch (regno) + { + case ARM_SP_REGNUM: + regcache_collect (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp); + break; + + case ARM_LR_REGNUM: + regcache_collect (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr); + break; + + case ARM_PC_REGNUM: + if (arm_apcs_32) + regcache_collect (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc); + else + { + unsigned pc_val; + + regcache_collect (ARM_PC_REGNUM, (char *) &pc_val); + + pc_val = ADDR_BITS_REMOVE (pc_val); + inferior_registers.r_pc + ^= ADDR_BITS_REMOVE (inferior_registers.r_pc); + inferior_registers.r_pc |= pc_val; + } + break; + + case ARM_PS_REGNUM: + if (arm_apcs_32) + regcache_collect (ARM_PS_REGNUM, (char *) &inferior_registers.r_cpsr); + else + { + unsigned psr_val; + + regcache_collect (ARM_PS_REGNUM, (char *) &psr_val); + + psr_val ^= ADDR_BITS_REMOVE (psr_val); + inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc); + inferior_registers.r_pc |= psr_val; + } + break; + + default: + regcache_collect (regno, (char *) &inferior_registers.r[regno]); + break; + } + +#ifndef CROSS_DEBUGGER + ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_registers, 0); + + if (ret < 0) + warning ("unable to write register %d to inferior", regno); +#endif +} + +static void +store_regs (void) +{ + struct reg inferior_registers; + int ret; + int regno; + + + for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++) + regcache_collect (regno, (char *) &inferior_registers.r[regno]); + + regcache_collect (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp); + regcache_collect (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr); + + if (arm_apcs_32) + { + regcache_collect (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc); + regcache_collect (ARM_PS_REGNUM, (char *) &inferior_registers.r_cpsr); + } + else + { + unsigned pc_val; + unsigned psr_val; + + regcache_collect (ARM_PC_REGNUM, (char *) &pc_val); + regcache_collect (ARM_PS_REGNUM, (char *) &psr_val); + + pc_val = ADDR_BITS_REMOVE (pc_val); + psr_val ^= ADDR_BITS_REMOVE (psr_val); + + inferior_registers.r_pc = pc_val | psr_val; + } + +#ifndef CROSS_DEBUGGER + ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_registers, 0); + + if (ret < 0) + warning ("unable to store general registers"); +#endif +} + +static void +store_fp_register (int regno) +{ + struct fpreg inferior_fp_registers; +#ifndef CROSS_DEBUGGER + int ret; + + ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); + + if (ret < 0) + { + warning ("unable to fetch floating-point registers"); + return; + } +#endif + + switch (regno) + { + case ARM_FPS_REGNUM: + regcache_collect (ARM_FPS_REGNUM, + (char *) &inferior_fp_registers.fpr_fpsr); + break; + + default: + regcache_collect + (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); + break; + } + +#ifndef CROSS_DEBUGGER + ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); + + if (ret < 0) + warning ("unable to write register %d to inferior", regno); +#endif +} + +static void +store_fp_regs (void) +{ + struct fpreg inferior_fp_registers; + int ret; + int regno; + + + for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) + regcache_collect + (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); + + regcache_collect (ARM_FPS_REGNUM, (char *) &inferior_fp_registers.fpr_fpsr); + +#ifndef CROSS_DEBUGGER + ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); + + if (ret < 0) + warning ("unable to store floating-point registers"); +#endif +} + +void +store_inferior_registers (int regno) +{ + if (regno >= 0) + { + if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM) + store_register (regno); + else + store_fp_register (regno); + } + else + { + store_regs (); + store_fp_regs (); + } +} + + +struct md_core +{ + struct reg intreg; + struct fpreg freg; +}; + +static void +fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, + int which, CORE_ADDR ignore) +{ + struct md_core *core_reg = (struct md_core *) core_reg_sect; + int regno; + CORE_ADDR r_pc; + + supply_gregset (&core_reg->intreg); + supply_fpregset (&core_reg->freg); +} + +static void +fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size, + int which, CORE_ADDR ignore) +{ + struct reg gregset; + struct fpreg fparegset; + + switch (which) + { + case 0: /* Integer registers. */ + if (core_reg_size != sizeof (struct reg)) + warning ("wrong size of register set in core file"); + else + { + /* The memcpy may be unnecessary, but we can't really be sure + of the alignment of the data in the core file. */ + memcpy (&gregset, core_reg_sect, sizeof (gregset)); + supply_gregset (&gregset); + } + break; + + case 2: + if (core_reg_size != sizeof (struct fpreg)) + warning ("wrong size of FPA register set in core file"); + else + { + /* The memcpy may be unnecessary, but we can't really be sure + of the alignment of the data in the core file. */ + memcpy (&fparegset, core_reg_sect, sizeof (fparegset)); + supply_fpregset (&fparegset); + } + break; + + default: + /* Don't know what kind of register request this is; just ignore it. */ + break; + } +} + +static struct core_fns arm_freebsd_core_fns = +{ + bfd_target_unknown_flavour, /* core_flovour. */ + default_check_format, /* check_format. */ + default_core_sniffer, /* core_sniffer. */ + fetch_core_registers, /* core_read_registers. */ + NULL +}; + +static struct core_fns arm_freebsd_elfcore_fns = +{ + bfd_target_elf_flavour, /* core_flovour. */ + default_check_format, /* check_format. */ + default_core_sniffer, /* core_sniffer. */ + fetch_elfcore_registers, /* core_read_registers. */ + NULL +}; + +void +_initialize_arm_fbsdnat (void) +{ + add_core_fns (&arm_freebsd_core_fns); + add_core_fns (&arm_freebsd_elfcore_fns); +} Index: contrib/gdb/gdb/armfbsd-tdep.c =================================================================== RCS file: contrib/gdb/gdb/armfbsd-tdep.c diff -N contrib/gdb/gdb/armfbsd-tdep.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/gdb/gdb/armfbsd-tdep.c 29 Aug 2005 12:39:39 -0000 @@ -0,0 +1,67 @@ +/* Target-specific functions for ARM running under NetBSD. + Copyright 2002, 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "osabi.h" + +#include "arch-utils.h" +#include "arm-tdep.h" +#include "solib-svr4.h" + +/* Description of the longjmp buffer. */ +#define ARM_FBSD_JB_PC 24 +#define ARM_FBSD_JB_ELEMENT_SIZE INT_REGISTER_SIZE + +static void +arm_freebsd_init_abi_common (struct gdbarch_info info, + struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + tdep->lowest_pc = 0x8000; + + tdep->jb_pc = ARM_FBSD_JB_PC; + tdep->jb_elt_size = ARM_FBSD_JB_ELEMENT_SIZE; +} + +static void +arm_freebsd_elf_init_abi (struct gdbarch_info info, + struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + arm_freebsd_init_abi_common (info, gdbarch); + + /* FreeBSD ELF uses SVR4-style shared libraries. */ + set_gdbarch_in_solib_call_trampoline + (gdbarch, generic_in_solib_call_trampoline); + set_solib_svr4_fetch_link_map_offsets + (gdbarch, svr4_ilp32_fetch_link_map_offsets); + + tdep->fp_model = ARM_FLOAT_SOFT_VFP; +} + + +void +_initialize_armfbsd_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_FREEBSD_ELF, + arm_freebsd_elf_init_abi); +} Index: contrib/gdb/gdb/config/arm/fbsd.mh =================================================================== RCS file: contrib/gdb/gdb/config/arm/fbsd.mh diff -N contrib/gdb/gdb/config/arm/fbsd.mh --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/gdb/gdb/config/arm/fbsd.mh 7 Jul 2006 21:29:38 -0000 @@ -0,0 +1,4 @@ +# Host ARM running FreeBSD +NATDEPFILES= fork-child.o infptrace.o inftarg.o corelow.o armfbsd-nat.o +XM_FILE=xm-fbsd.h +NAT_FILE=nm-fbsd.h Index: contrib/gdb/gdb/config/arm/fbsd.mt =================================================================== RCS file: contrib/gdb/gdb/config/arm/fbsd.mt diff -N contrib/gdb/gdb/config/arm/fbsd.mt --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/gdb/gdb/config/arm/fbsd.mt 29 Aug 2005 12:39:39 -0000 @@ -0,0 +1,3 @@ +# Target: ARM running FreeBSD +TDEPFILES= arm-tdep.o armfbsd-tdep.o fbsd-tdep.o solib.o solib-svr4.o +TM_FILE=tm-fbsd.h Index: contrib/gdb/gdb/config/arm/nm-fbsd.h =================================================================== RCS file: contrib/gdb/gdb/config/arm/nm-fbsd.h diff -N contrib/gdb/gdb/config/arm/nm-fbsd.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/gdb/gdb/config/arm/nm-fbsd.h 29 Aug 2005 12:39:39 -0000 @@ -0,0 +1,30 @@ +/* Native-dependent definitions for ARM running NetBSD, for GDB. + Copyright 1986, 1987, 1989, 1992, 1994, 1999 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef NM_FBSD_H +#define NM_FBSD_H + +/* Type of the third argument to the `ptrace' system call. */ +#define PTRACE_ARG3_TYPE caddr_t + +/* Override copies of {fetch,store}_inferior_registers in `infptrace.c'. */ +#define FETCH_INFERIOR_REGISTERS + +#endif /* NM_NBSD_H */ Index: contrib/gdb/gdb/config/arm/tm-fbsd.h =================================================================== RCS file: contrib/gdb/gdb/config/arm/tm-fbsd.h diff -N contrib/gdb/gdb/config/arm/tm-fbsd.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/gdb/gdb/config/arm/tm-fbsd.h 29 Aug 2005 12:39:39 -0000 @@ -0,0 +1,26 @@ +/* Macro definitions for ARM running under NetBSD. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef TM_FBSD_H +#define TM_FBSD_H + +#include "solib.h" + +#endif /* TM_FBSD_H */ Index: contrib/gdb/gdb/config/arm/xm-fbsd.h =================================================================== RCS file: contrib/gdb/gdb/config/arm/xm-fbsd.h diff -N contrib/gdb/gdb/config/arm/xm-fbsd.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ contrib/gdb/gdb/config/arm/xm-fbsd.h 29 Aug 2005 12:39:39 -0000 @@ -0,0 +1,20 @@ +/* Parameters for execution on an ARM running NetBSD, for GDB. + Copyright 1994 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ +